example.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter is
	Port (	Clk 		: in  STD_LOGIC;
		Enable		: in  STD_LOGIC;
		UpDown	: in  STD_LOGIC;
		Reset 		: in  STD_LOGIC;
		Output		: out  STD_LOGIC_VECTOR (6 downto 0));
end Counter;

architecture Behavioral of Counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
	process(Clk, Reset, Enable, UpDown)
	begin
		if Reset = '1' then
			pre_count <= "0000";
		elsif (Clk='1' and Clk'event) then
			if Enable='1' then
				if UpDown='1' then
					pre_count <= pre_count + "1";
				else
					pre_count <= pre_count - "1";
				end if;
			end if;
		end if;
	end process;  
	Output <=  "1111110" when pre_count ="0000" else
					"0110000" when pre_count ="0001" else
					"1101101" when pre_count ="0010" else
					"1111001" when pre_count ="0011" else
					"0110011" when pre_count ="0100" else
					"1011011" when pre_count ="0101" else
					"1011111" when pre_count ="0110" else
					"1110000" when pre_count ="0111" else
					"1111111" when pre_count ="1000" else
					"1111011" when pre_count ="1001" else
					"1110111" when pre_count ="1010" else
					"0011111" when pre_count ="1011" else
					"1001110" when pre_count ="1100" else
					"0111101" when pre_count ="1101" else
					"1001111" when pre_count ="1110" else
					"1000111" ;
end Behavioral;