Created
March 19, 2022 13:51
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[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x100070A0, val: 0x2FF | |
[RGU] rgu_update_reg: 1, bits: 0x200, addr: 0x100070A0, val: 0x2FF | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL(0x200F1) | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL2(0x2FF) | |
[RGU] mtk_wdt_init: MTK_WDT_LATCH_CTL(0xB871) | |
[RGU] mtk_wdt_init: MTK_WDT_REQ_MODE(3F0032), MTK_WDT_REQ_IRQ_EN(3F0032) | |
Enter mtk_kpd_gpio_set! | |
after set KP enable: KP_SEL = 0x0 ! | |
[RTC] irqsta = 0x1, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x80, spar1 = 0x800 | |
[RTC] new_spare0 = 0x4000, new_spare1 = 0x5001, new_spare2 = 0x1, new_spare3 = 0x1 | |
[RTC] bbpu = 0x1, con = 0x486, cali = 0x2020, osc32con = | |
[PLFM] Init Boot Device: OK(0) | |
EMI_MPU_CTRL=0 1st | |
EMI_MPU_CTRL=0 2nd | |
[RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 | |
[RGU] WDT DDR reserve mode FAIL! 200F1 | |
[RGU] DDR RESERVE Success 0 | |
[RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]cold boot | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Bypass_TXWINDOW=1 | |
[CH0][RK0][1600][CBT] Best CA Vref 18, Window Min 57 at CA4, Window Sum 349 | |
[CH0][RK1][1600][CBT] Best CA Vref 18, Window Min 58 at CA4, Window Sum 355 | |
[CH0][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ6, Window Sum 420 | |
[CH0][RK0][1600][RX] Best Vref 30, Window Min 49 at DQ8, Window Sum 850 | |
[CH0][RK1][1600][TX] Best Vref 15, Window Min 25 at DQ14, Window Sum 426 | |
[CH1][RK0][1600][CBT] Best CA V▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x152A (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x19 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x196C (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x1A08 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x48 | |
[PMIC]PONSTS[0xC]=0x6 | |
[PMIC]POFFSTS[0xE]=0x1 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x1200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] DDLO_RSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x1221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] enable_dcxo first con = 0x486, osc32con = 0xDE6E, sec = 0x2020 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3986 | |
[RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD | |
[RTC] bbpu = 0x1, con = 0x486, osc32con = 0xDE6E, sec = 0x2020, yea = 0xC102 | |
[RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 | |
[RTC] rtc_boot_check Writeif_unlock | |
[RTC]switch to dcxo | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=811 | |
[RTC] EOSC_Cali: val=0x32B | |
[RTC] get_frequency_meter: input=0x7, ouput=701 | |
[RTC] EOSC_Cali: val=0x2BD | |
[RTC] get_frequency_meter: input=0xB, ouput=758 | |
[RTC] EOSC_Cali: val=0x2F6 | |
[RTC] get_frequency_meter: input=0xD, ouput=784 | |
[RTC] EOSC_Cali: val=0x310 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=784 | |
[RTC] get_frequency_meter: input=0xE, ouput=796 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x100070A0, val: 0x2FF | |
[RGU] rgu_update_reg: 1, bits: 0x200, addr: 0x100070A0, val: 0x2FF | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL(0x200F1) | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL2(0x2FF) | |
[RGU] mtk_wdt_init: MTK_WDT_LATCH_CTL(0xB871) | |
[RGU] mtk_wdt_init: MTK_WDT_REQ_MODE(3F0032), MTK_WDT_REQ_IRQ_EN(3F0032) | |
Enter mtk_kpd_gpio_set! | |
after set KP enable: KP_SEL = 0x0 ! | |
[RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x80, spar1 = 0x800 | |
[RTC] new_spare0 = 0x4000, new_spare1 = 0x5001, new_spare2 = 0x1, new_spare3 = 0x1 | |
[RTC] bbpu = 0x1, con = 0x486, cali = 0x2020, osc32con = | |
[PLFM] Init Boot Device: OK(0) | |
EMI_MPU_CTRL=0 1st | |
EMI_MPU_CTRL=0 2nd | |
[RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 | |
[RGU] WDT DDR reserve mode FAIL! 200F1 | |
[RGU] DDR RESERVE Success 0 | |
[RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]cold boot | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Bypass_TXWINDOW=1 | |
[CH0][RK0][1600][CBT] Best CA Vref 18, Window Min 57 at CA4, Window Sum 347 | |
[CH0][RK1][1600][CBT] Best CA Vref 18, Window Min 58 at CA4, Window Sum 356 | |
[CH0][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ6, Window Sum 420 | |
[CH0][RK0][1600][RX] Best Vref 30, Window Min 49 at DQ8, Window Sum 850 | |
[CH0][RK1][1600][TX] Best Vref 15, Window Min 25 at DQ14, Window Sum 426 | |
[CH1][RK0][1600][CBT] Best CAK▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x152A (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x19 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x196C (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x1A08 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x48 | |
[PMIC]PONSTS[0xC]=0x6 | |
[PMIC]POFFSTS[0xE]=0x1 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x1200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] DDLO_RSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x1221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] enable_dcxo first con = 0x486, osc32con = 0xDE6E, sec = 0x2020 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3986 | |
[RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD | |
[RTC] bbpu = 0x1, con = 0x486, osc32con = 0xDE6E, sec = 0x2020, yea = 0xC102 | |
[RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 | |
[RTC] rtc_boot_check Writeif_unlock | |
[RTC]switch to dcxo | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=811 | |
[RTC] EOSC_Cali: val=0x32B | |
[RTC] get_frequency_meter: input=0x7, ouput=700 | |
[RTC] EOSC_Cali: val=0x2BC | |
[RTC] get_frequency_meter: input=0xB, ouput=757 | |
[RTC] EOSC_Cali: val=0x2F5 | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] EOSC_Cali: val=0x30F | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=784 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x100070A0, val: 0x2FF | |
[RGU] rgu_update_reg: 1, bits: 0x200, addr: 0x100070A0, val: 0x2FF | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL(0x200F1) | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL2(0x2FF) | |
[RGU] mtk_wdt_init: MTK_WDT_LATCH_CTL(0xB871) | |
[RGU] mtk_wdt_init: MTK_WDT_REQ_MODE(3F0032), MTK_WDT_REQ_IRQ_EN(3F0032) | |
Enter mtk_kpd_gpio_set! | |
after set KP enable: KP_SEL = 0x0 ! | |
[RTC] irqsta = 0x1, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x80, spar1 = 0x800 | |
[RTC] new_spare0 = 0x4000, new_spare1 = 0x5001, new_spare2 = 0x1, new_spare3 = 0x1 | |
[RTC] bbpu = 0x1, con = 0x486, cali = 0x2020, osc32con = | |
[PLFM] Init Boot Device: OK(0) | |
EMI_MPU_CTRL=0 1st | |
EMI_MPU_CTRL=0 2nd | |
[RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 | |
[RGU] WDT DDR reserve mode FAIL! 200F1 | |
[RGU] DDR RESERVE Success 0 | |
[RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]cold boot | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Bypass_TXWINDOW=1 | |
[CH0][RK0][1600][CBT] Best CA Vref 18, Window Min 57 at CA4, Window Sum 347 | |
[CH0][RK1][1600][CBT] Best CA Vref 18, Window Min 58 at CA4, Window Sum 356 | |
[CH0][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ6, Window Sum 420 | |
[CH0][RK0][1600][RX] Best Vref 30, Window Min 49 at DQ8, Window Sum 850 | |
[CH0][RK1][1600][TX] Best Vref 15, Window Min 25 at DQ14, Window Sum 426 | |
[CH1][RK0][1600][CBT] Best CA ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x152A (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x19 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x196C (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x1A08 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x48 | |
[PMIC]PONSTS[0xC]=0x6 | |
[PMIC]POFFSTS[0xE]=0x1 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x1200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] DDLO_RSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x1221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] enable_dcxo first con = 0x486, osc32con = 0xDE6E, sec = 0x2020 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3985 | |
[RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD | |
[RTC] bbpu = 0x1, con = 0x486, osc32con = 0xDE6E, sec = 0x2020, yea = 0xC102 | |
[RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 | |
[RTC] rtc_boot_check Writeif_unlock | |
[RTC]switch to dcxo | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=812 | |
[RTC] EOSC_Cali: val=0x32C | |
[RTC] get_frequency_meter: input=0x7, ouput=701 | |
[RTC] EOSC_Cali: val=0x2BD | |
[RTC] get_frequency_meter: input=0xB, ouput=756 | |
[RTC] EOSC_Cali: val=0x2F4 | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] EOSC_Cali: val=0x30F | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=784 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x100070A0, val: 0x2FF | |
[RGU] rgu_update_reg: 1, bits: 0x200, addr: 0x100070A0, val: 0x2FF | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL(0x200F1) | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL2(0x2FF) | |
[RGU] mtk_wdt_init: MTK_WDT_LATCH_CTL(0xB871) | |
[RGU] mtk_wdt_init: MTK_WDT_REQ_MODE(3F0032), MTK_WDT_REQ_IRQ_EN(3F0032) | |
Enter mtk_kpd_gpio_set! | |
after set KP enable: KP_SEL = 0x0 ! | |
[RTC] irqsta = 0x1, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x80, spar1 = 0x800 | |
[RTC] new_spare0 = 0x4000, new_spare1 = 0x5001, new_spare2 = 0x1, new_spare3 = 0x1 | |
[RTC] bbpu = 0x1, con = 0x486, cali = 0x2020, osc32con = | |
[PLFM] Init Boot Device: OK(0) | |
EMI_MPU_CTRL=0 1st | |
EMI_MPU_CTRL=0 2nd | |
[RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 | |
[RGU] WDT DDR reserve mode FAIL! 200F1 | |
[RGU] DDR RESERVE Success 0 | |
[RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]cold boot | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Bypass_TXWINDOW=1 | |
[CH0][RK0][1600][CBT] Best CA Vref 18, Window Min 57 at CA4, Window Sum 349 | |
[CH0][RK1][1600][CBT] Best CA Vref 18, Window Min 58 at CA4, Window Sum 356 | |
[CH0][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ6, Window Sum 420 | |
[CH0][RK0][1600][RX] Best Vref 30, Window Min 49 at DQ8, Window Sum 850 | |
[CH0][RK1][1600][TX] Best Vref 15, Window Min 25 at DQ14, Window Sum 426 | |
[CH1][RK0][1600][CBT] Best CA Vref ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x152A (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x19 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x196C (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x1A08 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x48 | |
[PMIC]PONSTS[0xC]=0x4 | |
[PMIC]POFFSTS[0xE]=0x1 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x1200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] DDLO_RSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x1221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] enable_dcxo first con = 0x486, osc32con = 0xDE6E, sec = 0x2020 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3985 | |
[RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD | |
[RTC] bbpu = 0x1, con = 0x486, osc32con = 0xDE6E, sec = 0x2020, yea = 0xC102 | |
[RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 | |
[RTC] rtc_boot_check Writeif_unlock | |
[RTC]switch to dcxo | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=810 | |
[RTC] EOSC_Cali: val=0x32A | |
[RTC] get_frequency_meter: input=0x7, ouput=701 | |
[RTC] EOSC_Cali: val=0x2BD | |
[RTC] get_frequency_meter: input=0xB, ouput=756 | |
[RTC] EOSC_Cali: val=0x2F4 | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] EOSC_Cali: val=0x30F | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=784 | |
[RTC] get_frequency_meter: input=0xE, ouput=796 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]cold boot | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Byp▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x152A (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x19 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x196C (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x1A08 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x48 | |
[PMIC]PONSTS[0xC]=0x6 | |
[PMIC]POFFSTS[0xE]=0x1 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x1200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] DDLO_RSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x1221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] enable_dcxo first con = 0x486, osc32con = 0xDE6E, sec = 0x2020 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3985 | |
[RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD | |
[RTC] bbpu = 0x1, con = 0x486, osc32con = 0xDE6E, sec = 0x2020, yea = 0xC102 | |
[RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 | |
[RTC] rtc_boot_check Writeif_unlock | |
[RTC]switch to dcxo | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=810 | |
[RTC] EOSC_Cali: val=0x32A | |
[RTC] get_frequency_meter: input=0x7, ouput=700 | |
[RTC] EOSC_Cali: val=0x2BC | |
[RTC] get_frequency_meter: input=0xB, ouput=756 | |
[RTC] EOSC_Cali: val=0x2F4 | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] EOSC_Cali: val=0x30F | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]cold boot | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Byp | |
[CH0][RK0][1600][CBT] Best CA Vref 18, Window Min 57 at CA4, Window Sum 347 | |
[CH0][RK1][1600][CBT] Best CA Vref 18, Window Min 58 at CA4, Window Sum 353 | |
[CH0][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ6, Window Sum 420 | |
[CH0][RK0][1600][RX] Best Vref 30, Window Min 49 at DQ8, Window Sum 850 | |
[CH0][RK1][1600][TX] Best Vref 15, Window Min 25 at DQ14, Window Sum 426 | |
[CH1][RK0][1600][CBT] Best CA▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x152A (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x19 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x196C (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x1A08 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x48 | |
[PMIC]PONSTS[0xC]=0x6 | |
[PMIC]POFFSTS[0xE]=0x1 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x1200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] DDLO_RSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x1221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 3AEE 8000 98E9 82B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] enable_dcxo first con = 0x486, osc32con = 0xDE6E, sec = 0x2020 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3984 | |
[RTC] rtc_boot_check1 powerkey1 = 0xA357, powerkey2 = 0x67D2, without LPD | |
[RTC] bbpu = 0x1, con = 0x486, osc32con = 0xDE6E, sec = 0x2020, yea = 0xC102 | |
[RTC] rtc_boot_check2 powerkey1 = 0xA357, powerkey2 = 0x67D2 | |
[RTC] rtc_boot_check Writeif_unlock | |
[RTC]switch to dcxo | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=811 | |
[RTC] EOSC_Cali: val=0x32B | |
[RTC] get_frequency_meter: input=0x7, ouput=701 | |
[RTC] EOSC_Cali: val=0x2BD | |
[RTC] get_frequency_meter: input=0xB, ouput=756 | |
[RTC] EOSC_Cali: val=0x2F4 | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] EOSC_Cali: val=0x30F | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] RTC_SPAR0=0x0 | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x2020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0x0 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 0 (0x0) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: wdt does not trigger rst | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: | |
[PLFM] Init Boot Device: OK(0) | |
EMI_MPU_CTRL=0 1st | |
EMI_MPU_CTRL=0 2nd | |
[RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 | |
[RGU] WDT DDR reserve mode FAIL! 200F1 | |
[RGU] DDR RESERVE Success 0 | |
[RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 | |
ikKJ | |
▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒Pll init start... | |
INFRA_BUS_DCM_CTRL 5F7FE0 | |
mtcmos Start.. | |
before: WDT_SWSYSRST = 0x8000 | |
after: WDT_SWSYSRST = 0x9000 | |
P[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9 | |
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass | |
[PWRAP] InitSiStrobe (6, 6, DA65) Data Boundary Is Found !! | |
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 6) | |
[PWRAP] Read Test pass, return_value=0x0 | |
[PWRAP] Write Test pass | |
[PWRAP] RECORD_CMD0: 0x0 (Last one command addr) | |
[PWRAP] RECORD_WDATA0:0x0 (Last one command wdata) | |
[PWRAP] RECORD_CMD1: 0x0 (Last second command addr) | |
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata) | |
[PWRAP] RECORD_CMD2: 0x0 (Last third command addr) | |
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata) | |
[PWRAP] init pass, ret=0. | |
[PMIC]Preloader Start | |
[PMIC]MT6357 CHIP Code = 0x57, mrv=1 | |
[PMIC]POWER_HOLD :0x1 | |
[PMIC]TOP_RST_STATUS[0x152]=0x0 | |
[PMIC]PONSTS[0xC]=0x4 | |
[PMIC]POFFSTS[0xE]=0x0 | |
[PMIC]PGSTATUS0[0x14]=0xFFFE | |
[PMIC]PSOCSTATUS[0x16]=0x0 | |
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0 | |
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x49F | |
[PMIC]THERMALSTATUS[0x18]=0x0 | |
[PMIC]STRUP_CON4[0xA1C]=0x0 | |
[PMIC]TOP_RST_MISC[0x14C]=0x200 | |
[PMIC]TOP_CLK_TRIM[0x38E]=0x6AC0 | |
latch VPROC 800000 uV | |
latch VSRAM_PROC 900000 uV | |
latch VSRAM_OTHERS 900000 uV | |
latch VCORE 800000 uV | |
latch VMODEM 800000 uV | |
[pmic_check_rst] PORSTB | |
[PMIC]just_rst = 0 | |
No EFUSE SW Load | |
[PMIC]pmic_wdt_set Reg[0x14C]=0x221 | |
[rt5738_driver_probe] | |
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0 | |
mt6691_vdd2_hw_init | |
[0x0]=0xA5 [0x1]=0xA5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63 | |
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1 | |
register vs1 OK | |
register vmodem OK | |
register vcore OK | |
register vproc OK | |
register vpa OK | |
register vsram_others OK | |
register vsram_proc OK | |
register vdram OK | |
register vfe28 OK | |
[PMIC]Init done | |
ac 0,usb 1 | |
[PLFM] Init PMIC: OK(0) | |
[PLFM] chip_ver[1] | |
[BLDR] Build Time: 20201104-090402 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 1 1 | |
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=-1 -1 -1 -1 -1 -1 -1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x6B6D 386A AD00 9829 A2B5 A19A A8AA 11 1 | |
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4E1D 386A 8000 98E9 A2B5 A2AA 9455 11 0 | |
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1 | |
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] RTC 32K mode setting wrong. Enter first boot/recovery. | |
[RTC] rtc_boot_check1 powerkey1 = 0xF146, powerkey2 = 0xC102, with LPD | |
[RTC] bbpu = 0x45, con = 0x8339, osc32con = 0xBD3E, sec = 0x2140, yea = 0x2108 | |
[RTC] rtc_first_boot_init | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3015 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=0 | |
[RTC] get_frequency_meter: input=0x0, ouput=5 | |
[RTC] get_frequency_meter: input=0x0, ouput=3015 | |
[RTC] EOSC_Cali: RG_FQMTR_CKSEL=0x42 | |
[RTC] get_frequency_meter: input=0xF, ouput=811 | |
[RTC] EOSC_Cali: val=0x32B | |
[RTC] get_frequency_meter: input=0x7, ouput=701 | |
[RTC] EOSC_Cali: val=0x2BD | |
[RTC] get_frequency_meter: input=0xB, ouput=756 | |
[RTC] EOSC_Cali: val=0x2F4 | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] EOSC_Cali: val=0x30F | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC_Cali: val=0x31D | |
[RTC] get_frequency_meter: input=0xD, ouput=783 | |
[RTC] get_frequency_meter: input=0xE, ouput=797 | |
[RTC] EOSC cali val = 0xE | |
[RTC] EOSC cali val = 0xDE4E | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[RTC] rtc_2sec_stat_clear | |
[RTC] XO_XMODE_M = 1 , XO_EN32K_M = 1 | |
[RTC] 32k-less mode | |
[RTC] rtc_2sec_reboot_check 0x6020, without 2sec reboot, type 0x0 | |
[RTC] rtc 2sec reboot is not enabled | |
[RTC] rtc_lpd_init RTC_CON=0x486 | |
[PMIC] pmic_init_setting end. v180413 | |
[MT6357] 1 6,61 | |
[MT6357] 1 2,45 | |
[MT6357] 1 1,48 | |
[MT6357] get volt 5, 61, 900000 | |
vsram_others = 900000 uV | |
[MT6357] get volt 3, 45, 800000 | |
vproc = 800000 uV | |
[MT6357] get volt 6, 61, 900000 | |
vsram_proc = 900000 uV | |
[MT6357] get volt 2, 45, 800000 | |
vcore = 800000 uV | |
[MT6357] get volt 1, 48, 800000 | |
vmodem = 800000 uV | |
[MT6357] 2 6,1 | |
[MT6357] 2 5,1 | |
[MT6357] 2 3,1 | |
[MT6357] 2 2,1 | |
[RGU] EMI_DCS_SUCCESS 0 | |
[RGU] DVFSRC_SUCCESS 0 | |
[RGU] MODE: 0x4D | |
[RGU] STA: 0xA0000000 | |
[RGU] LENGTH: 0xFFE0 | |
[RGU] INTERVAL: 0xFFF | |
[RGU] SWSYSRST: 0x9000 | |
[RGU] LATCH_CTL: 0x0 | |
[RGU] NONRST_REG2: 0x0 | |
[RGU] DEBUG_CTL: 0x200F1 | |
[RGU] g_rgu_status: 4 (0x4) | |
[RGU] mtk_wdt_mode_config mode value=10, tmp:22000010 | |
[RGU] rst from: ? | |
[RGU] bypass pwrkey: NOT set | |
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDEG_EN2(800067D2) | |
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x100070A0, val: 0x2FF | |
[RGU] rgu_update_reg: 1, bits: 0x200, addr: 0x100070A0, val: 0x2FF | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL(0x200F1) | |
[RGU] mtk_wdt_init: MTK_WDT_DEBUG_CTL2(0x2FF) | |
[RGU] mtk_wdt_init: MTK_WDT_LATCH_CTL(0xB871) | |
[RGU] mtk_wdt_init: MTK_WDT_REQ_MODE(3F0032), MTK_WDT_REQ_IRQ_EN(3F0032) | |
Enter mtk_kpd_gpio_set! | |
after set KP enable: KP_SEL = 0x0 ! | |
[RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x80, spar1 = 0x800 | |
[RTC] new_spare0 = 0x4000, new_spare1 = 0x5001, new_spare2 = 0x1, new_spare3 = 0x1 | |
[RTC] bbpu = 0x0, con = 0x486, cali = 0x2020, osc32con = 0xDE6E | |
[PLFM] WDT normal boot! | |
[PMIC]POWER_HOLD :0x1 | |
[RTC]rtc_lpsd_solution | |
[RTC]1st RTC_AL_MASK= 0x0 | |
[RTC]2nd RTC_AL_MASK= 0x7F | |
[RTC]rtc_bbpu_power_on done | |
[PLFM] Init Boot Device: OK(0) | |
EMI_MPU_CTRL=0 1st | |
EMI_MPU_CTRL=0 2nd | |
[RGU] rgu_update_reg: 0, bits: 0x400, addr: 0x10007040, val: 0x200F1 | |
[RGU] WDT DDR reserve mode FAIL! 200F1 | |
[RGU] DDR RESERVE Success 0 | |
[RGU] rgu_update_reg: 0, bits: 0x200, addr: 0x10007040, val: 0x200F1 | |
[RGU] rgu_update_reg: 0, bits: 0x100, addr: 0x10007040, val: 0x200F1 | |
[GPT_PL] startsec:0000000000001C00, partattr:0023785C1D062024.. | |
[dramc] init partition address is 0x0000000000380000 | |
init_dram:1660: init_dram Starting | |
[MT6357] 2 8,0 | |
[MT6357] 2 7,0 | |
[set_dram_voltage]set dram voltage done!!! | |
[MT6357] 1 2,25 | |
[dramc]wdt_dbg_signal[0]=0x0 | |
[dramc]wdt_dbg_signal[1]=0x0 | |
[dramc] read off[2] = 6 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 1, Bypass_RXWINDOW=1, Bypass_TXWINDOW=1 | |
[CH0][RK0][1600][CBT] Best CA Vref 18, Window Min 57 at CA4, Window Sum 348 | |
[CH0][RK1][1600][CBT] Best CA Vref 18, Window Min 58 at CA4, Window Sum 356 | |
[CH0][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ6, Window Sum 420 | |
[CH0][RK0][1600][RX] Best Vref 30, Window Min 49 at DQ8, Window Sum 850 | |
[CH0][RK1][1600][TX] Best Vref 15, Window Min 25 at DQ14, Window Sum 426 | |
[CH1][RK0][1600][CBT] Best CA Vref 18, Window Min 56 at CA4, Window Sum 351 | |
[CH1][RK1][1600][CBT] Best CA Vref 18, Window Min 56 at CA4, Window Sum 348 | |
[CH1][RK0][1600][TX] Best Vref 13, Window Min 25 at DQ13, Window Sum 429 | |
[CH1][RK0][1600][RX] Best Vref 29, Window Min 52 at DQ10, Window Sum 883 | |
[CH1][RK1][1600][TX] Best Vref 8, Window Min 25 at DQ14, Window Sum 426 [FAST_K] Bypass saving calibration result to emmc | |
[MT6357] 1 2,37 | |
[dramc] read off[1] = 4 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 | |
[CH0][RK0][2666][CBT] Best CA Vref 18, Window Min 52 at CA4, Window Sum 332 | |
[CH0][RK1][2666][CBT] Best CA Vref 16, Window Min 53 at CA4, Window Sum 338 | |
[CH0][RK0][2666][TX] Best Vref 12, Window Min 23 at DQ14, Window Sum 431 | |
[CH0][RK0][2666][RX] Best Vref 14, Window Min 33 at DQ0, Window Sum 563 | |
[CH0][RK1][2666][TX] Best Vref 12, Window Min 22 at DQ11, Window Sum 409 | |
[CH1][RK0][2666][CBT] Best CA Vref 18, Window Min 52 at CA4, Window Sum 341 | |
[CH1][RK1][2666][CBT] Best CA Vref 16, Window Min 51 at CA4, Window Sum 332 | |
[CH1][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ14, Window Sum 424 | |
[CH1][RK0][2666][RX] Best Vref 14, Window Min 34 at DQ14, Window Sum 594 | |
[CH1][RK1][2666][TX] Best Vref 10, Window Min 21 at DQ6, Window Sum 403 [FAST_K] Bypass saving calibration result to emmc | |
[MT6357] 1 2,45 | |
[dramc] read off[0] = 2 1024 | |
[FAST_K] DramcSave_Time_For_Cal_Init SHU0, femmc_Ready=1 | |
[FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 | |
[CH0][RK0][3200][CBT] Best CA Vref 18, Window Min 51 at CA4, Window Sum 327 | |
[CH0][RK1][3200][CBT] Best CA Vref 16, Window Min 53 at CA3, Window Sum 328 | |
[CH0][RK0][3200][TX] Best Vref 12, Window Min 19 at DQ14, Window Sum 352 | |
[CH0][RK0][3200][RX] Best Vref 14, Window Min 29 at DQ7, Window Sum 491 | |
[CH0][RK1][3200][TX] Best Vref 14, Window Min 19 at DQ0, Window Sum 335 | |
[CH1][RK0][3200][CBT] Best CA Vref 18, Window Min 51 at CA4, Window Sum 333 | |
[CH1][RK1][3200][CBT] Best CA Vref 16, Window Min 51 at CA4, Window Sum 328 | |
[CH1][RK0][3200][TX] Best Vref 12, Window Min 21 at DQ3, Window Sum 369 | |
[CH1][RK0][3200][RX] Best Vref 14, Window Min 30 at DQ14, Window Sum 524 | |
[CH1][RK1][3200][TX] Best Vref 10, Window Min 21 at DQ1, Window Sum 362 [FAST_K] Bypass saving calibration result to emmc | |
[dramc_run_time_config] | |
TX_TRACKING: ON | |
RX_TRACKING: ON | |
HW_GATING: ON | |
HW_GATING DBG: OFF | |
DUMMY_READ_FOR_TRACKING: ON | |
ZQCS_ENABLE_LP4: ON | |
LOWPOWER_GOLDEN_SETTINGS(DCM): ON | |
DUMMY_READ_FOR_DQS_GATING_RETRY: OFF | |
IMPEDANCE_TRACKING: ON | |
TEMP_SENSOR: ON | |
PER_BANK_REFRESH: ON | |
HW_SAVE_FOR_SR: ON | |
SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON | |
CLK_FREE_FUN_FOR_DRAMC_PSEL: ON | |
PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON | |
Read ODT Tracking: ON | |
DQS Precalculation for DVFS: ON | |
Step1: Set DVFS HW enable | |
Step2: Set jump ratio | |
Step1: Set DVFS HW enable | |
Step2: Set jump ratio | |
========================= | |
[switch_dramc_voltage_to_auto_mode]switch dram voltage to auto mode done!!! | |
[Dram_Buffer] dram size: 0x0 | |
[Dram_Buffer] dram_buf_t size: 0x180FC0 | |
[Dram_Buffer] part_hdr_t size: 0x200 | |
[Dram_Buffer] g_dram_buf start addr: 0x42000000 | |
[Dram_Buffer] g_dram_buf->msdc_gpd_pool start addr: 0x42180E00 | |
[Dram_Buffer] g_dram_buf->msdc_bd_pool start addr: 0x42180EC0 | |
RAM_CONSOLE using default | |
RAM_CONSOLE start: 0x54400000, size: 0x10000, sig: 0xFFFFFFFF | |
RAM_CONSOLE wdt status (0x4)=0x4 | |
orig_dram_info[0] start: 0x0000000040000000, size: 0x0000000080000000 | |
orig_dram_info[1] start: 0x00000000C0000000, size: 0x0000000080000000 | |
CUSTOM_CONFIG_MAX_DRAM_SIZE: 0x0000000100000000 | |
total_dram_size: 0x0000000100000000, max_dram_size: 0x0000000100000000 | |
[GPT_PL]Parsing Primary GPT now... | |
[GPT_PL][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800 | |
[GPT_PL][1]name=boot_para, part_id=8, start_sect=0x1C00, nr_sects=0x800 | |
[GPT_PL][2]name=cam_vpu1, part_id=8, start_sect=0x2400, nr_sects=0x7800 | |
[GPT_PL][3]name=cam_vpu2, part_id=8, start_sect=0x9C00, nr_sects=0x7800 | |
[GPT_PL][4]name=cam_vpu3, part_id=8, start_sect=0x11400, nr_sects=0x7800 | |
[GPT_PL][5]name=nvram, part_id=8, start_sect=0x18C00, nr_sects=0x2800 | |
[GPT_PL][6]name=protect1, part_id=8, start_sect=0x1B400, nr_sects=0x5000 | |
[GPT_PL][7]name=protect2, part_id=8, start_sect=0x20400, nr_sects=0x5000 | |
[GPT_PL][8]name=persist, part_id=8, start_sect=0x25400, nr_sects=0x18000 | |
[GPT_PL][9]name=nvcfg, part_id=8, start_sect=0x3D400, nr_sects=0x4000 | |
[GPT_PL][10]name=seccfg, part_id=8, start_sect=0x41400, nr_sects=0x200 | |
[GPT_PL][11]name=lk, part_id=8, start_sect=0x41600, nr_sects=0x800 | |
[GPT_PL][12]name=lk2, part_id=8, start_sect=0x41E00, nr_sects=0x800 | |
[GPT_PL][13]name=boot, part_id=8, start_sect=0x42600, nr_sects=0x8000 | |
[GPT_PL][14]name=recovery, part_id=8, start_sect=0x4A600, nr_sects=0x8000 | |
[GPT_PL][15]name=para, part_id=8, start_sect=0x52600, nr_sects=0x400 | |
[GPT_PL][16]name=logo, part_id=8, start_sect=0x52A00, nr_sects=0x4000 | |
[GPT_PL][17]name=dtbo, part_id=8, start_sect=0x56A00, nr_sects=0x4000 | |
[GPT_PL][18]name=expdb, part_id=8, start_sect=0x5AA00, nr_sects=0x5000 | |
[GPT_PL][19]name=frp, part_id=8, start_sect=0x5FA00, nr_sects=0x800 | |
[GPT_PL][20]name=nvdata, part_id=8, start_sect=0x60200, nr_sects=0x10000 | |
[GPT_PL][21]name=tee1, part_id=8, start_sect=0x70200, nr_sects=0x2800 | |
[GPT_PL][22]name=tee2, part_id=8, start_sect=0x72A00, nr_sects=0x2800 | |
[GPT_PL][23]name=kb, part_id=8, start_sect=0x75200, nr_sects=0x1000 | |
[GPT_PL][24]name=dkb, part_id=8, start_sect=0x76200, nr_sects=0x1000 | |
[GPT_PL][25]name=metadata, part_id=8, start_sect=0x77200, nr_sects=0x10000 | |
[GPT_PL][26]name=vbmeta, part_id=8, start_sect=0x87200, nr_sects=0x5A00 | |
[GPT_PL][27]name=system, part_id=8, start_sect=0x8CC00, nr_sects=0x2A2000 | |
[GPT_PL][28]name=vendor, part_id=8, start_sect=0x32EC00, nr_sects=0xC8000 | |
[GPT_PL][29]name=factory, part_id=8, start_sect=0x3F6C00, nr_sects=0x8000 | |
[GPT_PL][30]name=cache, part_id=8, start_sect=0x3FEC00, nr_sects=0x200000 | |
[GPT_PL][31]name=userdata, part_id=8, start_sect=0x5FEC00, nr_sects=0x17203DF | |
[GPT_PL][32]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][33]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][34]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][35]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][36]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][37]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][38]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][39]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][40]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][41]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][42]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][43]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][44]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][45]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][46]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][47]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][48]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][49]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][50]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][51]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][52]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][53]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][54]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][55]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][56]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][57]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][58]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][59]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][60]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][61]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][62]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][63]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][64]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][65]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][66]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][67]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][68]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][69]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][70]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][71]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][72]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][73]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][74]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][75]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][76]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][77]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][78]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][79]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][80]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][81]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][82]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][83]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][84]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][85]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][86]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][87]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][88]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][89]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][90]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][91]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][92]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][93]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][94]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][95]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][96]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][97]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][98]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][99]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][100]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][101]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][102]name=, part_id=8, start_sect=0x0, nr_sects=0x1 | |
[GPT_PL][103]name=, pa | |
chr type: 1 | |
[PLFM] USB cable in | |
[TOOL] USB enum timeout (Yes), handshake timeout(Yes) | |
[TOOL] Enumeration(Start) | |
HS is detected | |
[TOOL] Enumeration(End): OK 292ms | |
[TOOL] : usb listen timeout | |
[TOOL] <USB> cannot detect tools! | |
Device APC domain init setup: | |
Domain Setup Infra (0x33333333),(0x30333333),(0x32333333),(0x33333333) | |
Device APC: sec_init Infra MAS_SEC_0=0x20 | |
[BLDR] check active part. of lk and lk2 | |
[BLDR] lk active = 0, lk2 active = 0 | |
[BLDR] Loading lk Partition... | |
[PART] partition name = lk | |
[LIB] S-CHIP | |
[SEC_POLICY] sboot_state = 0x1 | |
[SEC_POLICY] lock_state = 0x4 | |
[PART] img_auth_required = 1 | |
[PART] partition hdr (1) | |
[PART] Image with part header | |
[PART] name : lk | |
[PART] addr : FFFFFFFFh mode : -1 | |
[PART] size : 541612 | |
[PART] magic: 58881688h | |
sbc_en = 1 | |
sbc_en = 1 | |
[SBC] cert verify, part = lk, img = lk...ok | |
[PART] part: lk img: lk cert vfy(135 ms) | |
[PART] load "lk" from 0x00000000082C0200 (dev) to 0x56000000 (mem) [SUCCESS] | |
[PART] load speed: 35260KB/s, 541612 bytes, 15ms | |
[PART] img vfy...[SBC] img auth ok | |
ok | |
[PART] part: lk img: lk vfy(42 ms) | |
[BLDR] check active part. of tee1 and tee2 | |
[BLDR] tee1 active = 0, tee2 active = 0 | |
[BLDR] Loading tee1 Partition... | |
[PART] partition name = tee1 | |
[LIB] S-CHIP | |
[SEC_POLICY] sboot_state = 0x1 | |
[SEC_POLICY] lock_state = 0x4 | |
[PART] img_auth_required = 1 | |
[PART] partition hdr (1) | |
[PART] Image with part header | |
[PART] name : atf | |
[PART] addr : FFFFFFFFh mode : 0 | |
[PART] size : 123392 | |
[PART] magic: 58881688h | |
sbc_en = 1 | |
sbc_en = 1 | |
[SBC] cert verify, part = tee1, img = atf...ok | |
[PART] part: tee1 img: atf cert vfy(132 ms) | |
[PART] load "tee1" from 0x000000000E040200 (dev) to 0x54601000 (mem) [SUCCESS] | |
[PART] load speed: 30125KB/s, 123392 bytes, 4ms | |
[PART] img vfy...[SBC] img auth ok | |
ok | |
[PART] part: tee1 img: atf vfy(10 ms) | |
[BLDR_MTEE] sha256 takes 1 (ms) for 122816 bytes | |
[BLDR_MTEE] rsa2048 takes 57 (ms) | |
[BLDR_MTEE] verify pkcs#1 pss takes 0 (ms) | |
[BLDR_MTEE] aes128cbc takes 0 (ms) for 122816 | |
[PART] partition name = tee1 | |
[LIB] S-CHIP | |
[SEC_POLICY] sboot_state = 0x1 | |
[SEC_POLICY] lock_state = 0x4 | |
[PART] img_auth_required = 1 | |
[PART] partition hdr (1) | |
[PART] Image with part header | |
[PART] name : tee | |
[PART] addr : 600000h mode : 0 | |
[PART] size : 2440192 | |
[PART] magic: 58881688h | |
sbc_en = 1 | |
sbc_en = 1 | |
[SBC] cert verify, part = tee1, img = tee...ok | |
[PART] part: tee1 img: tee cert vfy(146 ms) | |
mblock[0].start: 0x0000000040000000, sz: 0x000000003FFC0000, limit: 0x0000000100000000, max_addr: 0x0000000000000000, target: -1, reserved_addr: 0x000000007F980000,reserved_size: 0x0000000000640000 | |
mblock_reserve dbg[0]: 1, 1, 1, 1 | |
mblock[1].start: 0x0000000080000000, sz: 0x0000000040000000, limit: 0x0000000100000000, max_addr: 0x000000007FFC0000, target: 0, reserved_addr: 0x00000000BF9C0000,reserved_size: 0x0000000000640000 | |
mblock_reserve dbg[1]: 1, 1, 1, 1 | |
mblock[2].start: 0x00000000C0000000, sz: 0x0000000080000000, limit: 0x0000000100000000, max_addr: 0x00000000C0000000, target: 1, reserved_addr: 0x00000000FF9C0000,reserved_size: 0x0000000000640000 | |
mblock_reserve dbg[2]: 1, 1, 1, 1 | |
mblock[2]: 00000000C0000000, 000000003F9C0000 from mblock | |
mblock[3]: 0000000100000000, 0000000040000000 from mblock | |
mblock_reserve: 00000000FF9C0000 - 0000000100000000 from mblock 2 | |
mblock_reserve[0].start: 0x0000000040000000, sz: 0x000000003FFC0000 | |
mblock_reserve[1].start: 0x0000000080000000, sz: 0x0000000040000000 | |
mblock_reserve[2].start: 0x00000000C0000000, sz: 0x000000003F9C0000 | |
mblock_reserve[3].start: 0x0000000100000000, sz: 0x0000000040000000 | |
mblock_reserve-R[0].start: 0x000000007FFC0000, sz: 0x0000000000040000 map:1 name:log_store | |
mblock_reserve-R[1].start: 0x00000000FF9C0000, sz: 0x0000000000640000 map:0 name:tee | |
[PART] load "tee1" from 0x000000000E05F470 (dev) to 0xFFA00000 (mem) [SUCCESS] | |
[PART] load speed: 41085KB/s, 2440192 bytes, 58ms | |
[PART] img vfy...[SBC] img auth ok | |
ok | |
[PART] part: tee1 img: tee vfy(190 ms) | |
[BLDR_MTEE] sha256 takes 12 (ms) for 2439616 bytes | |
[BLDR_MTEE] rsa2048 takes 58 (ms) | |
[BLDR_MTEE] verify pkcs#1 pss takes 0 (ms) | |
[BLDR_MTEE] aes128cbc takes 15 (ms) for 2439616 | |
[TZ_INIT] TEE start entry : 0xFFA00000 | |
[TZ_INIT] MEID : 0xC5, 0xFE, 0xD2, 0xA8 | |
[TZ_INIT] MEID : 0xEE, 0xD9, 0x5D, 0x10 | |
[TZ_INIT] MEID : 0xE7, 0x2C, 0xC1, 0xD6 | |
[TZ_INIT] MEID : 0x47, 0x65, 0xFB, 0xD8 | |
[BLDR] bldr load tee part ret=0x0, addr=0x54601000 | |
[BLDR] part_load_raw_part ret=0x0 | |
[BLDR] part_load_images ret=0x0 | |
[BLDR] - wdt_rpmb_program_mode MTK_WDT_NONRST_REG2: 40000000 | |
[PICACHU]start_picachu | |
[PICACHU] dram_rank_size[0] = 0x0000000080000000 | |
[PICACHU] dram_rank_size[1] = 0x0000000080000000 | |
[PICACHU] before modify dram_size = 0x0000000100000000 | |
[PICACHU] CFG_DRAM_ADDR = 0x40000000 | |
[PICACHU] after modify dram_size = 0x00000000BF000000 | |
[PICACHU] pi_dram_log_addr max address = 0xFF000000 | |
mblock[0].start: 0x0000000040000000, sz: 0x000000003FFC0000, limit: 0x00000000FF000000, max_addr: 0x0000000000000000, target: -1, reserved_addr: 0x000000007FE00000,reserved_size: 0x0000000000100000 | |
mblock_reserve dbg[0]: 1, 1, 1, 1 | |
mblock[1].start: 0x0000000080000000, sz: 0x0000000040000000, limit: 0x00000000FF000000, max_addr: 0x000000007FFC0000, target: 0, reserved_addr: 0x00000000BFF00000,reserved_size: 0x0000000000100000 | |
mblock_reserve dbg[1]: 1, 1, 1, 1 | |
mblock[2].start: 0x00000000C0000000, sz: 0x000000003F9C0000, limit: 0x00000000FF000000, max_addr: 0x00000000C0000000, target: 1, reserved_addr: 0x00000000FEF00000,reserved_size: 0x0000000000100000 | |
mblock_reserve dbg[2]: 1, 1, 1, 1 | |
mblock[3].start: 0x0000000100000000, sz: 0x0000000040000000, limit: 0x00000000FF000000, max_addr: 0x00000000FF9C0000, target: 2, reserved_addr: 0x00000000FEF00000,reserved_size: 0x0000000000100000 | |
mblock_reserve dbg[3]: 1, 0, 1, 1 | |
mblock[2]: 00000000C0000000, 000000003EF00000 from mblock | |
mblock[3]: 00000000FF000000, 00000000009C0000 from mblock | |
mblock_reserve: 00000000FEF00000 - 00000000FF000000 from mblock 2 | |
mblock_reserve[0].start: 0x0000000040000000, sz: 0x000000003FFC0000 | |
mblock_reserve[1].start: 0x0000000080000000, sz: 0x0000000040000000 | |
mblock_reserve[2].start: 0x00000000C0000000, sz: 0x000000003EF00000 | |
mblock_reserve[3].start: 0x00000000FF000000, sz: 0x00000000009C0000 | |
mblock_reserve[4].start: 0x0000000100000000, sz: 0x0000000040000000 | |
mblock_reserve-R[0].start: 0x000000007FFC0000, sz: 0x0000000000040000 map:1 name:log_store | |
mblock_reserve-R[1].start: 0x00000000FF9C0000, sz: 0x0000000000640000 map:0 name:tee | |
mblock_reserve-R[2].start: 0x00000000FEF00000, sz: 0x0000000000100000 map:0 name:PICACHU | |
[pmic_get_auxadc_value] reg_val = 0x5FD1, adc_result = 4042 | |
[DOE_ENV] No doconfig setting | |
[DOE_ENV]read_env_area fail, ret = -1 | |
[DOE_ENV]get_env PICACHU_DOE | |
[PICACHU] L Freq: 2001 | |
[PLFM],64S3,boot_opt=0x0 | |
[PLFM],32N2,boot_opt=0x6 | |
[PLFM],64N2,boot_opt=0x4 | |
lastpc[0][0] = FFFA1FC8 | |
lastpc[0][1] = FFFF3B30 | |
lastpc[0][2] = 81028291 | |
lastpc[0][3] = 80000055 | |
lastpc[0][4] = 10081900 | |
lastpc[0][5] = 410D6824 | |
lastpc[0][6] = 1D40C83D | |
lastpc[0][7] = 61E88240 | |
lastpc[1][0] = 0 | |
lastpc[1][1] = 0 | |
lastpc[1][2] = 0 | |
lastpc[1][3] = 0 | |
lastpc[1][4] = 0 | |
lastpc[1][5] = 0 | |
lastpc[1][6] = 0 | |
lastpc[1][7] = 0 | |
lastpc[2][0] = 0 | |
lastpc[2][1] = 0 | |
lastpc[2][2] = 0 | |
lastpc[2][3] = 0 | |
lastpc[2][4] = 0 | |
lastpc[2][5] = 0 | |
lastpc[2][6] = 0 | |
lastpc[2][7] = 0 | |
lastpc[3][0] = 0 | |
lastpc[3][1] = 0 | |
lastpc[3][2] = 0 | |
lastpc[3][3] = 0 | |
lastpc[3][4] = 0 | |
lastpc[3][5] = 0 | |
lastpc[3][6] = 0 | |
lastpc[3][7] = 0 | |
[PLFM] boot to LK by ATAG. | |
PL_VERSION = 0.1.00 | |
[mt_charger_type_detection] Got data !!, 1 | |
emmc ocr = 0xC0FF8080 | |
emmc cid: 0x15010041 0x4A544434 0x5206436A 0xBCE0A76F | |
emmc csd: 0xD0270132 0xF5903FF 0xF6DBFFEF 0x8E40400D | |
BOOT_REASON: 3 | |
BOOT_MODE: 0 | |
META_COM TYPE: 0 | |
META_COM ID: 0 | |
META_COM PORT: 285224960 | |
LOG_COM PORT: 285220864 | |
LOG_COM BAUD: 921600 | |
LOG_COM EN: 1 | |
LOG_COM SWITCH: 1 | |
MEM_NUM: 2 | |
MEM_SIZE: 0x3FFC0000 | |
MEM_SIZE: 0x40000000 | |
mblock num: 0x5 | |
mblock start: 0x0000000040000000 | |
mblock size: 0x000000003FFC0000 | |
mblock rank: 0x0 | |
mblock start: 0x0000000080000000 | |
mblock size: 0x0000000040000000 | |
mblock rank: 0x0 | |
mblock start: 0x00000000C0000000 | |
mblock size: 0x000000003EF00000 | |
mblock rank: 0x1 | |
mblock start: 0x00000000FF000000 | |
mblock size: 0x00000000009C0000 | |
mblock rank: 0x1 | |
orig_dram num: 0x2 | |
orig_dram start: 0x0000000040000000 | |
orig_dram size: 0x0000000080000000 | |
orig_dram start: 0x00000000C0000000 | |
orig_dram size: 0x0000000080000000 | |
orig_dram start: 0x0000000000000000 | |
orig_dram size: 0x0000000000000000 | |
orig_dram start: 0x0000000000000000 | |
orig_dram size: 0x0000000000000000 | |
lca start: 0x0000000000000000 | |
lca size: 0x0000000000000000 | |
tee start: 0x00000000FF9C0000 | |
tee size: 0x0000000000040000 | |
MD_INFO: 0x2 | |
MD_INFO: 0x1 | |
MD_INFO: 0x0 | |
MD_INFO: 0x0 | |
BOOT_TIME: 6848 | |
DA_INFO: 0xFFFFFFFF | |
DA_INFO: 0xFFFFFFFF | |
DA_INFO: 0xFFFFFFFF | |
DA_INFO: 0xFFFFFFFF | |
DA_INFO: 0x70000010 | |
SEC_INFO: 0x0 | |
SEC_INFO: 0x20 | |
PART_NUM: 3 | |
PART_INFO: 0x42058A24 | |
EFLAG: 0 | |
DDR_RESERVE: 0 | |
DDR_RESERVE: 0 | |
DDR_RESERVE: 0 | |
DRAM_BUF: 1576896 | |
SMC: 0x0 | |
SMC: 0x6 | |
SMC: 0x4 | |
SRAM satrt: 0x111D00 | |
SRAM size: 0x300 | |
PLAT_DBG_INFO key: 0x0 | |
PLAT_DBG_INFO base: 0x0 | |
PLAT_DBG_INFO size: 0x0 | |
PLAT_DBG_INFO key: 0x0 | |
PLAT_DBG_INFO base: 0x0 | |
PLAT_DBG_INFO size: 0x0 | |
PLAT_DBG_INFO key: 0xDB45 | |
PLAT_DBG_INFO base: 0x111E0C | |
PLAT_DBG_INFO size: 0x10 | |
[TZ_INIT] hwuid[0] : 0xA8D2FEC5 | |
[TZ_INIT] hwuid[1] : 0x105DD9EE | |
[TZ_INIT] hwuid[2] : 0xD6C12CE7 | |
[TZ_INIT] hwuid[3] : 0xD8FB6547 | |
[TZ_INIT] HRID[0] : 0xA2A0D71F | |
[TZ_INIT] HRID[1] : 0x804C73ED | |
[TZ_INIT] atf_log_port : 0x11002000 | |
[TZ_INIT] atf_log_baudrate : 0xE1000 | |
[TZ_INIT] atf_irq_num : 281 | |
[TZ_INIT] ATF log buffer start : 0xFF9C0000 | |
[TZ_INIT] ATF log buffer size : 0x40000 | |
[TZ_INIT] ATF aee buffer start : 0xFF9FC000 | |
[TZ_INIT] ATF aee buffer size : 0x4000 | |
Device APC: sec_postinit Infra MAS_SEC_0=0x0 | |
[BLDR] Others, jump to ATF | |
[BLDR] jump to 0x56000000 | |
[BLDR] <0x56000000>=0xEA000007 | |
[BLDR] <0x56000004>=0xEA007FC7 | |
[TZ_SEC_CFG] SRAMROM Secure Addr 0x10011C00 | |
[TZ_SEC_CFG] SRAMROM Secure Addr 1 0x30000 | |
[TZ_SEC_CFG] SRAMROM Secure Addr 2 0x38000 | |
[TZ_SEC_CFG] SRAMROM Secure Control 2 0xB680000 | |
[TZ_SEC_CFG] SRAMROM Secure Control 5 0xB690000 | |
[TZ_SEC_CFG] SRAMROM Secure Control 6 0xB690000 | |
[TZ_SEC_CFG] SRAMROM Secure Control 0xC0000B69 | |
MPU [LOCK | |
[TZ_EMI_MPU] MPU [0xFFA00000-0xFFFFFFFF] | |
[TZ_INIT] set secure memory protection : 0xFFA00000, 0xFFFFFFFF (OPT) | |
MPU [LOCK | |
[TZ_EMI_MPU] MPU [0x54600000-0x5462FFFF] | |
[TZ_INIT] set secure memory protection : 0x54600000, 0x5462FFFF | |
[TZ_INIT] Jump to ATF, then 0xFFA00000 and 0x56000000 | |
INFO: [ATF](0)[7.001080]log_enable:1 | |
INFO: [ATF](0)[7.001521]atf_log_port:0x11002000 | |
INFO: [ATF](0)[7.002081]BOOT_REASON: 3 | |
INFO: [ATF](0)[7.002544]IS_ABNORMAL_BOOT: 0 | |
INFO: [ATF](0)[7.003061]CPUxGPT reg(0) | |
INFO: [ATF](0)[7.003524][systimer] CNTCR_REG(0x505) | |
INFO: [ATF](0)[7.004127]Secondary bootloader is AArch32 | |
INFO: [ATF](0)[7.004774]bl31_plat_arch_setup() | |
INFO: [ATF](0)[7.005323]mmap atf buffer : 0xff9c0000, 0x40000 | |
[ATF](0)[7.006479]mmap: | |
[ATF](0)[7.006738] VA:0x10f000 PA:0x10f000 size:0x2000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.007729] VA:0x11d000 PA:0x11d000 size:0x1000 attr:0x18 granularity:0x40000000 | |
[ATF](0)[7.008730] VA:0xc000000 PA:0xc000000 size:0x600000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.009764] VA:0x10006000 PA:0x10006000 size:0x100000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.010820] VA:0x10000000 PA:0x10000000 size:0x400000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.011875] VA:0x10400000 PA:0x10400000 size:0x50000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.012920] VA:0x10480000 PA:0x10480000 size:0x10000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.013964] VA:0x11000000 PA:0x11000000 size:0x4000000 attr:0x8 granularity:0x40000000 | |
[ATF](0)[7.015031] VA:0x54601000 PA:0x54601000 size:0x1c000 attr:0x2 granularity:0x40000000 | |
[ATF](0)[7.016075] VA:0x5462f000 PA:0x5462f000 | |
[831] fb dump: 0x00000000, 0x00000000, 0x00000000, 0x00000000 | |
[833] ovl start done idx = 0, addr = 0x1400b00c | |
[834] ovl start done addr0 = 0x1000 | |
[834] ovl start done addr1 = 0x0 | |
[834] ovl start done addr2 = 0x1400b00c | |
[835] ovl start done addr3 = 0x1400b00c | |
[835] ovl start done addr4 = 0x1400b00c | |
[836] s_mt65xx_gd.gdfIndex=3[836] mt_get_logo_db_addr_pa: 0x5e900000 | |
[836] [PART_LK][get_part] logo | |
[837] [PART_LK][get_part] logo | |
[837] | |
========================================= | |
[838] [LK_BOOT] logo magic number : 0x58881688 | |
[838] [LK_BOOT] logo name : logo | |
[839] [LK_BOOT] logo size : 1613370 | |
[839] ========================================= | |
SMART RESET: FALSE | |
rst from: unknown | |
kedump mini start | |
kedump: current time: [2010/1/1 0:0:6] | |
kedump: ddr reserve mode disabled | |
kedump: ddr reserve mode failed | |
[848] mblock[0].start: 0x40000000, sz: 0x80000, limit: 0xc0000000, max_addr: 0x0, target: -1, reserved_addr: 0x40000000,reserved_size: 0x80000 | |
[850] mblock_reserve dbg[0]: 1, 1, 1, 1 | |
[850] mblock[1].start: 0x4c880000, sz: 0x7780000, limit: 0xc0000000, max_addr: 0x40080000, target: 0, reserved_addr: 0x53f80000,reserved_size: 0x80000 | |
[852] mblock_reserve dbg[1]: 1, 1, 1, 1 | |
[852] mblock[2].start: 0x54080000, sz: 0xf80000, limit: 0xc0000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x54f80000,reserved_size: 0x80000 | |
[854] mblock_reserve dbg[2]: 1, 1, 1, 1 | |
[854] mblock[3].start: 0x56400000, sz: 0x500000, limit: 0xc0000000, max_addr: 0x55000000, target: 2, reserved_addr: 0x56880000,reserved_size: 0x80000 | |
[856] mblock_reserve dbg[3]: 1, 1, 1, 1 | |
[856] mblock[4].start: 0x5f900000, sz: 0x1c1e0000, limit: 0xc0000000, max_addr: 0x56900000, target: 3, reserved_addr: 0x7ba60000,reserved_size: 0x80000 | |
[858] mblock_reserve dbg[4]: 1, 1, 1, 1 | |
[858] mblock[5].start: 0x7da00000, sz: 0x25c0000, limit: 0xc0000000, max_addr: 0x7bae0000, target: 4, reserved_addr: 0x7ff40000,reserved_size: 0x80000 | |
[860] mblock_reserve dbg[5]: 1, 1, 1, 1 | |
[860] mblock[6].start: 0x80000000, sz: 0x40000000, limit: 0xc0000000, max_addr: 0x7ffc0000, target: 5, reserved_addr: 0xbff80000,reserved_size: 0x80000 | |
[862] mblock_reserve dbg[6]: 1, 1, 1, 1 | |
[863] mblock[7].start: 0xc0000000, sz: 0x3ef00000, limit: 0xc0000000, max_addr: 0xc0000000, target: 6, reserved_addr: 0xbff80000,reserved_size: 0x80000 | |
[864] mblock_reserve dbg[7]: 1, 0, 1, 1 | |
[865] mblock[8].start: 0xff000000, sz: 0x9c0000, limit: 0xc0000000, max_addr: 0xc0000000, target: 6, reserved_addr: 0xbff80000,reserved_size: 0x80000 | |
[866] mblock_reserve dbg[8]: 1, 0, 1, 1 | |
[867] mblock[9].start: 0x100000000, sz: 0x40000000, limit: 0xc0000000, max_addr: 0xc0000000, target: 6, reserved_addr: 0xbff80000,reserved_size: 0x80000 | |
[868] mblock_reserve dbg[9]: 1, 0, 1, 1 | |
[869] mblock_reserve: bff80000 - c0000000 from mblock 6 | |
[870] mblock_reserve [0].start: 0x40000000, sz: 0x80000 | |
[870] mblock_reserve [1].start: 0x4c880000, sz: 0x7780000 | |
[871] mblock_reserve [2].start: 0x54080000, sz: 0xf80000 | |
[871] mblock_reserve [3].start: 0x56400000, sz: 0x500000 | |
[872] mblock_reserve [4].start: 0x5f900000, sz: 0x1c1e0000 | |
[873] mblock_reserve [5].start: 0x7da00000, sz: 0x25c0000 | |
[873] mblock_reserve [6].start: 0x80000000, sz: 0x3ff80000 | |
[874] mblock_reserve [7].start: 0xc0000000, sz: 0x3ef00000 | |
[875] mblock_reserve [8].start: 0xff000000, sz: 0x9c0000 | |
[875] mblock_reserve [9].start: 0x100000000, sz: 0x40000000 | |
[876] mblock_reserve-R[0].start: 0x7ffc0000, sz: 0x40000 map:1 name:log_store | |
[877] mblock_reserve-R[1].start: 0xff9c0000, sz: 0x640000 map:0 name:tee | |
[878] mblock_reserve-R[2].start: 0xfef00000, sz: 0x100000 map:0 name:PICACHU | |
[879] mblock_reserve-R[3].start: 0x56000000, sz: 0x400000 map:0 name:lk_addr_mb | |
[879] mblock_reserve-R[4].start: 0x56900000, sz: 0x9000000 map:0 name:scratch_addr_mb | |
[880] mblock_reserve-R[5].start: 0x54000000, sz: 0x80000 map:0 name:dtb_kernel_addr_mb | |
[881] mblock_reserve-R[6].start: 0x40080000, sz: 0xc800000 map:0 name:kernel_addr_mb | |
[882] mblock_reserve-R[7].start: 0x55000000, sz: 0x1000000 map:0 name:ramdisk_addr_mb | |
[883] mblock_reserve-R[8].start: 0x7bae0000, sz: 0x1f20000 map:0 name:platform_init | |
[884] | |
[3347] [lc709203f_init] voltage before 4063 | |
[6357] [lc709203f_init] voltage after 4037 | |
[6365] [BATTERY:bq24160] charger enable=1 ! | |
[6367] bq24160_dump_register | |
[6367] [0x0]=0x40 | |
[6368] [0x1]=0xc0 | |
[6369] [0x2]=0x8c | |
[6369] [0x3]=0xa4 | |
[6370] [0x4]=0x45 | |
[6370] [0x5]=0x54 | |
[6371] [0x6]=0x0 | |
[6372] [0x7]=0x58 | |
[6373] [mt65xx_bat_init] g_capacity_status=[80] | |
[6373] [lc709203f_init] | |
[6374] [lc709203f_check_power_on] lc709203f_get_ic_power_mode [0x1] | |
[6376] [lc709203f_check_power_on] lc709203f_get_thermistor_b [0xd34] | |
[6377] [lc709203f_check_power_on] lc709203f_get_adjustment_pack_appli [0xb4] | |
[6378] [lc709203f_check_power_on] 1 | |
[6379] mtk detect key function key = 0 | |
[6380] [lk logo: mt_disp_show_boot_logo 135] | |
[6380] [lk logo: init_fb_screen 59] | |
[6381] mt_get_logo_db_addr: 0x5e900000 | |
[6381] [lk logo: init_fb_screen 77]MTK_LCM_PHYSICAL_ROTATION = 270 | |
[6382] [lk logo: sync_anim_version 42] | |
[6382] [lk logo: init_fb_screen 100]pinfo[0]=0x0000002a, pinfo[1]=0x00189e3a, pinfo[2]=176 | |
[6383] [lk logo: init_fb_screen 102]define ANIMATION_NEW:show new animation with capacity num | |
[6384] [lk logo: init_fb_screen 103]CAPACITY_LEFT =172, CAPACITY_TOP =330 | |
[6385] [lk logo: init_fb_screen 104]LCM_HEIGHT=307, LCM_WIDTH=546 | |
[6386] mt_get_tempfb_addr: 0x7ccb0000 ,fb_addr 0x7bae0000 | |
[6387] [show_animation_common: check_logo_index_valid 71]logonum =42, index =0 | |
[6387] show_animation_common, in_addr=0x5e9000b0, logolen=35427 | |
[6388] [decompress_logo decompress_logo 48]in=0x5e9000b0, out=0x7ccb0000, inlen=35427, logolen=9338880 | |
[6428] [decompress_logo decompress_logo 97]have=9216000 | |
[6429] [show_animation_common: fill_animation_logo 124]bits = 32 | |
[6429] [show_logo_common: fill_rect_with_content 474] | |
[6430] [show_logo_common: fill_rect_with_content_by_32bit_argb8888 149] | |
[6492] [show_logo_common: fill_rect_with_content_by_32bit_argb8888 213] | |
[6492] fb dump: 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff | |
[6495] [LEDS]LK: mt65xx_backlight_on:level = 63 | |
[6495] [LEDS]LK: lcd-backlight level is 63 | |
[6496] cust->mode is 6 | |
[6496] cust->mode E cust_data= 0x56017bfd; level =63 | |
[6497] [LEDS]LK: mt65xx_leds_brightness_set is done | |
[6497] mtk detect key function key = 0 | |
[6498] [lk logo: mt_disp_show_boot_logo 135] | |
[6498] [lk logo: init_fb_screen 59] | |
[6499] mt_get_logo_db_addr: 0x5e900000 | |
[6499] [lk logo: init_fb_screen 77]MTK_LCM_PHYSICAL_ROTATION = 270 | |
[6500] [lk logo: sync_anim_version 42] | |
[6500] [lk logo: init_fb_screen 100]pinfo[0]=0x0000002a, pinfo[1]=0x00189e3a, pinfo[2]=176 | |
[6501] [lk logo: init_fb_screen 102]define ANIMATION_NEW:show new animation with capacity num | |
[6502] [lk logo: init_fb_screen 103]CAPACITY_LEFT =172, CAPACITY_TOP =330 | |
[6503] [lk logo: init_fb_screen 104]LCM_HEIGHT=307, LCM_WIDTH=546 | |
[6504] mt_get_tempfb_addr: 0x7ccb0000 ,fb_addr 0x7bae0000 | |
[6504] [show_animation_common: check_logo_index_valid 71]logonum =42, index =0 | |
[6505] show_animation_common, in_addr=0x5e9000b0, logolen=35427 | |
[6506] [decompress_logo decompress_logo 48]in=0x5e9000b0, out=0x7ccb0000, inlen=35427, logolen=9338880 | |
[6546] [decompress_logo decompress_logo 97]have=9216000 | |
[6547] [show_logo_common: fill_rect_with_content 474] | |
[6547] [show_logo_common: fill_rect_with_content_by_32bit_argb8888 149] | |
[6609] [show_logo_common: fill_rect_with_content_by_32bit_argb8888 213] | |
[6610] fb dump: 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff | |
[6612] [LEDS]LK: mt65xx_backlight_on:level = 63 | |
[6612] [LEDS]LK: mt65xx_leds_brightness_set is done | |
[6613] fb dump: 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff | |
[LK_ENV]get_env MTK_DEVICE_ID | |
[6616] [PART_LK][get_part] proinfo | |
[6616] [LK_BOOT] Load 'proinfo' partition to 0x560A6788 (19 bytes in 0 ms) | |
[6617] Serial #: "0L0V041811" | |
[6619] mblock[0].start: 0x40000000, sz: 0x80000, limit: 0xc0000000, max_addr: 0x0, target: -1, reserved_addr: 0x39c80000,reserved_size: 0x6400000 | |
[6620] mblock_reserve dbg[0]: 1, 0, 1, 1 | |
[6621] mblock[1].start: 0x4c880000, sz: 0x7780000, limit: 0xc0000000, max_addr: 0x0, target: -1, reserved_addr: 0x4dc00000,reserved_size: 0x6400000 | |
[6622] mblock_reserve dbg[1]: 1, 1, 1, 1 | |
[6623] mblock[2].start: 0x54080000, sz: 0xf80000, limit: 0xc0000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x4ec00000,reserved_size: 0x6400000 | |
[6624] mblock_reserve dbg[2]: 1, 0, 1, 1 | |
[6625] mblock[3].start: 0x56400000, sz: 0x500000, limit: 0xc0000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x50500000,reserved_size: 0x6400000 | |
[6627] mblock_reserve dbg[3]: 1, 0, 1, 1 | |
[6627] mblock[4].start: 0x5f900000, sz: 0x1c1e0000, limit: 0xc0000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x756e0000,reserved_size: 0x6400000 | |
[6629] mblock_reserve dbg[4]: 1, 1, 1, 1 | |
[6629] mblock[5].start: 0x7da00000, sz: 0x25c0000, limit: 0xc0000000, max_addr: 0x7bae0000, target: 4, reserved_addr: 0x79bc0000,reserved_size: 0x6400000 | |
[6631] mblock_reserve dbg[5]: 1, 0, 1, 1 | |
[6631] mblock[6].start: 0x80000000, sz: 0x3ff80000, limit: 0xc0000000, max_addr: 0x7bae0000, target: 4, reserved_addr: 0xb9b80000,reserved_size: 0x6400000 | |
[6633] mblock_reserve dbg[6]: 1, 1, 1, 1 | |
[6633] mblock[7].start: 0xc0000000, sz: 0x3ef00000, limit: 0xc0000000, max_addr: 0xbff80000, target: 6, reserved_addr: 0xb9c00000,reserved_size: 0x6400000 | |
[6635] mblock_reserve dbg[7]: 1, 0, 1, 1 | |
[6636] mblock[8].start: 0xff000000, sz: 0x9c0000, limit: 0xc0000000, max_addr: 0xbff80000, target: 6, reserved_addr: 0xb9c00000,reserved_size: 0x6400000 | |
[6637] mblock_reserve dbg[8]: 1, 0, 1, 1 | |
[6638] mblock[9].start: 0x100000000, sz: 0x40000000, limit: 0xc0000000, max_addr: 0xbff80000, target: 6, reserved_addr: 0xb9c00000,reserved_size: 0x6400000 | |
[6639] mblock_reserve dbg[9]: 1, 0, 1, 1 | |
[6640] mblock_reserve: b9b80000 - bff80000 from mblock 6 | |
[6641] mblock_reserve [0].start: 0x40000000, sz: 0x80000 | |
[6641] mblock_reserve [1].start: 0x4c880000, sz: 0x7780000 | |
[6642] mblock_reserve [2].start: 0x54080000, sz: 0xf80000 | |
[6643] mblock_reserve [3].start: 0x56400000, sz: 0x500000 | |
[6643] mblock_reserve [4].start: 0x5f900000, sz: 0x1c1e0000 | |
[6644] mblock_reserve [5].start: 0x7da00000, sz: 0x25c0000 | |
[6645] mblock_reserve [6].start: 0x80000000, sz: 0x39b80000 | |
[6645] mblock_reserve [7].start: 0xc0000000, sz: 0x3ef00000 | |
[6646] mblock_reserve [8].start: 0xff000000, sz: 0x9c0000 | |
[6647] mblock_reserve [9].start: 0x100000000, sz: 0x40000000 | |
[6647] mblock_reserve-R[0].start: 0x7ffc0000, sz: 0x40000 map:1 name:log_store | |
[6648] mblock_reserve-R[1].start: 0xff9c0000, sz: 0x640000 map:0 name:tee | |
[6649] mblock_reserve-R[2].start: 0xfef00000, sz: 0x100000 map:0 name:PICACHU | |
[6650] mblock_reserve-R[3].start: 0x56000000, sz: 0x400000 map:0 name:lk_addr_mb | |
[6651] mblock_reserve-R[4].start: 0x56900000, sz: 0x9000000 map:0 name:scratch_addr_mb | |
[6652] mblock_reserve-R[5].start: 0x54000000, sz: 0x80000 map:0 name:dtb_kernel_addr_mb | |
[6653] mblock_reserve-R[6].start: 0x40080000, sz: 0xc800000 map:0 name:kernel_addr_mb | |
[6654] mblock_reserve-R[7].start: 0x55000000, sz: 0x1000000 map:0 name:ramdisk_addr_mb | |
[6654] mblock_reserve-R[8].start: 0x7bae0000, sz: 0x1f20000 map:0 name:platform_init | |
[6655] mblock_reserve-R[9].start: 0xbff80000, sz: 0x80000 map:0 name:atf-ramdump-memory | |
[6656] mblock_reserve-R[10].start: 0xb9b80000, sz: 0x6400000 map:0 name:avb | |
[SBC] S-CHIP | |
[6659] [SEC_POLICY] sboot_state = 0x1 | |
[6659] [SEC_POLICY] lock_state = 0x4 | |
[6659] [avb] img_auth_required = 1 | |
[6873] [AVB20] lock_state = 0x4 | |
[6874] [PART_LK][get_part] system | |
[6874] [PART_LK][get_part] boot | |
[6875] [PART_LK][get_part] vbmeta | |
[SBC] S-CHIP | |
[6876] [SEC_POLICY] sboot_state = 0x1 | |
[6877] [SEC_POLICY] lock_state = 0x4 | |
[6877] [avb] img_auth_required = 1 | |
[6898] [avb] cmdline = dm="1 vroot none ro 1,0 2716984 verity 1 PARTUUID=15947f6b-38aa-4e7c-8bdf-1adb98632d7e PARTUUID=15947f6b-38aa-4e7c-8bdf-1adb98632d7e 4096 4096 339623 339623 sha1 85a7824f7cf8e6c015432c657774ab9c9f2d92b9 95180092a2a9db10da47b2c8d0b5a239af3d9e3d9c49e87fccb81701cf2ee3c3 10 restart_on_corruption ignore_zero_blocks use_fec_from_device PARTUUID=15947f6b-38aa-4e7c-8bdf-1adb98632d7e fec_roots 2 fec_blocks 342299 fec_start 342299" root=/dev/dm-0 androidboot.vbmeta.device=PARTUUID=78630870-afb8-4e2c-9108-847a27e90dc9 androidboot.vbmeta.avb_version=1.1 androidboot.vbmeta.device_state=locked androidboot.vbmeta.invalidate_on_error=yes androidboot.veritymode=enforcing | |
[6905] [avb] boot/recovery vfy time = 288 ms | |
[6906] mblock_create mblock start b9b80000 size: 6400000 | |
[6906] [avb] ret = 0 | |
[6908] [LK] check_ota_result = 0 | |
[6908] [LK] ota-fail | |
[6909] boot state: green | |
[6909] [PROFILE] ::: lvl(1) load boot image takes 292 ms | |
[7152] [PROFILE] ::: lvl(1) decompress_kernel takes 241 ms | |
[7153] model=MT8168A | |
[7153] efuse set max_clk_freq=1300000000 | |
[7153] cluster-0: 4 core | |
[7155] PASS memory DTS node | |
[7156] LASTPC[0][0] = fffa1fc8 | |
[7156] LASTPC[0][1] = ffff3b30 | |
[7156] LASTPC[0][2] = 81028291 | |
[7157] LASTPC[0][3] = 80000055 | |
[7157] LASTPC[0][4] = 10081900 | |
[7157] LASTPC[0][5] = 410d6824 | |
[7158] LASTPC[0][6] = 1d40c83d | |
[7158] LASTPC[0][7] = 61e88240 | |
[7158] LASTPC[1][0] = 0 | |
[7159] LASTPC[1][1] = 0 | |
[7159] LASTPC[1][2] = 0 | |
[7159] LASTPC[1][3] = 0 | |
[7160] LASTPC[1][4] = 0 | |
[7160] LASTPC[1][5] = 0 | |
[7160] LASTPC[1][6] = 0 | |
[7160] LASTPC[1][7] = 0 | |
[7161] LASTPC[2][0] = 0 | |
[7161] LASTPC[2][1] = 0 | |
[7161] LASTPC[2][2] = 0 | |
[7162] LASTPC[2][3] = 0 | |
[7162] LASTPC[2][4] = 0 | |
[7162] LASTPC[2][5] = 0 | |
[7162] LASTPC[2][6] = 0 | |
[7163] LASTPC[2][7] = 0 | |
[7163] LASTPC[3][0] = 0 | |
[7163] LASTPC[3][1] = 0 | |
[7163] LASTPC[3][2] = 0 | |
[7164] LASTPC[3][3] = 0 | |
[7164] LASTPC[3][4] = 0 | |
[7164] LASTPC[3][5] = 0 | |
[7165] LASTPC[3][6] = 0 | |
[7165] LASTPC[3][7] = 0 | |
[7169] target_atag_imix_r:170 | |
[7170] fg_swocv_v buf [0], [0x560c8128:0x560c8129:1] | |
[7171] fg_swocv_i buf [0], [0x560c8128:0x560c8129:1] | |
[7172] shutdown_time buf [0], [0x560c8128:0x560c8129:1] | |
[7173] boot_voltage buf [0], [0x560c8128:0x560c8129:1] | |
[7174] boot_voltage buf [0], [0x560c8128:0x560c8129:1] | |
[7175] Not Support VCORE DVFS | |
[7175] mt_disp_get_lcd_time, fps=0 | |
[7176] videolfb - fb_base = 0x7bae0000 | |
[7176] videolfb - islcmfound = 0 | |
[7177] videolfb - fps = 6000 | |
[7177] videolfb - vram = 32636928 | |
[7178] videolfb - lcmname = kd101n92_45ni_a003_dsi | |
[7179] [ccci] modem mem arguments info using default | |
[7180] PTP_INFO Only support in MT6795 | |
start dump lk masp atag | |
dump sw sbc:0x22, sw sdl:0x22 , hw sbc: 1 | |
dump lock_state, 0x1 | |
[7183] create masp atag OK | |
[7183] tee_reserved_mem not supported | |
[7183] [LK] non_secure_sram (0x111d00, 0x300) | |
[7184] [PROFILE] ::: lvl(0) 1st logo takes 0 ms | |
[7185] [PROFILE] ::: lvl(0) boot_time takes 7184 ms | |
[7185] mblock[0].start: 0x40000000, sz: 0x80000, limit: 0x100000000, max_addr: 0x0, target: -1, reserved_addr: 0x40000000,reserved_size: 0x80000 | |
[7187] mblock_reserve dbg[0]: 1, 1, 1, 1 | |
[7187] mblock[1].start: 0x4c880000, sz: 0x7780000, limit: 0x100000000, max_addr: 0x40080000, target: 0, reserved_addr: 0x50000000,reserved_size: 0x80000 | |
[7189] mblock_reserve dbg[1]: 1, 1, 1, 1 | |
[7190] mblock[2].start: 0x54080000, sz: 0xf80000, limit: 0x100000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x50000000,reserved_size: 0x80000 | |
[7191] mblock_reserve dbg[2]: 1, 0, 1, 1 | |
[7192] mblock[3].start: 0x56400000, sz: 0x500000, limit: 0x100000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x50000000,reserved_size: 0x80000 | |
[7193] mblock_reserve dbg[3]: 1, 0, 1, 1 | |
[7194] mblock[4].start: 0x5f900000, sz: 0x1c1e0000, limit: 0x100000000, max_addr: 0x54000000, target: 1, reserved_addr: 0x70000000,reserved_size: 0x80000 | |
[7196] mblock_reserve dbg[4]: 1, 1, 1, 1 | |
[7196] mblock[5].start: 0x7da00000, sz: 0x25c0000, limit: 0x100000000, max_addr: 0x7bae0000, target: 4, reserved_addr: 0x70000000,reserved_size: 0x80000 | |
[7198] mblock_reserve dbg[5]: 1, 0, 1, 1 | |
[7198] mblock[6].start: 0x80000000, sz: 0x3ff80000, limit: 0x100000000, max_addr: 0x7bae0000, target: 4, reserved_addr: 0xb0000000,reserved_size: 0x80000 | |
[7200] mblock_reserve dbg[6]: 1, 1, 1, 1 | |
[7200] mblock[7].start: 0xc0000000, sz: 0x3ef00000, limit: 0x100000000, max_addr: 0xbff80000, target: 6, reserved_addr: 0xf0000000,reserved_size: 0x80000 | |
[7202] mblock_reserve dbg[7]: 1, 1, 1, 1 | |
[7202] mblock[8].start: 0xff000000, sz: 0x9c0000, limit: 0x100000000, max_addr: 0xfef00000, target: 7, reserved_addr: 0xf0000000,reserved_size: 0x80000 | |
[7204] mblock_reserve dbg[8]: 1, 0, 1, 1 | |
[7205] mblock[9].start: 0x100000000, sz: 0x40000000, limit: 0x100000000, max_addr: 0xfef00000, target: 7, reserved_addr: 0xf0000000,reserved_size: 0x80000 | |
[7206] mblock_reserve dbg[9]: 1, 0, 1, 1 | |
[7207] mblock[7]: c0000000, 30000000 from mblock | |
mblock[8]: f0080000, ee80000 from mblock | |
[7208] mblock_reserve: f0000000 - f0080000 from mblock 7 | |
[7208] mblock_re | |
[ 0.000000] <0>-(0)[0:swapper]psci: probing for conduit method from DT. | |
[ 0.000000] <0>-(0)[0:swapper]psci: PSCIv1.1 detected in firmware. | |
[ 0.000000] <0>-(0)[0:swapper]psci: Using standard PSCI v0.2 function IDs | |
[ 0.000000] <0>-(0)[0:swapper]psci: Trusted OS migration not required | |
[ 0.000000] <0>-(0)[0:swapper]psci: SMC Calling Convention v1.1 | |
[ 0.000000] <0>-(0)[0:swapper]random: get_random_bytes called from start_kernel+0xa4/0x41c with crng_init=0 | |
[ 0.000000] <0>-(0)[0:swapper]percpu: Embedded 26 pages/cpu @ffffffc0fff2b000 s67480 r8192 d30824 u106496 | |
[ 0.000000] <0>-(0)[0:swapper]Detected VIPT I-cache on CPU0 | |
[ 0.000000] <0>-(0)[0:swapper]CPU features: enabling workaround for ARM erratum 845719 | |
[ 0.000000] <0>-(0)[0:swapper]Built 1 zonelists, mobility grouping on. Total pages: 1014128 | |
[ 0.000000] <0>-(0)[0:swapper]Kernel command line: console=tty0 console=ttyS0,921600n1 earlycon=uart8250,mmio32,0x11002000 vmalloc=496M androidboot.hardware=mt8168 firmware_class.path=/vendor/firmware loop.max_part=7 has_battery_removed=1 skip_initramfs ro rootwait init=/init dm="1 vroot none ro 1,0 2716984 verity 1 PARTUUID=15947f6b-38aa-4e7c-8bdf-1adb98632d7e PARTUUID=15947f6b-38aa-4e7c-8bdf-1adb98632d7e 4096 4096 339623 339623 sha1 85a7824f7cf8e6c015432c657774ab9c9f2d92b9 95180092a2a9db10da47b2c8d0b5a239af3d9e3d9c49e87fccb81701cf2ee3c3 10 restart_on_corruption ignore_zero_blocks use_fec_from_device PARTUUID=15947f6b-38aa-4e7c-8bdf-1adb98632d7e fec_roots 2 fec_blocks 342299 fec_start 342299" root=/dev/dm-0 androidboot.vbmeta.device=PARTUUID=78630870-afb8-4e2c-9108-847a27e90dc9 androidboot.vbmeta.avb_version=1.1 androidboot.vbmeta.device_state=locked androidboot.vbmeta.invalidate_on_error=yes androidboot.veritymode=enforcing androidboot.verifiedbootstate=green bootopt=64S3,32N2,64N2 buildvar | |
[ 0.000000] <0>-(0)[0:swapper]device-mapper: init: will configure 1 devices | |
[ 0.000000] -(0)[0:swapper]PID hash table entries: 4096 (order: 3, 32768 bytes) | |
[ 0.000000] -(0)[0:swapper]Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) | |
[ 0.000000] -(0)[0:swapper]Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) | |
[ 0.000000] -(0)[0:swapper]software IO TLB [mem 0xfaf00000-0xfef00000] (64MB) mapped at [ffffffc0baf00000-ffffffc0beefffff] | |
[ 0.000000] -(0)[0:swapper]Memory: 3959384K/4122048K available (12412K kernel code, 1190K rwdata, 4164K rodata, 960K init, 3937K bss, 162664K reserved, 0K cma-reserved) | |
[ 0.000000] -(0)[0:swapper]Virtual kernel memory layout: | |
[ 0.000000] -(0)[0: | |
[ 0.094511] -(1)[0:swapper/1]Detected VIPT I-cache on CPU1 | |
[ 0.094543] -(1)[0:swapper/1]GICv3: CPU1: found redistributor 1 region 0:0x000000000c0a0000 | |
[ 0.094574] -(1)[0:swapper/1]CPU1: Booted secondary processor [410fd034] | |
[ 0.102687] -(2)[103841] -(3)[0:swapper/3]CPU3: Booted secondary processor [410fd034] | |
[ 0.103995] -(0)[1:swapper/0]smp: Brought up 1 node, 4 CPUs | |
[ 0.112717] -(0)[1:swapper/0]SMP: Total of 4 processors activated. | |
[ 0.113518] -(0)[1:swapper/0]CPU features: detected feature: GIC system register CPU interface | |
[ 0.114633] -(0)[1:swapper/0]CPU features: detected feature: 32-bit EL0 Support | |
[ 0.115587] -(0)[1:swapper/0]CPU features: detected feature: Kernel page table isolation (KPTI) | |
[ 0.118838] -(0)[1:swapper/0]CPU: All CPU(s) started at EL2 | |
[ 0.119573] -(0)[11:migration/0]alternatives: patching kernel code | |
[ 0.120575] -(0)[1:swapper/0]Sort hmp_domains from little to big: | |
[ 0.121365] -(0)[1:swapper/0] cpumask: 0x0f | |
[ 0.121941] -(0)[1:swapper/0]Initializing HMP scheduler: | |
[ 0.122629] -(0)[1:swapper/0]Initializing HMP scheduler done | |
[ 0.123417] -(0)[1:swapper/0]CPU3: update max cpu_capacity 1024 | |
[ 0.123430] -(0)[1:swapper/0]WARN: cpu=0, domain=DIE: incr. energy eff 871[0]->920[1] | |
[ 0.125218] -(0)[1:swapper/0]WARN: cpu=0, domain=DIE: incr. energy eff 920[1]->958[2] | |
[ 0.126232] -(0)[1:swapper/0]WARN: cpu=0, domain=DIE: incr. energy eff 958[2]->965[3] | |
[ 0.127245] -(0)[1:swapper/0]WARN: cpu=0, domain=DIE: incr. energy eff 965[3]->965[4] | |
[ 0.136309] -(0)[1:swapper/0]Registered cp15_barrier emulation handler | |
[ 0.137166] -(0)[1:swapper/0]Registered setend emulation handler | |
[ 0.138106] -(1)[16:kworker/1:0]CPU1: update max cpu_capacity 1024 | |
[ 0.138174] -(0)[1:swapper/0]clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns | |
[ 0.140429] -(0)[1:swapper/0]futex hash table entries: 1024 (order: 4, 65536 bytes) | |
[ 0.141570] -(0)[1:swapper/0]pinctrl core: initialized pinctrl subsystem | |
[ 0.142956] -(0)[1:swapper/0]DMI not present or invalid. | |
[ 0.143780] -(0)[1:swapper/0]NET: Registered protocol family 16 | |
[ 0.145282] -(0)[1:swapper/0]schedtune: configured to support 5 boost groups | |
[ 0.146276] -(0)[1:swapper/0]ramoops: using module parameters | |
[ 0.147101] -(0)[1:swapper/0]ramoops: pstore:address is 0x54410000, size is 0xe0000, console_size is 0x40000, pmsg_size is 0x10000 | |
[ 0.148796] -(0)[1:swapper/0]pstore: using zlib compression | |
[ 0.149906] -(0)[1:swapper/0]console [pstore-1] enabled | |
[ 0.150631] -(0)[1:swapper/0]pstore: Registered ramoops as persistent store backend | |
[ 0.151637] -(0)[1:swapper/0]ramoops: attached 0xe0000@0x54410000, ecc: 0/0 | |
[ 0.152715] -(0)[1:swapper/0]mt_pwrap_init++++ | |
[ 0.153397] -(0)[1:swapper/0]PWRAP reg: 0xffffff80096fc000, irq: 7 | |
[ 0.154411] -(0)[1:swapper/0]is_pwrap_init_done 1 | |
[ 0.155053] -(0)[1:swapper/0]mt_pwrap_init---- | |
[ 0.155858] -(1)[1:swapper/0]cpuidle: using governor menu | |
[ 0.157271] -(1)[1:swapper/0]vdso: 2 pages (1 code @ ffffff8008ca6000, 1 data @ ffffff80091b4000) | |
[ 0.158426] -(1)[1:swapper/0]hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. | |
[ 0.159694] -(0)[1:swapper/0]DMA: preallocated 256 KiB pool for atomic allocations | |
[ 0.160760] -(0)[1:swapper/0]mrdump_cblock_init: no mrdump_cb | |
[ 0.161561] -(0)[1:swapper/0]mirdump: reserved 544f0000+8000->ffffff80097d3000 | |
[ 0.161707] -(0)[1:swapper/0]mrdump_full_init: MT-RAMDUMP no control block | |
[ 0.163773] -(0)[1:swapper/0] | |
[ 0.163773] MTK_SIP_KERNEL_WDT - 0xffffff80086add00 | |
[ 0.164809] -(0)[1:swapper/0] | |
[ 0.164809] atf_aee_debug_virt_addr = 0xffffff80097e8000 | |
[ 0.165929] -(0)[1:swapper/0][CMDQ]cmdq_init enter | |
[ 0.165977] -(0)[1:swapper/0][cmdq] cmdq_init enter | |
[ 0.201306] -(0)[1:swapper/0]BOOTPROF: 201.303461:probe: probe=platform_drv_probe drv=clk-mt8168(ffffff8009226950) 18.248384ms | |
[ 0.206302] -(0)[1:swapper/0]mtk pctrl init OK | |
[ 0.210040] -(0)[1:swapper/0][EMI] module probe. | |
[ 0.21066 |
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