preemptlog.patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e6d70cc..b95faaf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1164,6 +1164,7 @@ emit_preemption_control(struct drm_i915_gem_request *req)
 	u32 mid_thread_mode = 0;
 	u32 data;
 
+	DRM_DEBUG_DRIVER("AAA\n");
 	/* Preemption is always disabled while preempting */
 	if (req->scheduler_flags & I915_REQ_SF_PREEMPT) {
 		data = MI_ARB_ON_OFF | MI_ARB_DISABLE;
@@ -1172,6 +1173,8 @@ emit_preemption_control(struct drm_i915_gem_request *req)
 		return;
 	}
 
+	DRM_DEBUG_DRIVER("BBB\n");
+
 	/* At level 0, no preemption will be attempted */
 	if (preemption_level == 0)
 		return;
@@ -1237,6 +1240,7 @@ emit_preemption_control(struct drm_i915_gem_request *req)
 		/* XXX: any further levels of preemption? */
 	default:
 		/* Default is the maximum level permitted by the hardware */
+		DRM_DEBUG_DRIVER("!!!!!preemption enabled\n");
 		return;
 	}
 
@@ -1270,6 +1274,8 @@ emit_preemption_control(struct drm_i915_gem_request *req)
 	intel_logical_ring_emit_reg(ringbuf, GEN8_CS_CHICKEN1);
 	intel_logical_ring_emit(ringbuf, mid_thread_mode | allow_mid_object);
 	intel_logical_ring_emit(ringbuf, MI_NOOP);
+	DRM_DEBUG_DRIVER("preemption_level=%d, allow_user_control=%u, allow_mid_object=%u\n",
+			 preemption_level, allow_user_control, allow_mid_object);
 }
 
 /*
@@ -3286,4 +3292,3 @@ void intel_lr_context_reset(struct intel_context *ctx)
 		intel_lr_context_resync(ctx, engine, true);
 	}
 }
-