gistfile1.txt

upstream code:
} else if (!strcmp(vdd->voltdm.name, "core")) {
                vdd->volt_data = omap44xx_vdd_core_volt_data;
                vdd->vp_reg.tranxdone_status =
                                OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
                vdd->vc_reg.cmdval_reg =
                                OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
                vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
                vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK;
                vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
                vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK;
                vdd->vc_reg.voltsetup_reg =
                                OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
...

voltage split code:
+       .vc_reg = {
+               .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
+               .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
+               .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
+               .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
+               .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
+               .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+       },
+       .voltdm = {
+               .name = "core",
+       },