pic18f4480-xc8-template.c

////////////////////////////////////////////////////////////////////////////////

// PIC18F4480 Configuration Bit Settings

// 'C' source line config statements

#include <xc.h>

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1H
#pragma config OSC = HS    // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = BOHW     // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3         // Brown-out Reset Voltage bits (VBOR set to 2.1V)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = ON     // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for low-power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config BBSIZ = 1024     // Boot Block Size Select bit (1K words (2K bytes) boot block)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)

////////////////////////////////////////////////////////////////////////////////


#include <stdio.h>
#include <stdlib.h>


//  Programming 
//  DEBUG:   only work with debug tool attached
//  RELEASE: working standalone
//
//  OSC1,OSC2 - xtal 20mhz caps 15pF to VSS
//
//  Connect VDD to MCLR using 1N4148 Diode 
//  MCLR - ---|<|-- 1N4148 --- VDD
//
//
//              |---------|
//  MCLR (ISP) -| 1    40 |- RB7 / PGD(ISP)
//  RA0        -| 2    39 |- RB6 / PGC(ISP)
//  RA1        -| 3    38 |- RB5
//  RA2        -| 4    37 |- RB4
//  RA3        -| 5    36 |- RB3
//  RA4        -| 6    35 |- RB2
//  RA5        -| 7    34 |- RB1
//  RE0        -| 8    33 |- RB0
//  RE1        -| 9    32 |- VDD (ISP)
//  RE2        -| 10   31 |- VSS (ISP)
//  VDD        -| 11   30 |- RD7
//  VSS        -| 12   29 |- RD6
//  OSC1       -| 13   28 |- RD5
//  OSC2       -| 14   27 |- RD4
//  RC0        -| 15   26 |- RC7 (USART-RX)
//  RC1        -| 16   25 |- RC6 (USART-TX)
//  RC2        -| 17   24 |- RC5
//  RC3        -| 18   23 |- RC4
//  RD0        -| 19   22 |- RD3
//  RD1        -| 20   21 |- RD2
//              |---------|




// crystal 20mhz capacitors 15pF
#define _XTAL_FREQ 20000000 
#define USE_AND_MASKS


//
void Delay1Second()
{
    int i;
    for(i=0;i<100;i++)
    {
         __delay_ms(10);
    }
}

char txt[10];

int main(int argc, char** argv) {
    

    TRISCbits.RC6 = 0; //TX pin set as output
    TRISCbits.RC7 = 1; //RX pin set as input

    TRISAbits.RA0 = 0;

    unsigned char UART1Config = USART_TX_INT_OFF & USART_RX_INT_OFF & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_BRGH_HIGH ;
    //SYNC = 0, BRGH = 1, BRG16 = 0, FOSC=20mhz
    //115200 = 113636 = -1.36% -> SPBRG=10
    /* 
     * 
     * using BusPirate to auto detect baudrate
    UART>(0)
 0.Macro menu
 1.Transparent bridge
 2.Live monitor
 3.Bridge with flow control
 4.Auto Baud Detection
UART>(4) 
Waiting activity...
Calculated:     115942 bps
Estimated:      115200 bps
UART>
*/
    
    unsigned char baud = 10;
    OpenUSART(UART1Config,baud);


    int i=0;
    while(1) //infinite loop
    {
        //LED blink
       LATAbits.LA0 = (i%2);

       //
       sprintf(txt,"%d\r\n",i);
       putsUSART(txt);

       //
       Delay1Second();

       //
       i++;

    }
    
    return (EXIT_SUCCESS);
}