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December 7, 2018 06:44
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out/kernel/seccomp.o: file format elf32-littlearm | |
Disassembly of section .text: | |
00000000 <arch_seccomp_spec_mitigate>: | |
0: e12fff1e bx lr | |
00000004 <get_seccomp_filter>: | |
4: e5900534 ldr r0, [r0, #1332] ; 0x534 | |
8: e3500000 cmp r0, #0 | |
c: 012fff1e bxeq lr | |
10: f590f000 pldw [r0] | |
14: e1901f9f ldrex r1, [r0] | |
18: e2811001 add r1, r1, #1 | |
1c: e1802f91 strex r2, r1, [r0] | |
20: e3320000 teq r2, #0 | |
24: 1afffffa bne 14 <get_seccomp_filter+0x10> | |
28: e12fff1e bx lr | |
0000002c <put_seccomp_filter>: | |
2c: e92d4830 push {r4, r5, fp, lr} | |
30: e5904534 ldr r4, [r0, #1332] ; 0x534 | |
34: e3540000 cmp r4, #0 | |
38: 0a000011 beq 84 <put_seccomp_filter+0x58> | |
3c: f57ff05b dmb ish | |
40: f594f000 pldw [r4] | |
44: e1940f9f ldrex r0, [r4] | |
48: e2400001 sub r0, r0, #1 | |
4c: e1841f90 strex r1, r0, [r4] | |
50: e3310000 teq r1, #0 | |
54: 1afffffa bne 44 <put_seccomp_filter+0x18> | |
58: e3500000 cmp r0, #0 | |
5c: f57ff05b dmb ish | |
60: 1a000007 bne 84 <put_seccomp_filter+0x58> | |
64: e594000c ldr r0, [r4, #12] | |
68: e5945008 ldr r5, [r4, #8] | |
6c: ebfffffe bl 0 <bpf_prog_destroy> | |
70: e1a00004 mov r0, r4 | |
74: ebfffffe bl 0 <kfree> | |
78: e3550000 cmp r5, #0 | |
7c: e1a04005 mov r4, r5 | |
80: 1affffed bne 3c <put_seccomp_filter+0x10> | |
84: e8bd8830 pop {r4, r5, fp, pc} | |
00000088 <__secure_computing>: | |
88: e92d4800 push {fp, lr} | |
8c: e1a01000 mov r1, r0 | |
90: e3a0000c mov r0, #12 | |
94: e1a0200d mov r2, sp | |
98: e3510000 cmp r1, #0 | |
9c: e7cc2010 bfi r2, r0, #0, #13 | |
a0: e5920000 ldr r0, [r2] | |
a4: e5902530 ldr r2, [r0, #1328] ; 0x530 | |
a8: 05900004 ldreq r0, [r0, #4] | |
ac: 02800048 addeq r0, r0, #72 ; 0x48 | |
b0: 11a00001 movne r0, r1 | |
b4: e3520002 cmp r2, #2 | |
b8: e5900000 ldr r0, [r0] | |
bc: 0a00000b beq f0 <__secure_computing+0x68> | |
c0: e3520001 cmp r2, #1 | |
c4: 1a00000c bne fc <__secure_computing+0x74> | |
c8: e3500004 cmp r0, #4 | |
cc: 8a000003 bhi e0 <__secure_computing+0x58> | |
d0: e3a01001 mov r1, #1 | |
d4: e3a0201a mov r2, #26 | |
d8: e1120011 tst r2, r1, lsl r0 | |
dc: 1a000001 bne e8 <__secure_computing+0x60> | |
e0: e35000ad cmp r0, #173 ; 0xad | |
e4: 1a000006 bne 104 <__secure_computing+0x7c> | |
e8: e3a00000 mov r0, #0 | |
ec: e8bd8800 pop {fp, pc} | |
f0: e3a02000 mov r2, #0 | |
f4: e8bd4800 pop {fp, lr} | |
f8: ea000003 b 10c <__seccomp_filter> | |
fc: e7f001f2 udf #18 | |
100: eafffffe b 100 <__secure_computing+0x78> | |
104: e3a00009 mov r0, #9 | |
108: ebfffffe bl 0 <do_exit> | |
0000010c <__seccomp_filter>: | |
10c: e92d4bf0 push {r4, r5, r6, r7, r8, r9, fp, lr} | |
110: e24dd080 sub sp, sp, #128 ; 0x80 | |
114: e1a06001 mov r6, r1 | |
118: e1a08000 mov r8, r0 | |
11c: e3a0000c mov r0, #12 | |
120: e1a0100d mov r1, sp | |
124: e7cc1010 bfi r1, r0, #0, #13 | |
128: f57ff04f dsb sy | |
12c: e5910000 ldr r0, [r1] | |
130: e5907534 ldr r7, [r0, #1332] ; 0x534 | |
134: e3570000 cmp r7, #0 | |
138: 0a0000af beq 3fc <__seccomp_filter+0x2f0> | |
13c: e1a09002 mov r9, r2 | |
140: e3560000 cmp r6, #0 | |
144: 1a000026 bne 1e4 <__seccomp_filter+0xd8> | |
148: e3a0000c mov r0, #12 | |
14c: e1a0100d mov r1, sp | |
150: e7cc1010 bfi r1, r0, #0, #13 | |
154: e3a031a1 mov r3, #1073741864 ; 0x40000028 | |
158: e3016fb8 movw r6, #8120 ; 0x1fb8 | |
15c: e3014fbc movw r4, #8124 ; 0x1fbc | |
160: e5910000 ldr r0, [r1] | |
164: e3a05d7f mov r5, #8128 ; 0x1fc0 | |
168: e5901004 ldr r1, [r0, #4] | |
16c: e5912048 ldr r2, [r1, #72] ; 0x48 | |
170: e88d000c stm sp, {r2, r3} | |
174: e3012ff4 movw r2, #8180 ; 0x1ff4 | |
178: e3013fb4 movw r3, #8116 ; 0x1fb4 | |
17c: e791c002 ldr ip, [r1, r2] | |
180: e3012fc4 movw r2, #8132 ; 0x1fc4 | |
184: e7913003 ldr r3, [r1, r3] | |
188: e7916006 ldr r6, [r1, r6] | |
18c: e7914004 ldr r4, [r1, r4] | |
190: e7915005 ldr r5, [r1, r5] | |
194: e7911002 ldr r1, [r1, r2] | |
198: e3a02000 mov r2, #0 | |
19c: e58d1038 str r1, [sp, #56] ; 0x38 | |
1a0: e3011fec movw r1, #8172 ; 0x1fec | |
1a4: e58d203c str r2, [sp, #60] ; 0x3c | |
1a8: e58d2034 str r2, [sp, #52] ; 0x34 | |
1ac: e58d5030 str r5, [sp, #48] ; 0x30 | |
1b0: e58d202c str r2, [sp, #44] ; 0x2c | |
1b4: e58d4028 str r4, [sp, #40] ; 0x28 | |
1b8: e58d6020 str r6, [sp, #32] | |
1bc: e1a0600d mov r6, sp | |
1c0: e58d2024 str r2, [sp, #36] ; 0x24 | |
1c4: e58d201c str r2, [sp, #28] | |
1c8: e58d3018 str r3, [sp, #24] | |
1cc: e58d2014 str r2, [sp, #20] | |
1d0: e58dc010 str ip, [sp, #16] | |
1d4: e5900004 ldr r0, [r0, #4] | |
1d8: e7900001 ldr r0, [r0, r1] | |
1dc: e58d200c str r2, [sp, #12] | |
1e0: e58d0008 str r0, [sp, #8] | |
1e4: e3004000 movw r4, #0 | |
1e8: e3474fff movt r4, #32767 ; 0x7fff | |
1ec: e597000c ldr r0, [r7, #12] | |
1f0: e2801024 add r1, r0, #36 ; 0x24 | |
1f4: e5902020 ldr r2, [r0, #32] | |
1f8: e1a00006 mov r0, r6 | |
1fc: e12fff32 blx r2 | |
200: e1a01000 mov r1, r0 | |
204: e1a02004 mov r2, r4 | |
208: e7cf101f bfc r1, #0, #16 | |
20c: e7cf201f bfc r2, #0, #16 | |
210: e5977008 ldr r7, [r7, #8] | |
214: e1510002 cmp r1, r2 | |
218: b1a04000 movlt r4, r0 | |
21c: e3570000 cmp r7, #0 | |
220: 1afffff1 bne 1ec <__seccomp_filter+0xe0> | |
224: e30f0fff movw r0, #65535 ; 0xffff | |
228: e6ff6074 uxth r6, r4 | |
22c: e7cf401f bfc r4, #0, #16 | |
230: e3470fef movt r0, #32751 ; 0x7fef | |
234: e1540000 cmp r4, r0 | |
238: ca000011 bgt 284 <__seccomp_filter+0x178> | |
23c: e3540102 cmp r4, #-2147483648 ; 0x80000000 | |
240: 0a000072 beq 410 <__seccomp_filter+0x304> | |
244: e3540803 cmp r4, #196608 ; 0x30000 | |
248: 0a000030 beq 310 <__seccomp_filter+0x204> | |
24c: e3540805 cmp r4, #327680 ; 0x50000 | |
250: 1a000017 bne 2b4 <__seccomp_filter+0x1a8> | |
254: e3a0000c mov r0, #12 | |
258: e1a0100d mov r1, sp | |
25c: e7cc1010 bfi r1, r0, #0, #13 | |
260: e3012fb0 movw r2, #8112 ; 0x1fb0 | |
264: e5910000 ldr r0, [r1] | |
268: e3001fff movw r1, #4095 ; 0xfff | |
26c: e1560001 cmp r6, r1 | |
270: 31a01006 movcc r1, r6 | |
274: e5900004 ldr r0, [r0, #4] | |
278: e2611000 rsb r1, r1, #0 | |
27c: e7801002 str r1, [r0, r2] | |
280: ea000044 b 398 <__seccomp_filter+0x28c> | |
284: e3001000 movw r1, #0 | |
288: e3a00000 mov r0, #0 | |
28c: e3471ff0 movt r1, #32752 ; 0x7ff0 | |
290: e1540001 cmp r4, r1 | |
294: 0a000010 beq 2dc <__seccomp_filter+0x1d0> | |
298: e3001000 movw r1, #0 | |
29c: e3471ffc movt r1, #32764 ; 0x7ffc | |
2a0: e1540001 cmp r4, r1 | |
2a4: 13001000 movwne r1, #0 | |
2a8: 13471fff movtne r1, #32767 ; 0x7fff | |
2ac: 11540001 cmpne r4, r1 | |
2b0: 0a000039 beq 39c <__seccomp_filter+0x290> | |
2b4: e3a0000c mov r0, #12 | |
2b8: e1a0100d mov r1, sp | |
2bc: e7cc1010 bfi r1, r0, #0, #13 | |
2c0: e3a04000 mov r4, #0 | |
2c4: e5910000 ldr r0, [r1] | |
2c8: e59004ec ldr r0, [r0, #1260] ; 0x4ec | |
2cc: e5900008 ldr r0, [r0, #8] | |
2d0: e3500001 cmp r0, #1 | |
2d4: 0a00004e beq 414 <__seccomp_filter+0x308> | |
2d8: ea000070 b 4a0 <__seccomp_filter+0x394> | |
2dc: e3590000 cmp r9, #0 | |
2e0: 1a00002d bne 39c <__seccomp_filter+0x290> | |
2e4: e1a0400d mov r4, sp | |
2e8: e7cc401f bfc r4, #0, #13 | |
2ec: e594000c ldr r0, [r4, #12] | |
2f0: e5d01011 ldrb r1, [r0, #17] | |
2f4: e3110004 tst r1, #4 | |
2f8: 1a000029 bne 3a4 <__seccomp_filter+0x298> | |
2fc: e5900004 ldr r0, [r0, #4] | |
300: e3011fb0 movw r1, #8112 ; 0x1fb0 | |
304: e3e02025 mvn r2, #37 ; 0x25 | |
308: e7802001 str r2, [r0, r1] | |
30c: ea000021 b 398 <__seccomp_filter+0x28c> | |
310: e3a0400c mov r4, #12 | |
314: e1a0000d mov r0, sp | |
318: e7cc0014 bfi r0, r4, #0, #13 | |
31c: e3011ff4 movw r1, #8180 ; 0x1ff4 | |
320: e3012fb0 movw r2, #8112 ; 0x1fb0 | |
324: e1a0500d mov r5, sp | |
328: e5900000 ldr r0, [r0] | |
32c: e5900004 ldr r0, [r0, #4] | |
330: e7901001 ldr r1, [r0, r1] | |
334: e7801002 str r1, [r0, r2] | |
338: e1a00005 mov r0, r5 | |
33c: e3a01080 mov r1, #128 ; 0x80 | |
340: ebfffffe bl 0 <__memzero> | |
344: e3a00001 mov r0, #1 | |
348: e3011fec movw r1, #8172 ; 0x1fec | |
34c: e58d0008 str r0, [sp, #8] | |
350: e3a0001f mov r0, #31 | |
354: e58d0000 str r0, [sp] | |
358: e1a0000d mov r0, sp | |
35c: e7cc0014 bfi r0, r4, #0, #13 | |
360: e5900000 ldr r0, [r0] | |
364: e5900004 ldr r0, [r0, #4] | |
368: e7900001 ldr r0, [r0, r1] | |
36c: e3a011a1 mov r1, #1073741864 ; 0x40000028 | |
370: e58d1014 str r1, [sp, #20] | |
374: e58d6004 str r6, [sp, #4] | |
378: e1a01005 mov r1, r5 | |
37c: e58d000c str r0, [sp, #12] | |
380: e1a0000d mov r0, sp | |
384: e7cc0014 bfi r0, r4, #0, #13 | |
388: e58d8010 str r8, [sp, #16] | |
38c: e5902000 ldr r2, [r0] | |
390: e3a0001f mov r0, #31 | |
394: ebfffffe bl 0 <force_sig_info> | |
398: e3e00000 mvn r0, #0 | |
39c: e28dd080 add sp, sp, #128 ; 0x80 | |
3a0: e8bd8bf0 pop {r4, r5, r6, r7, r8, r9, fp, pc} | |
3a4: e5806574 str r6, [r0, #1396] ; 0x574 | |
3a8: e3000705 movw r0, #1797 ; 0x705 | |
3ac: ebfffffe bl 0 <ptrace_notify> | |
3b0: e594000c ldr r0, [r4, #12] | |
3b4: e5901004 ldr r1, [r0, #4] | |
3b8: e5912000 ldr r2, [r1] | |
3bc: e3120001 tst r2, #1 | |
3c0: 0a000003 beq 3d4 <__seccomp_filter+0x2c8> | |
3c4: e5d02515 ldrb r2, [r0, #1301] ; 0x515 | |
3c8: e3e00000 mvn r0, #0 | |
3cc: e3120001 tst r2, #1 | |
3d0: 1afffff1 bne 39c <__seccomp_filter+0x290> | |
3d4: e5910048 ldr r0, [r1, #72] ; 0x48 | |
3d8: e3500000 cmp r0, #0 | |
3dc: baffffed blt 398 <__seccomp_filter+0x28c> | |
3e0: e3a01000 mov r1, #0 | |
3e4: e3a02001 mov r2, #1 | |
3e8: ebffff47 bl 10c <__seccomp_filter> | |
3ec: e3500000 cmp r0, #0 | |
3f0: 13e00000 mvnne r0, #0 | |
3f4: e28dd080 add sp, sp, #128 ; 0x80 | |
3f8: e8bd8bf0 pop {r4, r5, r6, r7, r8, r9, fp, pc} | |
3fc: e3000000 movw r0, #0 | |
400: e3a010c6 mov r1, #198 ; 0xc6 | |
404: e3400000 movt r0, #0 | |
408: ebfffffe bl 0 <warn_slowpath_null> | |
40c: e3a06000 mov r6, #0 | |
410: e3a04001 mov r4, #1 | |
414: e3a0700c mov r7, #12 | |
418: e1a0000d mov r0, sp | |
41c: e7cc0017 bfi r0, r7, #0, #13 | |
420: e3011ff4 movw r1, #8180 ; 0x1ff4 | |
424: e3012fb0 movw r2, #8112 ; 0x1fb0 | |
428: e1a0500d mov r5, sp | |
42c: e5900000 ldr r0, [r0] | |
430: e5900004 ldr r0, [r0, #4] | |
434: e7901001 ldr r1, [r0, r1] | |
438: e7801002 str r1, [r0, r2] | |
43c: e1a00005 mov r0, r5 | |
440: e3a01080 mov r1, #128 ; 0x80 | |
444: ebfffffe bl 0 <__memzero> | |
448: e3a00001 mov r0, #1 | |
44c: e3011fec movw r1, #8172 ; 0x1fec | |
450: e58d0008 str r0, [sp, #8] | |
454: e3a0001f mov r0, #31 | |
458: e58d0000 str r0, [sp] | |
45c: e1a0000d mov r0, sp | |
460: e7cc0017 bfi r0, r7, #0, #13 | |
464: e5900000 ldr r0, [r0] | |
468: e5900004 ldr r0, [r0, #4] | |
46c: e7900001 ldr r0, [r0, r1] | |
470: e3a011a1 mov r1, #1073741864 ; 0x40000028 | |
474: e58d1014 str r1, [sp, #20] | |
478: e58d6004 str r6, [sp, #4] | |
47c: e58d000c str r0, [sp, #12] | |
480: e1a00005 mov r0, r5 | |
484: e58d8010 str r8, [sp, #16] | |
488: ebfffffe bl 0 <do_coredump> | |
48c: e3540000 cmp r4, #0 | |
490: 0a000002 beq 4a0 <__seccomp_filter+0x394> | |
494: e3a0001f mov r0, #31 | |
498: ebfffffe bl 0 <do_group_exit> | |
49c: eafffffe b 49c <__seccomp_filter+0x390> | |
4a0: e3a0001f mov r0, #31 | |
4a4: ebfffffe bl 0 <do_exit> | |
000004a8 <prctl_get_seccomp>: | |
4a8: e3a0000c mov r0, #12 | |
4ac: e1a0100d mov r1, sp | |
4b0: e7cc1010 bfi r1, r0, #0, #13 | |
4b4: e5910000 ldr r0, [r1] | |
4b8: e5900530 ldr r0, [r0, #1328] ; 0x530 | |
4bc: e12fff1e bx lr | |
000004c0 <SyS_seccomp>: | |
4c0: ea00000c b 4f8 <do_seccomp> | |
000004c4 <prctl_set_seccomp>: | |
4c4: e3500001 cmp r0, #1 | |
4c8: 0a000006 beq 4e8 <prctl_set_seccomp+0x24> | |
4cc: e3500002 cmp r0, #2 | |
4d0: 13e00015 mvnne r0, #21 | |
4d4: 112fff1e bxne lr | |
4d8: e1a02001 mov r2, r1 | |
4dc: e3a00001 mov r0, #1 | |
4e0: e3a01000 mov r1, #0 | |
4e4: ea000003 b 4f8 <do_seccomp> | |
4e8: e3a00000 mov r0, #0 | |
4ec: e3a02000 mov r2, #0 | |
4f0: e3a01000 mov r1, #0 | |
4f4: eaffffff b 4f8 <do_seccomp> | |
000004f8 <do_seccomp>: | |
4f8: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} | |
4fc: e24dd014 sub sp, sp, #20 | |
500: e1a04001 mov r4, r1 | |
504: e3e06015 mvn r6, #21 | |
508: e3500002 cmp r0, #2 | |
50c: 0a000034 beq 5e4 <do_seccomp+0xec> | |
510: e3500001 cmp r0, #1 | |
514: 0a000052 beq 664 <do_seccomp+0x16c> | |
518: e3500000 cmp r0, #0 | |
51c: 1a00009d bne 798 <do_seccomp+0x2a0> | |
520: e3540000 cmp r4, #0 | |
524: 03520000 cmpeq r2, #0 | |
528: 1a00009a bne 798 <do_seccomp+0x2a0> | |
52c: e1a0500d mov r5, sp | |
530: e3001504 movw r1, #1284 ; 0x504 | |
534: e7cc501f bfc r5, #0, #13 | |
538: e595000c ldr r0, [r5, #12] | |
53c: e59004f0 ldr r0, [r0, #1264] ; 0x4f0 | |
540: e0800001 add r0, r0, r1 | |
544: ebfffffe bl 0 <_raw_spin_lock_irq> | |
548: e3a0000c mov r0, #12 | |
54c: e1a0100d mov r1, sp | |
550: e7cc1010 bfi r1, r0, #0, #13 | |
554: e5910000 ldr r0, [r1] | |
558: e59014f0 ldr r1, [r0, #1264] ; 0x4f0 | |
55c: e5911504 ldr r1, [r1, #1284] ; 0x504 | |
560: e6ff2071 uxth r2, r1 | |
564: e1520821 cmp r2, r1, lsr #16 | |
568: 0a0001a2 beq bf8 <do_seccomp+0x700> | |
56c: e5900530 ldr r0, [r0, #1328] ; 0x530 | |
570: e3e06015 mvn r6, #21 | |
574: e3500001 cmp r0, #1 | |
578: 8a00000e bhi 5b8 <do_seccomp+0xc0> | |
57c: e595400c ldr r4, [r5, #12] | |
580: e59404f0 ldr r0, [r4, #1264] ; 0x4f0 | |
584: e5900504 ldr r0, [r0, #1284] ; 0x504 | |
588: e6ff1070 uxth r1, r0 | |
58c: e1510820 cmp r1, r0, lsr #16 | |
590: 0a00019a beq c00 <do_seccomp+0x708> | |
594: e3a00001 mov r0, #1 | |
598: e5840530 str r0, [r4, #1328] ; 0x530 | |
59c: e1a00004 mov r0, r4 | |
5a0: f57ff05b dmb ish | |
5a4: ebfffffe bl 0 <arch_seccomp_spec_mitigate> | |
5a8: e5941004 ldr r1, [r4, #4] | |
5ac: e3a00007 mov r0, #7 | |
5b0: ebfffffe bl 0 <_set_bit> | |
5b4: e3a06000 mov r6, #0 | |
5b8: e595000c ldr r0, [r5, #12] | |
5bc: e3001504 movw r1, #1284 ; 0x504 | |
5c0: e59004f0 ldr r0, [r0, #1264] ; 0x4f0 | |
5c4: f57ff05b dmb ish | |
5c8: e1b010b1 ldrh r1, [r0, r1]! ; <UNPREDICTABLE> | |
5cc: e2811001 add r1, r1, #1 | |
5d0: e1c010b0 strh r1, [r0] | |
5d4: f57ff04a dsb ishst | |
5d8: e320f004 sev | |
5dc: f1080080 cpsie i | |
5e0: ea00006c b 798 <do_seccomp+0x2a0> | |
5e4: e3540000 cmp r4, #0 | |
5e8: 1a00006a bne 798 <do_seccomp+0x2a0> | |
5ec: e3a00008 mov r0, #8 | |
5f0: e1a0100d mov r1, sp | |
5f4: e7cc1010 bfi r1, r0, #0, #13 | |
5f8: e5910000 ldr r0, [r1] | |
5fc: e2921004 adds r1, r2, #4 | |
600: 30d11000 sbcscc r1, r1, r0 | |
604: 33a00000 movcc r0, #0 | |
608: e3500000 cmp r0, #0 | |
60c: 1a000170 bne bd4 <do_seccomp+0x6dc> | |
610: e28d0010 add r0, sp, #16 | |
614: e1a01002 mov r1, r2 | |
618: e3a02004 mov r2, #4 | |
61c: ebfffffe bl 0 <arm_copy_from_user> | |
620: e3500000 cmp r0, #0 | |
624: 1a00016c bne bdc <do_seccomp+0x6e4> | |
628: e59d0010 ldr r0, [sp, #16] | |
62c: e3e0605e mvn r6, #94 ; 0x5e | |
630: e3500805 cmp r0, #327680 ; 0x50000 | |
634: ba000048 blt 75c <do_seccomp+0x264> | |
638: e30f1fff movw r1, #65535 ; 0xffff | |
63c: e3471ffb movt r1, #32763 ; 0x7ffb | |
640: e1500001 cmp r0, r1 | |
644: ca00004a bgt 774 <do_seccomp+0x27c> | |
648: e3500805 cmp r0, #327680 ; 0x50000 | |
64c: 0a000050 beq 794 <do_seccomp+0x29c> | |
650: e3001000 movw r1, #0 | |
654: e3471ff0 movt r1, #32752 ; 0x7ff0 | |
658: e1500001 cmp r0, r1 | |
65c: 0a00004c beq 794 <do_seccomp+0x29c> | |
660: ea00004c b 798 <do_seccomp+0x2a0> | |
664: e3540007 cmp r4, #7 | |
668: 8a00004a bhi 798 <do_seccomp+0x2a0> | |
66c: e3a01008 mov r1, #8 | |
670: e1a0000d mov r0, sp | |
674: e7cc0011 bfi r0, r1, #0, #13 | |
678: e5900000 ldr r0, [r0] | |
67c: e2923008 adds r3, r2, #8 | |
680: 30d33000 sbcscc r3, r3, r0 | |
684: 33a00000 movcc r0, #0 | |
688: e3500000 cmp r0, #0 | |
68c: 1a00014d bne bc8 <do_seccomp+0x6d0> | |
690: e28d0008 add r0, sp, #8 | |
694: e1a01002 mov r1, r2 | |
698: e3a02008 mov r2, #8 | |
69c: ebfffffe bl 0 <arm_copy_from_user> | |
6a0: e3500000 cmp r0, #0 | |
6a4: 1a000146 bne bc4 <do_seccomp+0x6cc> | |
6a8: e1dd00b8 ldrh r0, [sp, #8] | |
6ac: e3e06015 mvn r6, #21 | |
6b0: e3a01000 mov r1, #0 | |
6b4: e2400001 sub r0, r0, #1 | |
6b8: e6ff0070 uxth r0, r0 | |
6bc: e1510620 cmp r1, r0, lsr #12 | |
6c0: 1a000034 bne 798 <do_seccomp+0x2a0> | |
6c4: e3a0000c mov r0, #12 | |
6c8: e1a0100d mov r1, sp | |
6cc: e7cc1010 bfi r1, r0, #0, #13 | |
6d0: e5910000 ldr r0, [r1] | |
6d4: e590138c ldr r1, [r0, #908] ; 0x38c | |
6d8: e3110001 tst r1, #1 | |
6dc: 1a000007 bne 700 <do_seccomp+0x208> | |
6e0: e59004b8 ldr r0, [r0, #1208] ; 0x4b8 | |
6e4: e3a02015 mov r2, #21 | |
6e8: e3a03000 mov r3, #0 | |
6ec: e5901068 ldr r1, [r0, #104] ; 0x68 | |
6f0: ebfffffe bl 0 <cap_capable> | |
6f4: e3e0600c mvn r6, #12 | |
6f8: e3500000 cmp r0, #0 | |
6fc: 1a000025 bne 798 <do_seccomp+0x2a0> | |
700: e3000000 movw r0, #0 | |
704: e30812c0 movw r1, #33472 ; 0x82c0 | |
708: e3400000 movt r0, #0 | |
70c: e3401140 movt r1, #320 ; 0x140 | |
710: e5900018 ldr r0, [r0, #24] | |
714: ebfffffe bl 0 <kmem_cache_alloc> | |
718: e3500000 cmp r0, #0 | |
71c: 0a000020 beq 7a4 <do_seccomp+0x2ac> | |
720: e3002000 movw r2, #0 | |
724: e1a06000 mov r6, r0 | |
728: e280000c add r0, r0, #12 | |
72c: e28d1008 add r1, sp, #8 | |
730: e3402000 movt r2, #0 | |
734: e3a03000 mov r3, #0 | |
738: ebfffffe bl 0 <bpf_prog_create_from_user> | |
73c: e3700001 cmn r0, #1 | |
740: da000019 ble 7ac <do_seccomp+0x2b4> | |
744: e3a00001 mov r0, #1 | |
748: e1a05006 mov r5, r6 | |
74c: e5860000 str r0, [r6] | |
750: e3750a01 cmn r5, #4096 ; 0x1000 | |
754: 8a000019 bhi 7c0 <do_seccomp+0x2c8> | |
758: ea00001a b 7c8 <do_seccomp+0x2d0> | |
75c: e3500102 cmp r0, #-2147483648 ; 0x80000000 | |
760: 13500000 cmpne r0, #0 | |
764: 0a00000a beq 794 <do_seccomp+0x29c> | |
768: e3500803 cmp r0, #196608 ; 0x30000 | |
76c: 03a06000 moveq r6, #0 | |
770: ea000008 b 798 <do_seccomp+0x2a0> | |
774: e3001000 movw r1, #0 | |
778: e3471fff movt r1, #32767 ; 0x7fff | |
77c: e1500001 cmp r0, r1 | |
780: 0a000003 beq 794 <do_seccomp+0x29c> | |
784: e3001000 movw r1, #0 | |
788: e3471ffc movt r1, #32764 ; 0x7ffc | |
78c: e1500001 cmp r0, r1 | |
790: 1a000000 bne 798 <do_seccomp+0x2a0> | |
794: e3a06000 mov r6, #0 | |
798: e1a00006 mov r0, r6 | |
79c: e28dd014 add sp, sp, #20 | |
7a0: e8bd8ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} | |
7a4: e3e0600b mvn r6, #11 | |
7a8: eafffffa b 798 <do_seccomp+0x2a0> | |
7ac: e1a05000 mov r5, r0 | |
7b0: e1a00006 mov r0, r6 | |
7b4: ebfffffe bl 0 <kfree> | |
7b8: e3750a01 cmn r5, #4096 ; 0x1000 | |
7bc: 9a000001 bls 7c8 <do_seccomp+0x2d0> | |
7c0: e1a06005 mov r6, r5 | |
7c4: eafffff3 b 798 <do_seccomp+0x2a0> | |
7c8: e2148001 ands r8, r4, #1 | |
7cc: 0a00000c beq 804 <do_seccomp+0x30c> | |
7d0: e3a0000c mov r0, #12 | |
7d4: e1a0100d mov r1, sp | |
7d8: e7cc1010 bfi r1, r0, #0, #13 | |
7dc: e5910000 ldr r0, [r1] | |
7e0: e59004ec ldr r0, [r0, #1260] ; 0x4ec | |
7e4: e2800fa6 add r0, r0, #664 ; 0x298 | |
7e8: ebfffffe bl 0 <mutex_lock_killable> | |
7ec: e3500000 cmp r0, #0 | |
7f0: 0a000003 beq 804 <do_seccomp+0x30c> | |
7f4: e3e06015 mvn r6, #21 | |
7f8: e3550000 cmp r5, #0 | |
7fc: 1a0000eb bne bb0 <do_seccomp+0x6b8> | |
800: eaffffe4 b 798 <do_seccomp+0x2a0> | |
804: e1a0900d mov r9, sp | |
808: e3001504 movw r1, #1284 ; 0x504 | |
80c: e7cc901f bfc r9, #0, #13 | |
810: e599000c ldr r0, [r9, #12] | |
814: e59004f0 ldr r0, [r0, #1264] ; 0x4f0 | |
818: e0800001 add r0, r0, r1 | |
81c: ebfffffe bl 0 <_raw_spin_lock_irq> | |
820: e3a0000c mov r0, #12 | |
824: e1a0100d mov r1, sp | |
828: e7cc1010 bfi r1, r0, #0, #13 | |
82c: e5910000 ldr r0, [r1] | |
830: e59014f0 ldr r1, [r0, #1264] ; 0x4f0 | |
834: e5911504 ldr r1, [r1, #1284] ; 0x504 | |
838: e6ff2071 uxth r2, r1 | |
83c: e1520821 cmp r2, r1, lsr #16 | |
840: 0a0000f0 beq c08 <do_seccomp+0x710> | |
844: e5900530 ldr r0, [r0, #1328] ; 0x530 | |
848: e3800002 orr r0, r0, #2 | |
84c: e3500002 cmp r0, #2 | |
850: 1a000018 bne 8b8 <do_seccomp+0x3c0> | |
854: e1a0100d mov r1, sp | |
858: e7cc101f bfc r1, #0, #13 | |
85c: e591200c ldr r2, [r1, #12] | |
860: e59204f0 ldr r0, [r2, #1264] ; 0x4f0 | |
864: e5900504 ldr r0, [r0, #1284] ; 0x504 | |
868: e6ff3070 uxth r3, r0 | |
86c: e1530820 cmp r3, r0, lsr #16 | |
870: 0a0000e6 beq c10 <do_seccomp+0x718> | |
874: e595000c ldr r0, [r5, #12] | |
878: e5b23534 ldr r3, [r2, #1332]! ; 0x534 | |
87c: e5900008 ldr r0, [r0, #8] | |
880: e3530000 cmp r3, #0 | |
884: 0a000007 beq 8a8 <do_seccomp+0x3b0> | |
888: e5937008 ldr r7, [r3, #8] | |
88c: e593300c ldr r3, [r3, #12] | |
890: e3570000 cmp r7, #0 | |
894: e5933008 ldr r3, [r3, #8] | |
898: e0800003 add r0, r0, r3 | |
89c: e1a03007 mov r3, r7 | |
8a0: e2800004 add r0, r0, #4 | |
8a4: 1afffff7 bne 888 <do_seccomp+0x390> | |
8a8: e3500902 cmp r0, #32768 ; 0x8000 | |
8ac: 9a000003 bls 8c0 <do_seccomp+0x3c8> | |
8b0: e3e0600b mvn r6, #11 | |
8b4: ea0000ab b b68 <do_seccomp+0x670> | |
8b8: e3e06015 mvn r6, #21 | |
8bc: ea0000a9 b b68 <do_seccomp+0x670> | |
8c0: e3580000 cmp r8, #0 | |
8c4: 0a000029 beq 970 <do_seccomp+0x478> | |
8c8: e3a0000c mov r0, #12 | |
8cc: e1a0300d mov r3, sp | |
8d0: e7cc3010 bfi r3, r0, #0, #13 | |
8d4: e593e000 ldr lr, [r3] | |
8d8: e59ea4ec ldr sl, [lr, #1260] ; 0x4ec | |
8dc: e59a0298 ldr r0, [sl, #664] ; 0x298 | |
8e0: e3500007 cmp r0, #7 | |
8e4: 9a0000cf bls c28 <do_seccomp+0x730> | |
8e8: e59e04f0 ldr r0, [lr, #1264] ; 0x4f0 | |
8ec: e5900504 ldr r0, [r0, #1284] ; 0x504 | |
8f0: e6ff3070 uxth r3, r0 | |
8f4: e1530820 cmp r3, r0, lsr #16 | |
8f8: 0a0000cc beq c30 <do_seccomp+0x738> | |
8fc: e5ba600c ldr r6, [sl, #12]! | |
900: e15a0006 cmp sl, r6 | |
904: 0a000019 beq 970 <do_seccomp+0x478> | |
908: e30fcbe8 movw ip, #64488 ; 0xfbe8 | |
90c: e34fcfff movt ip, #65535 ; 0xffff | |
910: ea00000e b 950 <do_seccomp+0x458> | |
914: e3530002 cmp r3, #2 | |
918: 1a00008c bne b50 <do_seccomp+0x658> | |
91c: e596311c ldr r3, [r6, #284] ; 0x11c | |
920: e3530000 cmp r3, #0 | |
924: 0a00000e beq 964 <do_seccomp+0x46c> | |
928: e59e7534 ldr r7, [lr, #1332] ; 0x534 | |
92c: e3570000 cmp r7, #0 | |
930: 1a000003 bne 944 <do_seccomp+0x44c> | |
934: ea000085 b b50 <do_seccomp+0x658> | |
938: e5977008 ldr r7, [r7, #8] | |
93c: e3570000 cmp r7, #0 | |
940: 0a000082 beq b50 <do_seccomp+0x658> | |
944: e1570003 cmp r7, r3 | |
948: 1afffffa bne 938 <do_seccomp+0x440> | |
94c: ea000004 b 964 <do_seccomp+0x46c> | |
950: e086000c add r0, r6, ip | |
954: e15e0000 cmp lr, r0 | |
958: 15963118 ldrne r3, [r6, #280] ; 0x118 | |
95c: 13530000 cmpne r3, #0 | |
960: 1affffeb bne 914 <do_seccomp+0x41c> | |
964: e5966000 ldr r6, [r6] | |
968: e15a0006 cmp sl, r6 | |
96c: 1afffff7 bne 950 <do_seccomp+0x458> | |
970: e3140002 tst r4, #2 | |
974: 0a000004 beq 98c <do_seccomp+0x494> | |
978: e3a00001 mov r0, #1 | |
97c: e3002534 movw r2, #1332 ; 0x534 | |
980: e5c50004 strb r0, [r5, #4] | |
984: e591000c ldr r0, [r1, #12] | |
988: e0802002 add r2, r0, r2 | |
98c: e5920000 ldr r0, [r2] | |
990: e3580000 cmp r8, #0 | |
994: e5850008 str r0, [r5, #8] | |
998: e591000c ldr r0, [r1, #12] | |
99c: e58d8000 str r8, [sp] | |
9a0: e5805534 str r5, [r0, #1332] ; 0x534 | |
9a4: 0a000055 beq b00 <do_seccomp+0x608> | |
9a8: e3a0000c mov r0, #12 | |
9ac: e1a0100d mov r1, sp | |
9b0: e7cc1010 bfi r1, r0, #0, #13 | |
9b4: e5917000 ldr r7, [r1] | |
9b8: e59704ec ldr r0, [r7, #1260] ; 0x4ec | |
9bc: e5901298 ldr r1, [r0, #664] ; 0x298 | |
9c0: e3510007 cmp r1, #7 | |
9c4: 9a00009b bls c38 <do_seccomp+0x740> | |
9c8: e59714f0 ldr r1, [r7, #1264] ; 0x4f0 | |
9cc: e5911504 ldr r1, [r1, #1284] ; 0x504 | |
9d0: e6ff2071 uxth r2, r1 | |
9d4: e1520821 cmp r2, r1, lsr #16 | |
9d8: 0a000098 beq c40 <do_seccomp+0x748> | |
9dc: e5b0500c ldr r5, [r0, #12]! | |
9e0: e1500005 cmp r0, r5 | |
9e4: 0a000045 beq b00 <do_seccomp+0x608> | |
9e8: e30fbbe8 movw fp, #64488 ; 0xfbe8 | |
9ec: e2040004 and r0, r4, #4 | |
9f0: e34fbfff movt fp, #65535 ; 0xffff | |
9f4: e58d0004 str r0, [sp, #4] | |
9f8: e085a00b add sl, r5, fp | |
9fc: e157000a cmp r7, sl | |
a00: 0a000039 beq aec <do_seccomp+0x5f4> | |
a04: e5970534 ldr r0, [r7, #1332] ; 0x534 | |
a08: e3500000 cmp r0, #0 | |
a0c: 0a000005 beq a28 <do_seccomp+0x530> | |
a10: f590f000 pldw [r0] | |
a14: e1901f9f ldrex r1, [r0] | |
a18: e2811001 add r1, r1, #1 | |
a1c: e1802f91 strex r2, r1, [r0] | |
a20: e3320000 teq r2, #0 | |
a24: 1afffffa bne a14 <do_seccomp+0x51c> | |
a28: e595611c ldr r6, [r5, #284] ; 0x11c | |
a2c: e3560000 cmp r6, #0 | |
a30: 0a000011 beq a7c <do_seccomp+0x584> | |
a34: f57ff05b dmb ish | |
a38: f596f000 pldw [r6] | |
a3c: e1960f9f ldrex r0, [r6] | |
a40: e2400001 sub r0, r0, #1 | |
a44: e1861f90 strex r1, r0, [r6] | |
a48: e3310000 teq r1, #0 | |
a4c: 1afffffa bne a3c <do_seccomp+0x544> | |
a50: e3500000 cmp r0, #0 | |
a54: f57ff05b dmb ish | |
a58: 1a000007 bne a7c <do_seccomp+0x584> | |
a5c: e596000c ldr r0, [r6, #12] | |
a60: e5968008 ldr r8, [r6, #8] | |
a64: ebfffffe bl 0 <bpf_prog_destroy> | |
a68: e1a00006 mov r0, r6 | |
a6c: ebfffffe bl 0 <kfree> | |
a70: e3580000 cmp r8, #0 | |
a74: e1a06008 mov r6, r8 | |
a78: 1affffed bne a34 <do_seccomp+0x53c> | |
a7c: f57ff05b dmb ish | |
a80: e5970534 ldr r0, [r7, #1332] ; 0x534 | |
a84: e585011c str r0, [r5, #284] ; 0x11c | |
a88: e597038c ldr r0, [r7, #908] ; 0x38c | |
a8c: e3100001 tst r0, #1 | |
a90: 0a000002 beq aa0 <do_seccomp+0x5a8> | |
a94: e245108c sub r1, r5, #140 ; 0x8c | |
a98: e3a00000 mov r0, #0 | |
a9c: ebfffffe bl 0 <_set_bit> | |
aa0: e5950118 ldr r0, [r5, #280] ; 0x118 | |
aa4: e3500000 cmp r0, #0 | |
aa8: 1a00000f bne aec <do_seccomp+0x5f4> | |
aac: e59500d8 ldr r0, [r5, #216] ; 0xd8 | |
ab0: e5900504 ldr r0, [r0, #1284] ; 0x504 | |
ab4: e6ff1070 uxth r1, r0 | |
ab8: e1510820 cmp r1, r0, lsr #16 | |
abc: 0a000055 beq c18 <do_seccomp+0x720> | |
ac0: e3a00002 mov r0, #2 | |
ac4: e5850118 str r0, [r5, #280] ; 0x118 | |
ac8: f57ff05b dmb ish | |
acc: e59d0004 ldr r0, [sp, #4] | |
ad0: e3500000 cmp r0, #0 | |
ad4: 1a000001 bne ae0 <do_seccomp+0x5e8> | |
ad8: e1a0000a mov r0, sl | |
adc: ebfffffe bl 0 <arch_seccomp_spec_mitigate> | |
ae0: e59a1004 ldr r1, [sl, #4] | |
ae4: e3a00007 mov r0, #7 | |
ae8: ebfffffe bl 0 <_set_bit> | |
aec: e5955000 ldr r5, [r5] | |
af0: e59704ec ldr r0, [r7, #1260] ; 0x4ec | |
af4: e280000c add r0, r0, #12 | |
af8: e1500005 cmp r0, r5 | |
afc: 1affffbd bne 9f8 <do_seccomp+0x500> | |
b00: e599500c ldr r5, [r9, #12] | |
b04: e59504f0 ldr r0, [r5, #1264] ; 0x4f0 | |
b08: e5900504 ldr r0, [r0, #1284] ; 0x504 | |
b0c: e6ff1070 uxth r1, r0 | |
b10: e1510820 cmp r1, r0, lsr #16 | |
b14: 0a000041 beq c20 <do_seccomp+0x728> | |
b18: e3a00002 mov r0, #2 | |
b1c: e3140004 tst r4, #4 | |
b20: e5850530 str r0, [r5, #1328] ; 0x530 | |
b24: f57ff05b dmb ish | |
b28: 1a000001 bne b34 <do_seccomp+0x63c> | |
b2c: e1a00005 mov r0, r5 | |
b30: ebfffffe bl 0 <arch_seccomp_spec_mitigate> | |
b34: e5951004 ldr r1, [r5, #4] | |
b38: e3a00007 mov r0, #7 | |
b3c: ebfffffe bl 0 <_set_bit> | |
b40: e59d8000 ldr r8, [sp] | |
b44: e3a05000 mov r5, #0 | |
b48: e3a06000 mov r6, #0 | |
b4c: ea000005 b b68 <do_seccomp+0x670> | |
b50: e3a01000 mov r1, #0 | |
b54: e3a02000 mov r2, #0 | |
b58: ebfffffe bl 0 <__task_pid_nr_ns> | |
b5c: e3500000 cmp r0, #0 | |
b60: 0a000038 beq c48 <do_seccomp+0x750> | |
b64: e1a06000 mov r6, r0 | |
b68: e599000c ldr r0, [r9, #12] | |
b6c: e3001504 movw r1, #1284 ; 0x504 | |
b70: e59004f0 ldr r0, [r0, #1264] ; 0x4f0 | |
b74: f57ff05b dmb ish | |
b78: e1b010b1 ldrh r1, [r0, r1]! ; <UNPREDICTABLE> | |
b7c: e2811001 add r1, r1, #1 | |
b80: e1c010b0 strh r1, [r0] | |
b84: f57ff04a dsb ishst | |
b88: e320f004 sev | |
b8c: f1080080 cpsie i | |
b90: e3580000 cmp r8, #0 | |
b94: 0a000003 beq ba8 <do_seccomp+0x6b0> | |
b98: e599000c ldr r0, [r9, #12] | |
b9c: e59004ec ldr r0, [r0, #1260] ; 0x4ec | |
ba0: e2800fa6 add r0, r0, #664 ; 0x298 | |
ba4: ebfffffe bl 0 <mutex_unlock> | |
ba8: e3550000 cmp r5, #0 | |
bac: 0afffef9 beq 798 <do_seccomp+0x2a0> | |
bb0: e595000c ldr r0, [r5, #12] | |
bb4: ebfffffe bl 0 <bpf_prog_destroy> | |
bb8: e1a00005 mov r0, r5 | |
bbc: ebfffffe bl 0 <kfree> | |
bc0: eafffef4 b 798 <do_seccomp+0x2a0> | |
bc4: e1a01000 mov r1, r0 | |
bc8: e2610008 rsb r0, r1, #8 | |
bcc: e28d2008 add r2, sp, #8 | |
bd0: ea000004 b be8 <do_seccomp+0x6f0> | |
bd4: e3a01004 mov r1, #4 | |
bd8: ea000000 b be0 <do_seccomp+0x6e8> | |
bdc: e1a01000 mov r1, r0 | |
be0: e2610004 rsb r0, r1, #4 | |
be4: e28d2010 add r2, sp, #16 | |
be8: e0820000 add r0, r2, r0 | |
bec: ebfffffe bl 0 <__memzero> | |
bf0: e3e0600d mvn r6, #13 | |
bf4: eafffee7 b 798 <do_seccomp+0x2a0> | |
bf8: e7f001f2 udf #18 | |
bfc: eafffffe b bfc <do_seccomp+0x704> | |
c00: e7f001f2 udf #18 | |
c04: eafffffe b c04 <do_seccomp+0x70c> | |
c08: e7f001f2 udf #18 | |
c0c: eafffffe b c0c <do_seccomp+0x714> | |
c10: e7f001f2 udf #18 | |
c14: eafffffe b c14 <do_seccomp+0x71c> | |
c18: e7f001f2 udf #18 | |
c1c: eafffffe b c1c <do_seccomp+0x724> | |
c20: e7f001f2 udf #18 | |
c24: eafffffe b c24 <do_seccomp+0x72c> | |
c28: e7f001f2 udf #18 | |
c2c: eafffffe b c2c <do_seccomp+0x734> | |
c30: e7f001f2 udf #18 | |
c34: eafffffe b c34 <do_seccomp+0x73c> | |
c38: e7f001f2 udf #18 | |
c3c: eafffffe b c3c <do_seccomp+0x744> | |
c40: e7f001f2 udf #18 | |
c44: eafffffe b c44 <do_seccomp+0x74c> | |
c48: e3000000 movw r0, #0 | |
c4c: e3a01f4b mov r1, #300 ; 0x12c | |
c50: e3400000 movt r0, #0 | |
c54: ebfffffe bl 0 <warn_slowpath_null> | |
c58: e3e06002 mvn r6, #2 | |
c5c: eaffffc1 b b68 <do_seccomp+0x670> | |
00000c60 <seccomp_check_filter>: | |
c60: e92d47f0 push {r4, r5, r6, r7, r8, r9, sl, lr} | |
c64: e3510000 cmp r1, #0 | |
c68: 0a0000c9 beq f94 <seccomp_check_filter+0x334> | |
c6c: e2803004 add r3, r0, #4 | |
c70: e3a0c000 mov ip, #0 | |
c74: e3a0e021 mov lr, #33 ; 0x21 | |
c78: e3e0803c mvn r8, #60 ; 0x3c | |
c7c: e3a0a040 mov sl, #64 ; 0x40 | |
c80: e3a09001 mov r9, #1 | |
c84: e3a07000 mov r7, #0 | |
c88: e3e02015 mvn r2, #21 | |
c8c: ea000009 b cb8 <seccomp_check_filter+0x58> | |
c90: e7934104 ldr r4, [r3, r4, lsl #2] | |
c94: e1c0e0b0 strh lr, [r0] | |
c98: e1140008 tst r4, r8 | |
c9c: 0a0000b8 beq f84 <seccomp_check_filter+0x324> | |
ca0: ea0000bc b f98 <seccomp_check_filter+0x338> | |
ca4: e1c0c0b0 strh ip, [r0] | |
ca8: ea000000 b cb0 <seccomp_check_filter+0x50> | |
cac: e1c090b0 strh r9, [r0] | |
cb0: e783a104 str sl, [r3, r4, lsl #2] | |
cb4: ea0000b2 b f84 <seccomp_check_filter+0x324> | |
cb8: e1d060b0 ldrh r6, [r0] | |
cbc: e35600ac cmp r6, #172 ; 0xac | |
cc0: 8a0000b4 bhi f98 <seccomp_check_filter+0x338> | |
cc4: e28f5004 add r5, pc, #4 | |
cc8: e1a04087 lsl r4, r7, #1 | |
ccc: e795f106 ldr pc, [r5, r6, lsl #2] | |
cd0: 00000f84 andeq r0, r0, r4, lsl #31 | |
cd4: 00000f84 andeq r0, r0, r4, lsl #31 | |
cd8: 00000f84 andeq r0, r0, r4, lsl #31 | |
cdc: 00000f84 andeq r0, r0, r4, lsl #31 | |
ce0: 00000f84 andeq r0, r0, r4, lsl #31 | |
ce4: 00000f84 andeq r0, r0, r4, lsl #31 | |
ce8: 00000f84 andeq r0, r0, r4, lsl #31 | |
cec: 00000f84 andeq r0, r0, r4, lsl #31 | |
cf0: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
cf4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
cf8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
cfc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d00: 00000f84 andeq r0, r0, r4, lsl #31 | |
d04: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d08: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d0c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d10: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d14: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d18: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d1c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d20: 00000f84 andeq r0, r0, r4, lsl #31 | |
d24: 00000f84 andeq r0, r0, r4, lsl #31 | |
d28: 00000f84 andeq r0, r0, r4, lsl #31 | |
d2c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d30: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d34: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d38: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d3c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d40: 00000f84 andeq r0, r0, r4, lsl #31 | |
d44: 00000f84 andeq r0, r0, r4, lsl #31 | |
d48: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d4c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d50: 00000c90 muleq r0, r0, ip | |
d54: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d58: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d5c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d60: 00000f84 andeq r0, r0, r4, lsl #31 | |
d64: 00000f84 andeq r0, r0, r4, lsl #31 | |
d68: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d6c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d70: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d74: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d78: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d7c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d80: 00000f84 andeq r0, r0, r4, lsl #31 | |
d84: 00000f84 andeq r0, r0, r4, lsl #31 | |
d88: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d8c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d90: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d94: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d98: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
d9c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
da0: 00000f84 andeq r0, r0, r4, lsl #31 | |
da4: 00000f84 andeq r0, r0, r4, lsl #31 | |
da8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dac: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
db0: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
db4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
db8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dbc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dc0: 00000f84 andeq r0, r0, r4, lsl #31 | |
dc4: 00000f84 andeq r0, r0, r4, lsl #31 | |
dc8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dcc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dd0: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dd4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dd8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ddc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
de0: 00000f84 andeq r0, r0, r4, lsl #31 | |
de4: 00000f84 andeq r0, r0, r4, lsl #31 | |
de8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dec: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
df0: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
df4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
df8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
dfc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e00: 00000f84 andeq r0, r0, r4, lsl #31 | |
e04: 00000f84 andeq r0, r0, r4, lsl #31 | |
e08: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e0c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e10: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e14: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e18: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e1c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e20: 00000f84 andeq r0, r0, r4, lsl #31 | |
e24: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e28: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e2c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e30: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e34: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e38: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e3c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e40: 00000f84 andeq r0, r0, r4, lsl #31 | |
e44: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e48: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e4c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e50: 00000f84 andeq r0, r0, r4, lsl #31 | |
e54: 00000f84 andeq r0, r0, r4, lsl #31 | |
e58: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e5c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e60: 00000f84 andeq r0, r0, r4, lsl #31 | |
e64: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e68: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e6c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e70: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e74: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e78: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e7c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e80: 00000f84 andeq r0, r0, r4, lsl #31 | |
e84: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e88: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e8c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e90: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e94: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e98: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
e9c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ea0: 00000f84 andeq r0, r0, r4, lsl #31 | |
ea4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ea8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
eac: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
eb0: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
eb4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
eb8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ebc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ec0: 00000f84 andeq r0, r0, r4, lsl #31 | |
ec4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ec8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ecc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ed0: 00000ca4 andeq r0, r0, r4, lsr #25 | |
ed4: 00000cac andeq r0, r0, ip, lsr #25 | |
ed8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
edc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ee0: 00000f84 andeq r0, r0, r4, lsl #31 | |
ee4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ee8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
eec: 00000f84 andeq r0, r0, r4, lsl #31 | |
ef0: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ef4: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
ef8: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
efc: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f00: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f04: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f08: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f0c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f10: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f14: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f18: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f1c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f20: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f24: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f28: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f2c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f30: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f34: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f38: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f3c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f40: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f44: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f48: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f4c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f50: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f54: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f58: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f5c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f60: 00000f84 andeq r0, r0, r4, lsl #31 | |
f64: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f68: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f6c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f70: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f74: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f78: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f7c: 00000f98 muleq r0, r8, pc ; <UNPREDICTABLE> | |
f80: 00000f84 andeq r0, r0, r4, lsl #31 | |
f84: e2877001 add r7, r7, #1 | |
f88: e2800008 add r0, r0, #8 | |
f8c: e1570001 cmp r7, r1 | |
f90: 3affff48 bcc cb8 <seccomp_check_filter+0x58> | |
f94: e3a02000 mov r2, #0 | |
f98: e1a00002 mov r0, r2 | |
f9c: e8bd87f0 pop {r4, r5, r6, r7, r8, r9, sl, pc} | |
00000fa0 <seccomp_actions_logged_handler>: | |
fa0: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} | |
fa4: e24dd064 sub sp, sp, #100 ; 0x64 | |
fa8: e1a04003 mov r4, r3 | |
fac: e1a09002 mov r9, r2 | |
fb0: e1a0b001 mov fp, r1 | |
fb4: e1a07000 mov r7, r0 | |
fb8: e3510000 cmp r1, #0 | |
fbc: 0a00000a beq fec <seccomp_actions_logged_handler+0x4c> | |
fc0: e3a00015 mov r0, #21 | |
fc4: ebfffffe bl 0 <capable> | |
fc8: e1a01000 mov r1, r0 | |
fcc: e3e00000 mvn r0, #0 | |
fd0: e3510000 cmp r1, #0 | |
fd4: 0a000097 beq 1238 <seccomp_actions_logged_handler+0x298> | |
fd8: e28d002c add r0, sp, #44 ; 0x2c | |
fdc: e3a01034 mov r1, #52 ; 0x34 | |
fe0: e58d4004 str r4, [sp, #4] | |
fe4: ebfffffe bl 0 <__memzero> | |
fe8: ea000028 b 1090 <seccomp_actions_logged_handler+0xf0> | |
fec: e28d502c add r5, sp, #44 ; 0x2c | |
ff0: e3a01034 mov r1, #52 ; 0x34 | |
ff4: e58d4004 str r4, [sp, #4] | |
ff8: e3a06034 mov r6, #52 ; 0x34 | |
ffc: e1a00005 mov r0, r5 | |
1000: ebfffffe bl 0 <__memzero> | |
1004: e3000000 movw r0, #0 | |
1008: e300a000 movw sl, #0 | |
100c: e3400000 movt r0, #0 | |
1010: e280400c add r4, r0, #12 | |
1014: e3000000 movw r0, #0 | |
1018: e340a000 movt sl, #0 | |
101c: e3400000 movt r0, #0 | |
1020: e5908000 ldr r8, [r0] | |
1024: e3a00000 mov r0, #0 | |
1028: e514100c ldr r1, [r4, #-12] | |
102c: e1110008 tst r1, r8 | |
1030: 0a000012 beq 1080 <seccomp_actions_logged_handler+0xe0> | |
1034: e3100001 tst r0, #1 | |
1038: 0a000007 beq 105c <seccomp_actions_logged_handler+0xbc> | |
103c: e1a00005 mov r0, r5 | |
1040: e1a0100a mov r1, sl | |
1044: e1a02006 mov r2, r6 | |
1048: ebfffffe bl 0 <strscpy> | |
104c: e3500000 cmp r0, #0 | |
1050: ba00007a blt 1240 <seccomp_actions_logged_handler+0x2a0> | |
1054: e0466000 sub r6, r6, r0 | |
1058: e0855000 add r5, r5, r0 | |
105c: e5141008 ldr r1, [r4, #-8] | |
1060: e1a00005 mov r0, r5 | |
1064: e1a02006 mov r2, r6 | |
1068: ebfffffe bl 0 <strscpy> | |
106c: e3500000 cmp r0, #0 | |
1070: ba000072 blt 1240 <seccomp_actions_logged_handler+0x2a0> | |
1074: e0466000 sub r6, r6, r0 | |
1078: e0855000 add r5, r5, r0 | |
107c: e3a00001 mov r0, #1 | |
1080: e3560000 cmp r6, #0 | |
1084: 14941008 ldrne r1, [r4], #8 | |
1088: 13510000 cmpne r1, #0 | |
108c: 1affffe5 bne 1028 <seccomp_actions_logged_handler+0x88> | |
1090: e28d0008 add r0, sp, #8 | |
1094: e8b70078 ldm r7!, {r3, r4, r5, r6} | |
1098: e1a02000 mov r2, r0 | |
109c: e8a20078 stmia r2!, {r3, r4, r5, r6} | |
10a0: e897007a ldm r7, {r1, r3, r4, r5, r6} | |
10a4: e59dc088 ldr ip, [sp, #136] ; 0x88 | |
10a8: e882007a stm r2, {r1, r3, r4, r5, r6} | |
10ac: e3a01034 mov r1, #52 ; 0x34 | |
10b0: e1a02009 mov r2, r9 | |
10b4: e59d3004 ldr r3, [sp, #4] | |
10b8: e58d1010 str r1, [sp, #16] | |
10bc: e28d102c add r1, sp, #44 ; 0x2c | |
10c0: e58d100c str r1, [sp, #12] | |
10c4: e1a0100b mov r1, fp | |
10c8: e58dc000 str ip, [sp] | |
10cc: ebfffffe bl 0 <proc_dostring> | |
10d0: e3500000 cmp r0, #0 | |
10d4: 1a000057 bne 1238 <seccomp_actions_logged_handler+0x298> | |
10d8: e35b0000 cmp fp, #0 | |
10dc: 0a000055 beq 1238 <seccomp_actions_logged_handler+0x298> | |
10e0: e59d000c ldr r0, [sp, #12] | |
10e4: e3001000 movw r1, #0 | |
10e8: e58d0060 str r0, [sp, #96] ; 0x60 | |
10ec: e28d0060 add r0, sp, #96 ; 0x60 | |
10f0: e3401000 movt r1, #0 | |
10f4: ebfffffe bl 0 <strsep> | |
10f8: e3500000 cmp r0, #0 | |
10fc: 0a000052 beq 124c <seccomp_actions_logged_handler+0x2ac> | |
1100: e3004000 movw r4, #0 | |
1104: e3006000 movw r6, #0 | |
1108: e3007000 movw r7, #0 | |
110c: e3009000 movw r9, #0 | |
1110: e3008000 movw r8, #0 | |
1114: e28d5060 add r5, sp, #96 ; 0x60 | |
1118: e1a0b000 mov fp, r0 | |
111c: e3a0a000 mov sl, #0 | |
1120: e3404000 movt r4, #0 | |
1124: e3406000 movt r6, #0 | |
1128: e3407000 movt r7, #0 | |
112c: e3409000 movt r9, #0 | |
1130: e3408000 movt r8, #0 | |
1134: e5db0000 ldrb r0, [fp] | |
1138: e3500000 cmp r0, #0 | |
113c: 0a00003a beq 122c <seccomp_actions_logged_handler+0x28c> | |
1140: e1a00004 mov r0, r4 | |
1144: e1a0100b mov r1, fp | |
1148: ebfffffe bl 0 <strcmp> | |
114c: e3500000 cmp r0, #0 | |
1150: e1a00009 mov r0, r9 | |
1154: 0a00002c beq 120c <seccomp_actions_logged_handler+0x26c> | |
1158: e1a00007 mov r0, r7 | |
115c: e1a0100b mov r1, fp | |
1160: ebfffffe bl 0 <strcmp> | |
1164: e3500000 cmp r0, #0 | |
1168: 0a00001e beq 11e8 <seccomp_actions_logged_handler+0x248> | |
116c: e1a00008 mov r0, r8 | |
1170: e1a0100b mov r1, fp | |
1174: ebfffffe bl 0 <strcmp> | |
1178: e3500000 cmp r0, #0 | |
117c: 0a00001b beq 11f0 <seccomp_actions_logged_handler+0x250> | |
1180: e3000000 movw r0, #0 | |
1184: e1a0100b mov r1, fp | |
1188: e3400000 movt r0, #0 | |
118c: ebfffffe bl 0 <strcmp> | |
1190: e3500000 cmp r0, #0 | |
1194: 0a000017 beq 11f8 <seccomp_actions_logged_handler+0x258> | |
1198: e3000000 movw r0, #0 | |
119c: e1a0100b mov r1, fp | |
11a0: e3400000 movt r0, #0 | |
11a4: ebfffffe bl 0 <strcmp> | |
11a8: e3500000 cmp r0, #0 | |
11ac: 0a000013 beq 1200 <seccomp_actions_logged_handler+0x260> | |
11b0: e3000000 movw r0, #0 | |
11b4: e1a0100b mov r1, fp | |
11b8: e3400000 movt r0, #0 | |
11bc: ebfffffe bl 0 <strcmp> | |
11c0: e3500000 cmp r0, #0 | |
11c4: 0a00000f beq 1208 <seccomp_actions_logged_handler+0x268> | |
11c8: e3000000 movw r0, #0 | |
11cc: e1a0100b mov r1, fp | |
11d0: e3400000 movt r0, #0 | |
11d4: ebfffffe bl 0 <strcmp> | |
11d8: e3500000 cmp r0, #0 | |
11dc: 1a000017 bne 1240 <seccomp_actions_logged_handler+0x2a0> | |
11e0: e2890030 add r0, r9, #48 ; 0x30 | |
11e4: ea000008 b 120c <seccomp_actions_logged_handler+0x26c> | |
11e8: e2890008 add r0, r9, #8 | |
11ec: ea000006 b 120c <seccomp_actions_logged_handler+0x26c> | |
11f0: e2890010 add r0, r9, #16 | |
11f4: ea000004 b 120c <seccomp_actions_logged_handler+0x26c> | |
11f8: e2890018 add r0, r9, #24 | |
11fc: ea000002 b 120c <seccomp_actions_logged_handler+0x26c> | |
1200: e2890020 add r0, r9, #32 | |
1204: ea000000 b 120c <seccomp_actions_logged_handler+0x26c> | |
1208: e2890028 add r0, r9, #40 ; 0x28 | |
120c: e5900000 ldr r0, [r0] | |
1210: e1a01006 mov r1, r6 | |
1214: e180a00a orr sl, r0, sl | |
1218: e1a00005 mov r0, r5 | |
121c: ebfffffe bl 0 <strsep> | |
1220: e1a0b000 mov fp, r0 | |
1224: e3500000 cmp r0, #0 | |
1228: 1affffc1 bne 1134 <seccomp_actions_logged_handler+0x194> | |
122c: e3e00015 mvn r0, #21 | |
1230: e31a0040 tst sl, #64 ; 0x40 | |
1234: 0a000005 beq 1250 <seccomp_actions_logged_handler+0x2b0> | |
1238: e28dd064 add sp, sp, #100 ; 0x64 | |
123c: e8bd8ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} | |
1240: e3e00015 mvn r0, #21 | |
1244: e28dd064 add sp, sp, #100 ; 0x64 | |
1248: e8bd8ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} | |
124c: e3a0a000 mov sl, #0 | |
1250: e3000000 movw r0, #0 | |
1254: e3400000 movt r0, #0 | |
1258: e580a000 str sl, [r0] | |
125c: e3a00000 mov r0, #0 | |
1260: e28dd064 add sp, sp, #100 ; 0x64 | |
1264: e8bd8ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} | |
Disassembly of section .data: | |
00000000 <seccomp_actions_logged>: | |
0: 0000003f andeq r0, r0, pc, lsr r0 | |
00000004 <seccomp_sysctl_path>: | |
4: 0000003b andeq r0, r0, fp, lsr r0 | |
8: 00000042 andeq r0, r0, r2, asr #32 | |
c: 00000000 andeq r0, r0, r0 | |
00000010 <seccomp_sysctl_table>: | |
10: 0000004a andeq r0, r0, sl, asr #32 | |
14: 00000000 andeq r0, r0, r0 | |
18: 00000034 andeq r0, r0, r4, lsr r0 | |
1c: 00000124 andeq r0, r0, r4, lsr #2 | |
... | |
34: 00000058 andeq r0, r0, r8, asr r0 | |
... | |
40: 000001a4 andeq r0, r0, r4, lsr #3 | |
... | |
Disassembly of section .ARM.exidx: | |
00000000 <.ARM.exidx>: | |
0: 00000000 andeq r0, r0, r0 | |
4: 80b0b0b0 ldrhthi fp, [r0], r0 | |
8: 00000004 andeq r0, r0, r4 | |
c: 80b0b0b0 ldrhthi fp, [r0], r0 | |
10: 0000002c andeq r0, r0, ip, lsr #32 | |
14: 808483b0 ; <UNDEFINED> instruction: 0x808483b0 | |
18: 00000088 andeq r0, r0, r8, lsl #1 | |
1c: 808480b0 strhhi r8, [r4], r0 | |
20: 0000010c andeq r0, r0, ip, lsl #2 | |
24: 801f84bf ; <UNDEFINED> instruction: 0x801f84bf | |
28: 000004a8 andeq r0, r0, r8, lsr #9 | |
2c: 80b0b0b0 ldrhthi fp, [r0], r0 | |
30: 000004c0 andeq r0, r0, r0, asr #9 | |
34: 80b0b0b0 ldrhthi fp, [r0], r0 | |
38: 000004c4 andeq r0, r0, r4, asr #9 | |
3c: 80b0b0b0 ldrhthi fp, [r0], r0 | |
40: 000004f8 strdeq r0, [r0], -r8 | |
44: 8004afb0 ; <UNDEFINED> instruction: 0x8004afb0 | |
48: 00000c60 andeq r0, r0, r0, ror #24 | |
4c: 80aeb0b0 strhthi fp, [lr], r0 | |
50: 00000fa0 andeq r0, r0, r0, lsr #31 | |
54: 8018afb0 ; <UNDEFINED> instruction: 0x8018afb0 | |
Disassembly of section .alt.smp.init: | |
00000000 <.alt.smp.init>: | |
0: 00000010 andeq r0, r0, r0, lsl r0 | |
4: f5d0f000 pld [r0] | |
8: 00000040 andeq r0, r0, r0, asr #32 | |
c: f5d4f000 pld [r4] | |
10: 000005d8 ldrdeq r0, [r0], -r8 | |
14: e320f000 nop {0} | |
18: 00000a10 andeq r0, r0, r0, lsl sl | |
1c: f5d0f000 pld [r0] | |
20: 00000a38 andeq r0, r0, r8, lsr sl | |
24: f5d6f000 pld [r6] | |
28: 00000b88 andeq r0, r0, r8, lsl #23 | |
2c: e320f000 nop {0} | |
Disassembly of section .rodata.str: | |
00000000 <.rodata.str>: | |
0: 6b2f2e2e blvs bcb8c0 <seccomp_actions_logged_handler+0xbca920> | |
4: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
8: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
c: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffe88 <seccomp_actions_logged_handler+0xffffeee8> | |
10: 00632e70 rsbeq r2, r3, r0, ror lr | |
14: 6b2f2e2e blvs bcb8d4 <seccomp_actions_logged_handler+0xbca934> | |
18: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
1c: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
20: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffe9c <seccomp_actions_logged_handler+0xffffeefc> | |
24: 00632e70 rsbeq r2, r3, r0, ror lr | |
28: 6b2f2e2e blvs bcb8e8 <seccomp_actions_logged_handler+0xbca948> | |
2c: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
30: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
34: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffeb0 <seccomp_actions_logged_handler+0xffffef10> | |
38: 00632e70 rsbeq r2, r3, r0, ror lr | |
3c: 6b2f2e2e blvs bcb8fc <seccomp_actions_logged_handler+0xbca95c> | |
40: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
44: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
48: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffec4 <seccomp_actions_logged_handler+0xffffef24> | |
4c: 00632e70 rsbeq r2, r3, r0, ror lr | |
50: 6b2f2e2e blvs bcb910 <seccomp_actions_logged_handler+0xbca970> | |
54: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
58: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
5c: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffed8 <seccomp_actions_logged_handler+0xffffef38> | |
60: 00632e70 rsbeq r2, r3, r0, ror lr | |
64: 6b2f2e2e blvs bcb924 <seccomp_actions_logged_handler+0xbca984> | |
68: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
6c: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
70: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffeec <seccomp_actions_logged_handler+0xffffef4c> | |
74: 00632e70 rsbeq r2, r3, r0, ror lr | |
78: 6b2f2e2e blvs bcb938 <seccomp_actions_logged_handler+0xbca998> | |
7c: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
80: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
84: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; ffffff00 <seccomp_actions_logged_handler+0xffffef60> | |
88: 00632e70 rsbeq r2, r3, r0, ror lr | |
8c: 6b2f2e2e blvs bcb94c <seccomp_actions_logged_handler+0xbca9ac> | |
90: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
94: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
98: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; ffffff14 <seccomp_actions_logged_handler+0xffffef74> | |
9c: 00632e70 rsbeq r2, r3, r0, ror lr | |
a0: 6b2f2e2e blvs bcb960 <seccomp_actions_logged_handler+0xbca9c0> | |
a4: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
a8: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
ac: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; ffffff28 <seccomp_actions_logged_handler+0xffffef88> | |
b0: 00632e70 rsbeq r2, r3, r0, ror lr | |
b4: 6b2f2e2e blvs bcb974 <seccomp_actions_logged_handler+0xbca9d4> | |
b8: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
bc: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
c0: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; ffffff3c <seccomp_actions_logged_handler+0xffffef9c> | |
c4: 00632e70 rsbeq r2, r3, r0, ror lr | |
c8: 6b2f2e2e blvs bcb988 <seccomp_actions_logged_handler+0xbca9e8> | |
cc: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
d0: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
d4: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; ffffff50 <seccomp_actions_logged_handler+0xffffefb0> | |
d8: 00632e70 rsbeq r2, r3, r0, ror lr | |
Disassembly of section __bug_table: | |
00000000 <__bug_table>: | |
0: 000000fc strdeq r0, [r0], -ip | |
4: 00000000 andeq r0, r0, r0 | |
8: 00000320 andeq r0, r0, r0, lsr #6 | |
c: 00000bf8 strdeq r0, [r0], -r8 | |
10: 00000014 andeq r0, r0, r4, lsl r0 | |
14: 000000e0 andeq r0, r0, r0, ror #1 | |
18: 00000c00 andeq r0, r0, r0, lsl #24 | |
1c: 00000028 andeq r0, r0, r8, lsr #32 | |
20: 000000ee andeq r0, r0, lr, ror #1 | |
24: 00000c08 andeq r0, r0, r8, lsl #24 | |
28: 0000003c andeq r0, r0, ip, lsr r0 | |
2c: 000000e0 andeq r0, r0, r0, ror #1 | |
30: 00000c10 andeq r0, r0, r0, lsl ip | |
34: 00000050 andeq r0, r0, r0, asr r0 | |
38: 000001c2 andeq r0, r0, r2, asr #3 | |
3c: 00000c18 andeq r0, r0, r8, lsl ip | |
40: 00000064 andeq r0, r0, r4, rrx | |
44: 000000ee andeq r0, r0, lr, ror #1 | |
48: 00000c20 andeq r0, r0, r0, lsr #24 | |
4c: 00000078 andeq r0, r0, r8, ror r0 | |
50: 000000ee andeq r0, r0, lr, ror #1 | |
54: 00000c28 andeq r0, r0, r8, lsr #24 | |
58: 0000008c andeq r0, r0, ip, lsl #1 | |
5c: 00000117 andeq r0, r0, r7, lsl r1 | |
60: 00000c30 andeq r0, r0, r0, lsr ip | |
64: 000000a0 andeq r0, r0, r0, lsr #1 | |
68: 00000118 andeq r0, r0, r8, lsl r1 | |
6c: 00000c38 andeq r0, r0, r8, lsr ip | |
70: 000000b4 strheq r0, [r0], -r4 | |
74: 00000140 andeq r0, r0, r0, asr #2 | |
78: 00000c40 andeq r0, r0, r0, asr #24 | |
7c: 000000c8 andeq r0, r0, r8, asr #1 | |
80: 00000141 andeq r0, r0, r1, asr #2 | |
Disassembly of section .init.text: | |
00000000 <seccomp_sysctl_init>: | |
0: e92d4800 push {fp, lr} | |
4: e3000000 movw r0, #0 | |
8: e3001000 movw r1, #0 | |
c: e3400000 movt r0, #0 | |
10: e3401000 movt r1, #0 | |
14: ebfffffe bl 0 <register_sysctl_paths> | |
18: e3500000 cmp r0, #0 | |
1c: 0a000001 beq 28 <seccomp_sysctl_init+0x28> | |
20: e3a00000 mov r0, #0 | |
24: e8bd8800 pop {fp, pc} | |
28: e3000000 movw r0, #0 | |
2c: e3400000 movt r0, #0 | |
30: ebfffffe bl 0 <printk> | |
34: e3a00000 mov r0, #0 | |
38: e8bd8800 pop {fp, pc} | |
Disassembly of section .ARM.exidx.init.text: | |
00000000 <.ARM.exidx.init.text>: | |
0: 00000000 andeq r0, r0, r0 | |
4: 808480b0 strhhi r8, [r4], r0 | |
Disassembly of section .initcall6.init: | |
00000000 <__initcall_seccomp_sysctl_init6>: | |
0: 00000000 andeq r0, r0, r0 | |
Disassembly of section .rodata.str1.1: | |
00000000 <.L.str>: | |
0: 6b2f2e2e blvs bcb8c0 <seccomp_actions_logged_handler+0xbca920> | |
4: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
8: 65732f6c ldrbvs r2, [r3, #-3948]! ; 0xfffff094 | |
c: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffe88 <seccomp_actions_logged_handler+0xffffeee8> | |
10: 00632e70 rsbeq r2, r3, r0, ror lr | |
00000014 <.L.str.4>: | |
14: 65733401 ldrbvs r3, [r3, #-1025]! ; 0xfffffbff | |
18: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffe94 <seccomp_actions_logged_handler+0xffffeef4> | |
1c: 73203a70 ; <UNDEFINED> instruction: 0x73203a70 | |
20: 74637379 strbtvc r7, [r3], #-889 ; 0xfffffc87 | |
24: 6572206c ldrbvs r2, [r2, #-108]! ; 0xffffff94 | |
28: 74736967 ldrbtvc r6, [r3], #-2407 ; 0xfffff699 | |
2c: 69746172 ldmdbvs r4!, {r1, r4, r5, r6, r8, sp, lr}^ | |
30: 66206e6f strtvs r6, [r0], -pc, ror #28 | |
34: 656c6961 strbvs r6, [ip, #-2401]! ; 0xfffff69f | |
38: 6b000a64 blvs 29d0 <seccomp_actions_logged_handler+0x1a30> | |
3c: 656e7265 strbvs r7, [lr, #-613]! ; 0xfffffd9b | |
40: 6573006c ldrbvs r0, [r3, #-108]! ; 0xffffff94 | |
44: 6d6f6363 stclvs 3, cr6, [pc, #-396]! ; fffffec0 <seccomp_actions_logged_handler+0xffffef20> | |
48: 63610070 cmnvs r1, #112 ; 0x70 | |
4c: 6e6f6974 ; <UNDEFINED> instruction: 0x6e6f6974 | |
50: 76615f73 uqsub16vc r5, r1, r3 | |
54: 006c6961 rsbeq r6, ip, r1, ror #18 | |
58: 69746361 ldmdbvs r4!, {r0, r5, r6, r8, r9, sp, lr}^ | |
5c: 5f736e6f svcpl 0x00736e6f | |
60: 67676f6c strbvs r6, [r7, -ip, ror #30]! | |
64: andcs r6, r0, r5, ror #8 | |
00000067 <.L.str.9>: | |
67: stmdbvs fp!, {r5}^ | |
00000069 <.L.str.10>: | |
69: 6c6c696b ; <UNDEFINED> instruction: 0x6c6c696b | |
6d: 6f72705f svcvs 0x0072705f | |
71: 73736563 cmnvc r3, #415236096 ; 0x18c00000 | |
... | |
00000076 <.L.str.11>: | |
76: 6c6c696b ; <UNDEFINED> instruction: 0x6c6c696b | |
7a: 7268745f rsbvc r7, r8, #1593835520 ; 0x5f000000 | |
7e: 00646165 rsbeq r6, r4, r5, ror #2 | |
00000082 <.L.str.12>: | |
82: 70617274 rsbvc r7, r1, r4, ror r2 | |
... | |
00000087 <.L.str.13>: | |
87: 6e727265 cdpvs 2, 7, cr7, cr2, cr5, {3} | |
8b: rsbsvc r0, r4, #111 ; 0x6f | |
0000008d <.L.str.14>: | |
8d: 63617274 cmnvs r1, #116, 4 ; 0x40000007 | |
91: svcvs 0x006c0065 | |
00000093 <.L.str.15>: | |
93: 00676f6c rsbeq r6, r7, ip, ror #30 | |
00000097 <.L.str.16>: | |
97: 6f6c6c61 svcvs 0x006c6c61 | |
9b: Address 0x000000000000009b is out of bounds. | |
Disassembly of section .rodata: | |
00000000 <seccomp_actions_avail>: | |
0: 6c6c696b ; <UNDEFINED> instruction: 0x6c6c696b | |
4: 6f72705f svcvs 0x0072705f | |
8: 73736563 cmnvc r3, #415236096 ; 0x18c00000 | |
c: 6c696b20 ; <UNDEFINED> instruction: 0x6c696b20 | |
10: 68745f6c ldmdavs r4!, {r2, r3, r5, r6, r8, r9, sl, fp, ip, lr}^ | |
14: 64616572 strbtvs r6, [r1], #-1394 ; 0xfffffa8e | |
18: 61727420 cmnvs r2, r0, lsr #8 | |
1c: 72652070 rsbvc r2, r5, #112 ; 0x70 | |
20: 206f6e72 rsbcs r6, pc, r2, ror lr ; <UNPREDICTABLE> | |
24: 63617274 cmnvs r1, #116, 4 ; 0x40000007 | |
28: 6f6c2065 svcvs 0x006c2065 | |
2c: 6c612067 stclvs 0, cr2, [r1], #-412 ; 0xfffffe64 | |
30: 00776f6c rsbseq r6, r7, ip, ror #30 | |
00000034 <seccomp_log_names>: | |
34: 00000001 andeq r0, r0, r1 | |
38: 00000069 andeq r0, r0, r9, rrx | |
3c: 00000002 andeq r0, r0, r2 | |
40: 00000076 andeq r0, r0, r6, ror r0 | |
44: 00000004 andeq r0, r0, r4 | |
48: 00000082 andeq r0, r0, r2, lsl #1 | |
4c: 00000008 andeq r0, r0, r8 | |
50: 00000087 andeq r0, r0, r7, lsl #1 | |
54: 00000010 andeq r0, r0, r0, lsl r0 | |
58: 0000008d andeq r0, r0, sp, lsl #1 | |
5c: 00000020 andeq r0, r0, r0, lsr #32 | |
60: 00000093 muleq r0, r3, r0 | |
64: 00000040 andeq r0, r0, r0, asr #32 | |
68: 00000097 muleq r0, r7, r0 | |
... | |
Disassembly of section .comment: | |
00000000 <.comment>: | |
0: 616c6300 cmnvs ip, r0, lsl #6 | |
4: 7620676e strtvc r6, [r0], -lr, ror #14 | |
8: 69737265 ldmdbvs r3!, {r0, r2, r5, r6, r9, ip, sp, lr}^ | |
c: 38206e6f stmdacc r0!, {r0, r1, r2, r3, r5, r6, r9, sl, fp, sp, lr} | |
10: 302e302e eorcc r3, lr, lr, lsr #32 | |
14: 74682820 strbtvc r2, [r8], #-2080 ; 0xfffff7e0 | |
18: 3a737074 bcc 1cdc1f0 <seccomp_actions_logged_handler+0x1cdb250> | |
1c: 69672f2f stmdbvs r7!, {r0, r1, r2, r3, r5, r8, r9, sl, fp, sp}^ | |
20: 6c6c2e74 stclvs 14, cr2, [ip], #-464 ; 0xfffffe30 | |
24: 6f2e6d76 svcvs 0x002e6d76 | |
28: 672f6772 ; <UNDEFINED> instruction: 0x672f6772 | |
2c: 632f7469 ; <UNDEFINED> instruction: 0x632f7469 | |
30: 676e616c strbvs r6, [lr, -ip, ror #2]! | |
34: 7469672e strbtvc r6, [r9], #-1838 ; 0xfffff8d2 | |
38: 33363020 teqcc r6, #32 | |
3c: 32353935 eorscc r3, r5, #868352 ; 0xd4000 | |
40: 35366264 ldrcc r6, [r6, #-612]! ; 0xfffffd9c | |
44: 30316231 eorscc r6, r1, r1, lsr r2 | |
48: 66323434 ; <UNDEFINED> instruction: 0x66323434 | |
4c: 62353261 eorsvs r3, r5, #268435462 ; 0x10000006 | |
50: 36306532 ; <UNDEFINED> instruction: 0x36306532 | |
54: 33333735 teqcc r3, #13893632 ; 0xd40000 | |
58: 64663232 strbtvs r3, [r6], #-562 ; 0xfffffdce | |
5c: 32613964 rsbcc r3, r1, #100, 18 ; 0x190000 | |
60: 28202933 stmdacs r0!, {r0, r1, r4, r5, r8, fp, sp} | |
64: 70747468 rsbsvc r7, r4, r8, ror #8 | |
68: 2f2f3a73 svccs 0x002f3a73 | |
6c: 2e746967 vsubcs.f16 s13, s8, s15 ; <UNPREDICTABLE> | |
70: 6d766c6c ldclvs 12, cr6, [r6, #-432]! ; 0xfffffe50 | |
74: 67726f2e ldrbvs r6, [r2, -lr, lsr #30]! | |
78: 7469672f strbtvc r6, [r9], #-1839 ; 0xfffff8d1 | |
7c: 766c6c2f strbtvc r6, [ip], -pc, lsr #24 | |
80: 69672e6d stmdbvs r7!, {r0, r2, r3, r5, r6, r9, sl, fp, sp}^ | |
84: 64622074 strbtvs r2, [r2], #-116 ; 0xffffff8c | |
88: 39373533 ldmdbcc r7!, {r0, r1, r4, r5, r8, sl, ip, sp} | |
8c: 63646264 cmnvs r4, #100, 4 ; 0x40000006 | |
90: 33303132 teqcc r0, #-2147483636 ; 0x8000000c | |
94: 65336362 ldrvs r6, [r3, #-866]! ; 0xfffffc9e | |
98: 37336165 ldrcc r6, [r3, -r5, ror #2]! | |
9c: 38383037 ldmdacc r8!, {r0, r1, r2, r4, r5, ip, sp} | |
a0: 34323663 ldrtcc r3, [r2], #-1635 ; 0xfffff99d | |
a4: 64633061 strbtvs r3, [r3], #-97 ; 0xffffff9f | |
a8: 63306236 teqvs r0, #1610612739 ; 0x60000003 | |
ac: 00293233 eoreq r3, r9, r3, lsr r2 | |
Disassembly of section .ARM.attributes: | |
00000000 <.ARM.attributes>: | |
0: 00003c41 andeq r3, r0, r1, asr #24 | |
4: 61656100 cmnvs r5, r0, lsl #2 | |
8: 01006962 tsteq r0, r2, ror #18 | |
c: 00000032 andeq r0, r0, r2, lsr r0 | |
10: 302e3243 eorcc r3, lr, r3, asr #4 | |
14: 37050039 smladxcc r5, r9, r0, r0 | |
18: 0600412d streq r4, [r0], -sp, lsr #2 | |
1c: 0841070a stmdaeq r1, {r1, r3, r8, r9, sl}^ | |
20: 0a020901 beq 8242c <seccomp_actions_logged_handler+0x8148c> | |
24: 12011102 andne r1, r1, #-2147483648 ; 0x80000000 | |
28: 15011402 strne r1, [r1, #-1026] ; 0xfffffbfe | |
2c: 18031701 stmdane r3, {r0, r8, r9, sl, ip} | |
30: 1a011901 bne 4643c <seccomp_actions_logged_handler+0x4549c> | |
34: 22011e02 andcs r1, r1, #2, 28 | |
38: 2a012601 bcs 49844 <seccomp_actions_logged_handler+0x488a4> | |
3c: Address 0x000000000000003c is out of bounds. | |
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