Created
January 10, 2022 03:07
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| /dts-v1/; | |
| /memreserve/ 0x0000000000000000 0x0000000000100000; | |
| / { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| compatible = "annapurna-labs,alpine"; | |
| clock-ranges; | |
| version = "1.1"; | |
| model = "Annapurna Labs Alpine V2 UBNT"; | |
| chosen { | |
| }; | |
| aliases { | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00 0x00 0x00 0x00>; | |
| }; | |
| psci { | |
| compatible = "arm,psci-0.2", "arm,psci"; | |
| method = "smc"; | |
| cpu_on = <0x84000003>; | |
| cpu_suspend = <0x84000001>; | |
| }; | |
| cpus { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x00 0x00>; | |
| enable-method = "psci"; | |
| next-level-cache = <0x03>; | |
| cpu-idle-states = <0x04>; | |
| linux,phandle = <0x05>; | |
| phandle = <0x05>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x00 0x01>; | |
| enable-method = "psci"; | |
| next-level-cache = <0x03>; | |
| cpu-idle-states = <0x04>; | |
| linux,phandle = <0x06>; | |
| phandle = <0x06>; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x00 0x02>; | |
| enable-method = "psci"; | |
| next-level-cache = <0x03>; | |
| cpu-idle-states = <0x04>; | |
| linux,phandle = <0x07>; | |
| phandle = <0x07>; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x00 0x03>; | |
| enable-method = "psci"; | |
| next-level-cache = <0x03>; | |
| cpu-idle-states = <0x04>; | |
| linux,phandle = <0x08>; | |
| phandle = <0x08>; | |
| }; | |
| cache { | |
| compatible = "cache"; | |
| linux,phandle = <0x03>; | |
| phandle = <0x03>; | |
| }; | |
| idle-states { | |
| cpu-sleep { | |
| compatible = "arm,idle-state"; | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x10000>; | |
| entry-latency-us = <0x0a>; | |
| exit-latency-us = <0x0a>; | |
| min-residency-us = <0x3e8>; | |
| linux,phandle = <0x04>; | |
| phandle = <0x04>; | |
| }; | |
| }; | |
| }; | |
| soc { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| compatible = "simple-bus"; | |
| interrupt-parent = <0x01>; | |
| ranges; | |
| arch-timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08>; | |
| clock-frequency = <0x2faf080>; | |
| }; | |
| gic_main { | |
| compatible = "arm,gic-v3"; | |
| #interrupt-cells = <0x03>; | |
| #size-cells = <0x00>; | |
| #address-cells = <0x00>; | |
| interrupt-controller; | |
| reg = <0x00 0xf0200000 0x00 0x10000 0x00 0xf0280000 0x00 0x200000 0x00 0xf0100000 0x00 0x2000 0x00 0xf0110000 0x00 0x2000 0x00 0xf0120000 0x00 0x2000>; | |
| interrupts = <0x01 0x09 0xf04>; | |
| linux,phandle = <0x01>; | |
| phandle = <0x01>; | |
| }; | |
| ccu { | |
| compatible = "annapurna-labs,al-ccu"; | |
| reg = <0x00 0xf0090000 0x00 0x10000>; | |
| io_coherency = <0x01>; | |
| }; | |
| msix { | |
| compatible = "annapurna-labs,alpine-msix", "al,alpine-msix"; | |
| reg = <0x00 0xfbe00000 0x00 0x100000>; | |
| interrupts = <0x00 0xa0 0x01 0x00 0x13f 0x01>; | |
| interrupt-controller; | |
| msi-controller; | |
| al,msi-base-spi = <0xa1>; | |
| al,msi-num-spis = <0x9e>; | |
| interrupt-parent = <0x01>; | |
| linux,phandle = <0x02>; | |
| phandle = <0x02>; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04>; | |
| interrupt-affinity = <0x05 0x06 0x07 0x08>; | |
| }; | |
| nb_service { | |
| compatible = "annapurna-labs,al-nb-service", "al,alpine-sysfabric-service", "syscon"; | |
| reg = <0x00 0xf0070000 0x00 0x10000>; | |
| interrupts = <0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04>; | |
| }; | |
| pbs { | |
| compatible = "annapurna-labs,al-pbs"; | |
| reg = <0x00 0xfd8a8000 0x00 0x1000>; | |
| interrupts = <0x00 0x00 0x04>; | |
| }; | |
| tdm { | |
| compatible = "annapurna-labs,al-tdm"; | |
| reg = <0x00 0xf2300000 0x00 0x11000>; | |
| }; | |
| timer0 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00 0xfd890000 0x00 0x1000>; | |
| interrupts = <0x00 0x09 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| timer1 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00 0xfd891000 0x00 0x1000>; | |
| interrupts = <0x00 0x0a 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| timer2 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00 0xfd892000 0x00 0x1000>; | |
| interrupts = <0x00 0x0b 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| timer3 { | |
| compatible = "arm,sp804", "arm,primecell"; | |
| reg = <0x00 0xfd893000 0x00 0x1000>; | |
| interrupts = <0x00 0x0c 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| }; | |
| wdt0 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00 0xfd88c000 0x00 0x1000>; | |
| interrupts = <0x00 0x0d 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| linux,phandle = <0x0a>; | |
| phandle = <0x0a>; | |
| }; | |
| wdt1 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00 0xfd88d000 0x00 0x1000>; | |
| interrupts = <0x00 0x0e 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| }; | |
| wdt2 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00 0xfd88e000 0x00 0x1000>; | |
| interrupts = <0x00 0x0f 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| }; | |
| wdt3 { | |
| compatible = "arm,sp805", "arm,primecell"; | |
| reg = <0x00 0xfd88f000 0x00 0x1000>; | |
| interrupts = <0x00 0x10 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| status = "disabled"; | |
| }; | |
| i2c-pld { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00 0xfd880000 0x00 0x1000>; | |
| interrupts = <0x00 0x15 0x04>; | |
| clocks = <0x09>; | |
| clock-frequency = <0x186a0>; | |
| i2c-ss-scl-hcnt-raw = <0x855>; | |
| i2c-ss-scl-lcnt-raw = <0xb0b>; | |
| i2c-fs-scl-hcnt-raw = <0x19d>; | |
| i2c-fs-scl-lcnt-raw = <0x320>; | |
| i2c-hs-scl-hcnt-raw = <0xf3>; | |
| i2c-hs-scl-lcnt-raw = <0x198>; | |
| i2c_mux@71 { | |
| compatible = "pca9546"; | |
| reg = <0x71>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| i2c@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| s35390a@30 { | |
| compatible = "sii,s35390a"; | |
| reg = <0x30>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c-gen { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "snps,designware-i2c"; | |
| reg = <0x00 0xfd894000 0x00 0x1000>; | |
| interrupts = <0x00 0x08 0x04>; | |
| clocks = <0x09>; | |
| clock-frequency = <0x186a0>; | |
| i2c-ss-scl-hcnt-raw = <0x855>; | |
| i2c-ss-scl-lcnt-raw = <0xb0b>; | |
| i2c-fs-scl-hcnt-raw = <0x19d>; | |
| i2c-fs-scl-lcnt-raw = <0x320>; | |
| i2c-hs-scl-hcnt-raw = <0xf3>; | |
| i2c-hs-scl-lcnt-raw = <0x198>; | |
| status = "disabled"; | |
| }; | |
| gpio0 { | |
| #gpio-cells = <0x02>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00 0xfd887000 0x00 0x1000>; | |
| interrupts = <0x00 0x02 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x00>; | |
| }; | |
| gpio1 { | |
| #gpio-cells = <0x02>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00 0xfd888000 0x00 0x1000>; | |
| interrupts = <0x00 0x03 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x08>; | |
| }; | |
| gpio2 { | |
| #gpio-cells = <0x02>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00 0xfd889000 0x00 0x1000>; | |
| interrupts = <0x00 0x04 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x10>; | |
| linux,phandle = <0x10>; | |
| phandle = <0x10>; | |
| }; | |
| gpio3 { | |
| #gpio-cells = <0x02>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00 0xfd88a000 0x00 0x1000>; | |
| interrupts = <0x00 0x05 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x18>; | |
| }; | |
| gpio4 { | |
| #gpio-cells = <0x02>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00 0xfd88b000 0x00 0x1000>; | |
| interrupts = <0x00 0x06 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x20>; | |
| }; | |
| gpio5 { | |
| #gpio-cells = <0x02>; | |
| compatible = "arm,pl061", "arm,primecell"; | |
| gpio-controller; | |
| reg = <0x00 0xfd897000 0x00 0x1000>; | |
| interrupts = <0x00 0x07 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "apb_pclk"; | |
| baseidx = <0x28>; | |
| }; | |
| sgpo { | |
| #gpio-cells = <0x02>; | |
| compatible = "annapurna-labs,alpine-sgpo"; | |
| gpio-controller; | |
| reg = <0x00 0xfd8b4000 0x00 0x5000>; | |
| baseidx = <0x30>; | |
| }; | |
| uart0 { | |
| compatible = "ns16550a"; | |
| device_type = "serial"; | |
| reg = <0x00 0xfd883000 0x00 0x1000>; | |
| clock-frequency = <0x00>; | |
| interrupts = <0x00 0x11 0x04>; | |
| reg-shift = <0x02>; | |
| reg-io-width = <0x04>; | |
| }; | |
| uart1 { | |
| compatible = "ns16550a"; | |
| device_type = "serial"; | |
| reg = <0x00 0xfd884000 0x00 0x1000>; | |
| clock-frequency = <0x00>; | |
| interrupts = <0x00 0x12 0x04>; | |
| reg-shift = <0x02>; | |
| reg-io-width = <0x04>; | |
| }; | |
| uart2 { | |
| compatible = "ns16550a"; | |
| device_type = "serial"; | |
| reg = <0x00 0xfd885000 0x00 0x1000>; | |
| clock-frequency = <0x00>; | |
| interrupts = <0x00 0x13 0x04>; | |
| reg-shift = <0x02>; | |
| reg-io-width = <0x04>; | |
| status = "okay"; | |
| }; | |
| uart3 { | |
| compatible = "ns16550a"; | |
| device_type = "serial"; | |
| reg = <0x00 0xfd886000 0x00 0x1000>; | |
| clock-frequency = <0x00>; | |
| interrupts = <0x00 0x14 0x04>; | |
| reg-shift = <0x02>; | |
| reg-io-width = <0x04>; | |
| status = "disabled"; | |
| }; | |
| eth0 { | |
| reg = <0x00 0xfc000000 0x00 0x1000>; | |
| interrupts = <0x00 0x3d 0x04>; | |
| }; | |
| eth1 { | |
| reg = <0x00 0xfc100000 0x00 0x1000>; | |
| interrupts = <0x00 0x3e 0x04>; | |
| }; | |
| eth2 { | |
| reg = <0x00 0xfc200000 0x00 0x1000>; | |
| interrupts = <0x00 0x3f 0x04>; | |
| }; | |
| eth3 { | |
| reg = <0x00 0xfc300000 0x00 0x1000>; | |
| interrupts = <0x00 0x40 0x04>; | |
| }; | |
| reboot { | |
| compatible = "annapurna-labs,alpine-reboot"; | |
| wdt-parent = <0x0a>; | |
| }; | |
| pcie-internal { | |
| compatible = "annapurna-labs,alpine-internal-pcie"; | |
| device_type = "pci"; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| reg = <0x00 0xfbc00000 0x00 0x100000>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x01>; | |
| interrupt-map-mask = <0xf800 0x00 0x00 0x07>; | |
| interrupt-map = <0x4000 0x00 0x00 0x01 0x01 0x00 0x35 0x04 0x4800 0x00 0x00 0x01 0x01 0x00 0x36 0x04>; | |
| msi-parent = <0x02>; | |
| ranges = <0x2000000 0x00 0xfe000000 0x00 0xfe000000 0x00 0x1000000>; | |
| bus-range = <0x00 0x00>; | |
| }; | |
| pcie-external0 { | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00 0xfd800000 0x00 0x20000>; | |
| device_type = "pci"; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x29 0x04>; | |
| msi-parent = <0x02>; | |
| cfg-space-offset = <0x10000>; | |
| ranges = <0x00 0x00 0xfb600000 0x00 0xfb600000 0x00 0x100000 0x1000000 0x00 0x10000 0x00 0xc0000000 0x00 0x10000 0x2000000 0x00 0xc0010000 0x00 0xc0010000 0x00 0x7ff0000>; | |
| bus-range = <0x00 0xff>; | |
| }; | |
| pcie-external1 { | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00 0xfd820000 0x00 0x20000>; | |
| device_type = "pci"; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x2a 0x04>; | |
| msi-parent = <0x02>; | |
| cfg-space-offset = <0x2000>; | |
| ranges = <0x00 0x00 0xfb700000 0x00 0xfb700000 0x00 0x100000 0x1000000 0x00 0x20000 0x00 0xc8000000 0x00 0x10000 0x2000000 0x00 0xc8010000 0x00 0xc8010000 0x00 0x7ff0000>; | |
| bus-range = <0x00 0xff>; | |
| }; | |
| pcie-external2 { | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00 0xfd840000 0x00 0x20000>; | |
| device_type = "pci"; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x2b 0x04>; | |
| msi-parent = <0x02>; | |
| cfg-space-offset = <0x2000>; | |
| ranges = <0x00 0x00 0xfb800000 0x00 0xfb800000 0x00 0x100000 0x1000000 0x00 0x30000 0x00 0xd0000000 0x00 0x10000 0x2000000 0x00 0xd0010000 0x00 0xd0010000 0x00 0x7ff0000>; | |
| bus-range = <0x00 0xff>; | |
| }; | |
| pcie-external3 { | |
| compatible = "annapurna-labs,alpine-external-pcie"; | |
| reg = <0x00 0xfd900000 0x00 0x20000>; | |
| device_type = "pci"; | |
| #size-cells = <0x02>; | |
| #address-cells = <0x03>; | |
| #interrupt-cells = <0x01>; | |
| reg-names = "ecam"; | |
| interrupt-parent = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x2c 0x04>; | |
| msi-parent = <0x02>; | |
| cfg-space-offset = <0x2000>; | |
| ranges = <0x00 0x00 0xfb900000 0x00 0xfb900000 0x00 0x100000 0x1000000 0x00 0x40000 0x00 0xd8000000 0x00 0x10000 0x2000000 0x00 0xd8010000 0x00 0xd8010000 0x00 0x7ff0000>; | |
| bus-range = <0x00 0xff>; | |
| }; | |
| thermal { | |
| compatible = "annapurna-labs,al-thermal"; | |
| reg = <0x00 0xfd860a00 0x00 0x100>; | |
| #thermal-sensor-cells = <0x00>; | |
| linux,phandle = <0x0b>; | |
| phandle = <0x0b>; | |
| }; | |
| thermal-zones { | |
| cpu-thermal { | |
| polling-delay-passive = <0xfa>; | |
| polling-delay = <0x3e8>; | |
| thermal-sensors = <0x0b>; | |
| trips { | |
| cpu-crit { | |
| temperature = <0x19a28>; | |
| hysteresis = <0x7d0>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| nand-flash { | |
| compatible = "annapurna-labs,al-nand"; | |
| reg = <0x00 0xfa100000 0x00 0x202000>; | |
| interrupts = <0x00 0x01 0x04>; | |
| clocks = <0x09>; | |
| clock-names = "sbclk"; | |
| status = "disabled"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| max-onfi-timing-mode = <0x01>; | |
| partition@0 { | |
| label = "al_boot"; | |
| reg = <0x00 0x200000>; | |
| }; | |
| partition@1 { | |
| label = "device_tree"; | |
| reg = <0x200000 0x100000>; | |
| }; | |
| partition@2 { | |
| label = "linux_kernel"; | |
| reg = <0x300000 0x1300000>; | |
| }; | |
| partition@3 { | |
| label = "ubifs"; | |
| reg = <0x1300000 0x1e600000>; | |
| }; | |
| }; | |
| spi { | |
| compatible = "amazon,alpine-dw-apb-ssi", "snps,dw-spi-mmio", "snps,dw-apb-ssi"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0xfd882000 0x00 0x1000>; | |
| interrupts = <0x00 0x17 0x04>; | |
| num-chipselect = <0x04>; | |
| bus-num = <0x00>; | |
| clocks = <0x09>; | |
| clock-names = "sbclk"; | |
| spiflash@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "spi_flash_jedec_detection"; | |
| spi-max-frequency = <0x23c3460>; | |
| reg = <0x00>; | |
| partition@0 { | |
| reg = <0x00 0x1c0000>; | |
| label = "u-boot"; | |
| }; | |
| partition@1 { | |
| reg = <0x1c0000 0x10000>; | |
| label = "u-boot-env"; | |
| }; | |
| partition@2 { | |
| reg = <0x1d0000 0x10000>; | |
| label = "u-boot-env-2"; | |
| }; | |
| partition@3 { | |
| reg = <0x1e0000 0x10000>; | |
| label = "Factory"; | |
| }; | |
| partition@4 { | |
| reg = <0x1f0000 0x10000>; | |
| label = "EEPROM"; | |
| }; | |
| partition@5 { | |
| reg = <0x200000 0x3e00000>; | |
| label = "recovery"; | |
| }; | |
| }; | |
| }; | |
| clocks { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| refclk { | |
| #clock-cells = <0x00>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x16e3600>; | |
| }; | |
| sbclk { | |
| #clock-cells = <0x00>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0xf4240>; | |
| linux,phandle = <0x09>; | |
| phandle = <0x09>; | |
| }; | |
| nbclk { | |
| #clock-cells = <0x00>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0xf4240>; | |
| }; | |
| cpuclk { | |
| #clock-cells = <0x00>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0xf4240>; | |
| }; | |
| }; | |
| serdes { | |
| compatible = "annapurna-labs,al-serdes"; | |
| reg = <0x00 0xfd8c0000 0x00 0x2400>; | |
| }; | |
| mc { | |
| compatible = "annapurna-labs,alpine-mc"; | |
| reg = <0x00 0xf0080000 0x00 0x10000>; | |
| }; | |
| pinctrl { | |
| compatible = "annapurna-labs,alpine-pinctrl"; | |
| reg = <0x00 0xfd8a8000 0x00 0x1000>; | |
| if_nor_8 { | |
| id = "if_nor_8"; | |
| arg = <0x00>; | |
| }; | |
| if_nor_16 { | |
| id = "if_nor_16"; | |
| arg = <0x00>; | |
| }; | |
| if_nor_cs_0 { | |
| id = "if_nor_cs_0"; | |
| arg = <0x00>; | |
| }; | |
| if_nor_cs_1 { | |
| id = "if_nor_cs_1"; | |
| arg = <0x00>; | |
| }; | |
| if_nor_cs_2 { | |
| id = "if_nor_cs_2"; | |
| arg = <0x00>; | |
| }; | |
| if_nor_cs_3 { | |
| id = "if_nor_cs_3"; | |
| arg = <0x00>; | |
| }; | |
| if_nor_wp { | |
| id = "if_nor_wp"; | |
| arg = <0x00>; | |
| }; | |
| if_nand_8 { | |
| id = "if_nand_8"; | |
| arg = <0x00>; | |
| linux,phandle = <0x0c>; | |
| phandle = <0x0c>; | |
| }; | |
| if_nand_16 { | |
| id = "if_nand_16"; | |
| arg = <0x00>; | |
| }; | |
| if_nand_cs_0 { | |
| id = "if_nand_cs_0"; | |
| arg = <0x00>; | |
| linux,phandle = <0x0d>; | |
| phandle = <0x0d>; | |
| }; | |
| if_nand_cs_1 { | |
| id = "if_nand_cs_1"; | |
| arg = <0x00>; | |
| }; | |
| if_nand_cs_2 { | |
| id = "if_nand_cs_2"; | |
| arg = <0x00>; | |
| }; | |
| if_nand_cs_3 { | |
| id = "if_nand_cs_3"; | |
| arg = <0x00>; | |
| }; | |
| if_nand_wp { | |
| id = "if_nand_wp"; | |
| arg = <0x00>; | |
| }; | |
| if_sram_8 { | |
| id = "if_sram_8"; | |
| arg = <0x00>; | |
| }; | |
| if_sram_16 { | |
| id = "if_sram_16"; | |
| arg = <0x00>; | |
| }; | |
| if_sram_cs_0 { | |
| id = "if_sram_cs_0"; | |
| arg = <0x00>; | |
| }; | |
| if_sram_cs_1 { | |
| id = "if_sram_cs_1"; | |
| arg = <0x00>; | |
| }; | |
| if_sram_cs_2 { | |
| id = "if_sram_cs_2"; | |
| arg = <0x00>; | |
| }; | |
| if_sram_cs_3 { | |
| id = "if_sram_cs_3"; | |
| arg = <0x00>; | |
| }; | |
| if_sata_0_leds { | |
| id = "if_sata_0_leds"; | |
| arg = <0x00>; | |
| }; | |
| if_sata_1_leds { | |
| id = "if_sata_1_leds"; | |
| arg = <0x00>; | |
| }; | |
| if_eth_0_led { | |
| id = "if_eth_0_led"; | |
| arg = <0x00>; | |
| }; | |
| if_eth_1_led { | |
| id = "if_eth_1_led"; | |
| arg = <0x00>; | |
| }; | |
| if_eth_2_led { | |
| id = "if_eth_2_led"; | |
| arg = <0x00>; | |
| }; | |
| if_eth_3_led { | |
| id = "if_eth_3_led"; | |
| arg = <0x00>; | |
| }; | |
| if_eth_leds { | |
| id = "if_eth_leds"; | |
| arg = <0x00>; | |
| }; | |
| if_eth_gpio { | |
| id = "if_eth_gpio"; | |
| arg = <0x00>; | |
| }; | |
| if_uart_1 { | |
| id = "if_uart_1"; | |
| arg = <0x00>; | |
| linux,phandle = <0x0e>; | |
| phandle = <0x0e>; | |
| }; | |
| if_uart_1_modem { | |
| id = "if_uart_1_modem"; | |
| arg = <0x00>; | |
| }; | |
| if_uart_2 { | |
| id = "if_uart_2"; | |
| arg = <0x00>; | |
| linux,phandle = <0x0f>; | |
| phandle = <0x0f>; | |
| }; | |
| if_uart_3 { | |
| id = "if_uart_3"; | |
| arg = <0x00>; | |
| }; | |
| if_i2c_gen { | |
| id = "if_i2c_gen"; | |
| arg = <0x00>; | |
| }; | |
| if_ulpi_0_rst_n { | |
| id = "if_ulpi_0_rst_n"; | |
| arg = <0x00>; | |
| }; | |
| if_ulpi_1_rst_n { | |
| id = "if_ulpi_1_rst_n"; | |
| arg = <0x00>; | |
| }; | |
| if_pci_ep_int_a { | |
| id = "if_pci_ep_int_a"; | |
| arg = <0x00>; | |
| }; | |
| if_pci_ep_reset_out { | |
| id = "if_pci_ep_reset_out"; | |
| arg = <0x00>; | |
| }; | |
| if_spim_a_ss_1 { | |
| id = "if_spim_a_ss_1"; | |
| arg = <0x00>; | |
| }; | |
| if_spim_a_ss_2 { | |
| id = "if_spim_a_ss_2"; | |
| arg = <0x00>; | |
| }; | |
| if_spim_a_ss_3 { | |
| id = "if_spim_a_ss_3"; | |
| arg = <0x00>; | |
| }; | |
| if_spim_aux { | |
| id = "if_spim_aux"; | |
| arg = <0x00>; | |
| }; | |
| if_ulpi_1_b { | |
| id = "if_ulpi_1_b"; | |
| arg = <0x00>; | |
| }; | |
| if_gpio0 { | |
| id = "if_gpio"; | |
| arg = <0x00>; | |
| }; | |
| if_gpio1 { | |
| id = "if_gpio"; | |
| arg = <0x01>; | |
| }; | |
| if_gpio2 { | |
| id = "if_gpio"; | |
| arg = <0x02>; | |
| }; | |
| if_gpio3 { | |
| id = "if_gpio"; | |
| arg = <0x03>; | |
| }; | |
| if_gpio4 { | |
| id = "if_gpio"; | |
| arg = <0x04>; | |
| }; | |
| if_gpio5 { | |
| id = "if_gpio"; | |
| arg = <0x05>; | |
| }; | |
| if_gpio6 { | |
| id = "if_gpio"; | |
| arg = <0x06>; | |
| }; | |
| if_gpio7 { | |
| id = "if_gpio"; | |
| arg = <0x07>; | |
| }; | |
| if_gpio8 { | |
| id = "if_gpio"; | |
| arg = <0x08>; | |
| }; | |
| if_gpio9 { | |
| id = "if_gpio"; | |
| arg = <0x09>; | |
| }; | |
| if_gpio10 { | |
| id = "if_gpio"; | |
| arg = <0x0a>; | |
| }; | |
| if_gpio11 { | |
| id = "if_gpio"; | |
| arg = <0x0b>; | |
| }; | |
| if_gpio12 { | |
| id = "if_gpio"; | |
| arg = <0x0c>; | |
| }; | |
| if_gpio13 { | |
| id = "if_gpio"; | |
| arg = <0x0d>; | |
| }; | |
| if_gpio14 { | |
| id = "if_gpio"; | |
| arg = <0x0e>; | |
| }; | |
| if_gpio15 { | |
| id = "if_gpio"; | |
| arg = <0x0f>; | |
| }; | |
| if_gpio16 { | |
| id = "if_gpio"; | |
| arg = <0x10>; | |
| }; | |
| if_gpio17 { | |
| id = "if_gpio"; | |
| arg = <0x11>; | |
| }; | |
| if_gpio18 { | |
| id = "if_gpio"; | |
| arg = <0x12>; | |
| }; | |
| if_gpio19 { | |
| id = "if_gpio"; | |
| arg = <0x13>; | |
| }; | |
| if_gpio20 { | |
| id = "if_gpio"; | |
| arg = <0x14>; | |
| }; | |
| if_gpio21 { | |
| id = "if_gpio"; | |
| arg = <0x15>; | |
| }; | |
| if_gpio22 { | |
| id = "if_gpio"; | |
| arg = <0x16>; | |
| }; | |
| if_gpio23 { | |
| id = "if_gpio"; | |
| arg = <0x17>; | |
| }; | |
| if_gpio24 { | |
| id = "if_gpio"; | |
| arg = <0x18>; | |
| }; | |
| if_gpio25 { | |
| id = "if_gpio"; | |
| arg = <0x19>; | |
| }; | |
| if_gpio26 { | |
| id = "if_gpio"; | |
| arg = <0x1a>; | |
| }; | |
| if_gpio27 { | |
| id = "if_gpio"; | |
| arg = <0x1b>; | |
| }; | |
| if_gpio28 { | |
| id = "if_gpio"; | |
| arg = <0x1c>; | |
| }; | |
| if_gpio29 { | |
| id = "if_gpio"; | |
| arg = <0x1d>; | |
| }; | |
| if_gpio30 { | |
| id = "if_gpio"; | |
| arg = <0x1e>; | |
| }; | |
| if_gpio31 { | |
| id = "if_gpio"; | |
| arg = <0x1f>; | |
| }; | |
| if_gpio32 { | |
| id = "if_gpio"; | |
| arg = <0x20>; | |
| }; | |
| if_gpio33 { | |
| id = "if_gpio"; | |
| arg = <0x21>; | |
| }; | |
| if_gpio34 { | |
| id = "if_gpio"; | |
| arg = <0x22>; | |
| }; | |
| if_gpio35 { | |
| id = "if_gpio"; | |
| arg = <0x23>; | |
| }; | |
| if_gpio36 { | |
| id = "if_gpio"; | |
| arg = <0x24>; | |
| }; | |
| if_gpio37 { | |
| id = "if_gpio"; | |
| arg = <0x25>; | |
| }; | |
| if_gpio38 { | |
| id = "if_gpio"; | |
| arg = <0x26>; | |
| }; | |
| if_gpio39 { | |
| id = "if_gpio"; | |
| arg = <0x27>; | |
| }; | |
| if_gpio40 { | |
| id = "if_gpio"; | |
| arg = <0x28>; | |
| }; | |
| if_gpio41 { | |
| id = "if_gpio"; | |
| arg = <0x29>; | |
| }; | |
| if_gpio42 { | |
| id = "if_gpio"; | |
| arg = <0x2a>; | |
| }; | |
| if_gpio43 { | |
| id = "if_gpio"; | |
| arg = <0x2b>; | |
| }; | |
| if_sgpo_clk { | |
| id = "if_sgpo_clk"; | |
| arg = <0x00>; | |
| }; | |
| if_sgpo_ds_0 { | |
| id = "if_sgpo_ds_0"; | |
| arg = <0x00>; | |
| }; | |
| if_sgpo_ds_1 { | |
| id = "if_sgpo_ds_1"; | |
| arg = <0x00>; | |
| }; | |
| if_sgpo_ds_2 { | |
| id = "if_sgpo_ds_2"; | |
| arg = <0x00>; | |
| }; | |
| if_sgpo_ds_3 { | |
| id = "if_sgpo_ds_3"; | |
| arg = <0x00>; | |
| }; | |
| }; | |
| board-cfg { | |
| id = "alpine_v2_ubnt udc v1.0"; | |
| pinctrl_init { | |
| pinctrl-0 = <0x0c 0x0d 0x0e 0x0f>; | |
| }; | |
| gpio_init { | |
| gpio-list = <0x20 0x01 0x01 0x24 0x01 0x00 0x2b 0x01 0x00>; | |
| }; | |
| sgpo_init { | |
| status = "enabled"; | |
| group_mode = "two"; | |
| sata_mode = "active-presence"; | |
| timing { | |
| clk_setup_time_ns = <0x40>; | |
| update_freq_khz = <0x01>; | |
| clk_freq_mhz = <0x01>; | |
| blink_rate = "normal"; | |
| }; | |
| group0 { | |
| mode_mask = <0xf0>; | |
| init_val = <0xc0>; | |
| invert_mask = <0x00>; | |
| stretch_mask = <0x00>; | |
| blink_mask = <0x00>; | |
| stretch_time_ms = <0x200>; | |
| }; | |
| group1 { | |
| mode_mask = <0x00>; | |
| init_val = <0x00>; | |
| invert_mask = <0x00>; | |
| stretch_mask = <0xff>; | |
| blink_mask = <0xff>; | |
| stretch_time_ms = <0x200>; | |
| }; | |
| group2 { | |
| mode_mask = <0x00>; | |
| init_val = <0x00>; | |
| invert_mask = <0x00>; | |
| stretch_mask = <0x00>; | |
| blink_mask = <0x00>; | |
| stretch_time_ms = <0x200>; | |
| }; | |
| group3 { | |
| mode_mask = <0xff>; | |
| init_val = <0x00>; | |
| invert_mask = <0x00>; | |
| stretch_mask = <0x00>; | |
| blink_mask = <0x00>; | |
| stretch_time_ms = <0x200>; | |
| }; | |
| }; | |
| serdes { | |
| group0 { | |
| interface = "pcie_g2x2_pcie_g2x2"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00 0x01 0x02 0x03>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group1 { | |
| interface = "sata"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00 0x01 0x02 0x03>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group2 { | |
| interface = "pcie_g2x2_pcie_g2x2"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00 0x01 0x02 0x03>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group3 { | |
| interface = "sgmii"; | |
| ref-clock = "156.25Mhz"; | |
| active-lanes = <0x00>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| group4 { | |
| interface = "skip"; | |
| ref-clock = "100Mhz"; | |
| active-lanes = <0x00 0x01>; | |
| inv-tx-lanes; | |
| inv-rx-lanes; | |
| ssc = "disabled"; | |
| lane_0_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_1_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_2_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| lane_3_params { | |
| rx { | |
| override = "disabled"; | |
| }; | |
| tx { | |
| override = "disabled"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ethernet { | |
| port1 { | |
| status = "enabled"; | |
| mode = "rgmii"; | |
| ext_phy { | |
| phy_mgmt_if = "mdc-mdio"; | |
| phy-addr = <0x04>; | |
| mdc-mdio-freq = "1.0Mhz"; | |
| auto-neg-mode = "out-of-band"; | |
| }; | |
| }; | |
| port3 { | |
| status = "enabled"; | |
| mode = "rgmii"; | |
| }; | |
| }; | |
| pcie { | |
| ep-ports; | |
| port0 { | |
| status = "enabled"; | |
| gen = <0x02>; | |
| width = <0x02>; | |
| }; | |
| port1 { | |
| status = "disabled"; | |
| gen = <0x02>; | |
| width = <0x01>; | |
| }; | |
| port2 { | |
| status = "enabled"; | |
| gen = <0x02>; | |
| width = <0x01>; | |
| }; | |
| port3 { | |
| status = "enabled"; | |
| gen = <0x02>; | |
| width = <0x01>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| signature { | |
| key-udc_al324 { | |
| required = "image"; | |
| algo = "sha1,rsa2048"; | |
| rsa,r-squared = <0xafa8db9a 0x29a911e9 0xd23216a2 0x474ef70f 0xeaea25c7 0xef9b5ddf 0x8d3d50c2 0xaaa14ea 0x398e9232 0xb178a75 0xd02d96e7 0x2322a148 0xf0e02fc2 0xbb53e2a6 0x9beb5684 0xc6cedf16 0xb64112 0x343697ff 0x7b82b12a 0x6cf36f4f 0xf1b0218c 0x2e9fb994 0xe83f16eb 0xaf1bdf1c 0x2537cdfe 0xa567ec8b 0xc12202c3 0x41efab03 0x4970dedc 0x7570e457 0x4fec6bb8 0x8a86aa4c 0xc60298fa 0xb173b49a 0x99c3a7be 0x3e411e5d 0x54b4319c 0x216b8ce3 0x51297387 0x7812801b 0x7c8f572c 0x6981d0e2 0xca63b06 0xd79936cc 0xac853383 0xf6f15d94 0x5970c793 0xea15448b 0xb0c1f18a 0xce2b2faa 0x9e2e496d 0xa7d5c345 0xa6348868 0x10032309 0xd0918ea 0x8db9b016 0xc75ae648 0x6809de05 0x995cb04a 0x11c0f2f0 0xe2e851b9 0xbcbb8e46 0xcbaecb86 0xe453fb99>; | |
| rsa,modulus = <0xdf12bb5c 0xa1fd4fc8 0x909bb37d 0xcdcbb04a 0x4c56b4ee 0xe3c00dfa 0xb464acc6 0x4562d981 0xd3b27b5d 0x8d5c7f58 0x68be0b59 0xa948acae 0xcefdbf58 0x5e7cf766 0x3bdbcf58 0x23a0678e 0x6c0d473 0x656371ac 0x75c6c1b 0x48c438a0 0x53139e0c 0xc6c2545b 0x5dc415a2 0x14a8cfe7 0xd0a13d86 0x855681b2 0x934a7a5 0xab0c8b75 0xed4c597 0xf24235ac 0xd1c706e6 0x89a501fb 0x33ce40f2 0x446e5ccb 0xcd30219d 0x662d1563 0x8cf34cbf 0xcdbddc5d 0xefac773 0xce92072f 0xb96ae3d7 0x6449038 0x6e4906f7 0x45a1b628 0xdde17f5c 0x6bd15cc4 0x904b4ca0 0x5a188b97 0xade049c0 0x2735b10 0xb37bc807 0x735189c4 0x72f1ccba 0x9c59889b 0xe5404c4b 0xf3c6e133 0x9e900605 0x626f7695 0x3ae05da 0xcbfadd28 0x6a2142fa 0x67f9f90d 0xd9aaa1c5 0xd1bfa0e9>; | |
| rsa,exponent = <0x00 0x10001>; | |
| rsa,n0-inverse = <0x9708c8a7>; | |
| rsa,num-bits = <0x800>; | |
| key-name-hint = "udc_al324"; | |
| }; | |
| }; | |
| hypervisor { | |
| }; | |
| gpio_keys { | |
| compatible = "gpio-keys"; | |
| reset { | |
| label = "reset"; | |
| linux,code = <0x198>; | |
| gpios = <0x10 0x07 0x01>; | |
| debounce-interval = <0xc8>; | |
| }; | |
| }; | |
| }; |
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