OpenOCD STM32H7B0 ExtQSPI Memory

openocd.cfg

source [find interface/cmsis-dap.cfg]
transport select swd
set CHIPNAME stm32h7b0xx

if {![info exists OCTOSPI1]} {
	set OCTOSPI1 1
	set OCTOSPI2 0
}

source [find target/stm32h7x.cfg]

proc octospi_init { octo } {
	global a b
	mww 0x580244E0 0x000007FF				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
	mww 0x580244D4 0x01E95031				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
	mww 0x580244B0 0x00002000               ;# LL_CKGA_Enable(LL_CKGA_PERIPH_OCTOSPI1)
    sleep 1									;# Wait for clock startup

	mww 0x5200B404 0x00010101				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2

    # PB6 NCS(AF10), PB2 CLK(AF9)
    mww 0x58020400 0x00002020
    mww 0x58020408 0x00003030
    mww 0x5802040C 0x00000000
    mww 0x58020420 0x0A000900
    # PD11/12/13 IO0/1/3 (AF9)
    mww 0x58020C00 0x0A800000
    mww 0x58020C08 0x0FC00000
    mww 0x58020C0C 0x00000000
    mww 0x58020C24 0x00999000
    # PE2 IO2 (AF9)
    mww 0x58021000 0x00000020
    mww 0x58021008 0x00000030
    mww 0x5802100C 0x00000000
    mww 0x58021020 0x00000900

	mww 0x52005130 0x00001000

	mww 0x52005000 0x30401f01
	mww 0x52005008 0x00160709
	mww 0x5200500C 0x0000000f

	mww 0x52005108 0x40000008
    mww 0x52005100 0x01002101
    mww 0x52005110 0x0000000B

	sleep 1

	flash probe 1

    stmqspi cmd 1 3 0x9f

    stmqspi cmd 1 0 0x06
    stmqspi cmd 1 0 0x01 0x00 0x02 
    sleep 1
}

$_CHIPNAME.cpu0 configure -event reset-init {
	global OCTOSPI1
	global OCTOSPI2

	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for  64MHZ HCLK

	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
	mww 0x58024418 0x00000040				;# RCC_CDCFGR1: CDCPRE=1, CDPPRE=2, HPRE=1
	mww 0x5802441C 0x00000440				;# RCC_CDCFGR2: CDPPRE2=2, CDPPRE1=2
	mww 0x58024420 0x00000040				;# RCC_SRDCFGR: SRDPPRE=2
	mww 0x58024428 0x00404040				;# RCC_PLLCKSELR: DIVM3=4, DIVM2=4, DIVM1=4, PLLSRC=HSI
	mww 0x5802442C 0x01ff0ccc				;# RCC_PLLCFGR: PLLxRGE=8MHz to 16MHz, PLLxVCOSEL=wide
	mww 0x58024430 0x01010207				;# RCC_PLL1DIVR: 64MHz: DIVR1=2, DIVQ1=2, DIVP1=2, DIVN1=8
	mww 0x58024438 0x01010207				;# RCC_PLL2DIVR: 64MHz: DIVR2=2, DIVQ2=2, DIVP2=2, DIVN2=8
	mww 0x58024440 0x01010207				;# RCC_PLL3DIVR: 64MHz: DIVR3=2, DIVQ3=2, DIVP3=2, DIVN3=8
	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
	sleep 1
	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
	sleep 1

	adapter speed 1000

	octospi_init 0
}

reset_config none separate