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Name                                                                                             Version                 ProviderName
----                                                                                             -------                 ------------
Windows 驱动程序包 - FTDI CDM Driver Package - VCP Driver (08/16/2017 2.12.28)                        08/16/2017 2.12.28      Programs    
Windows Driver Package - NXP HIDClass  (11/03/2014 1.0.0.1)                                      11/03/2014 1.0.0.1      Programs    
Windows Driver Package - Philips (NXP) (DFU) USB  (03/11/2010 3.12.0.0)                          03/11/2010 3.12.0.0     Programs    
Windows 驱动程序包 - Arduino USBDevice  (03/03/2020 10.48.00.000)                                     03/03/2020 10.48.00.000 Programs    
Windows 驱动程序包 - SEGGER (JLinkCDC) Ports  (06/06/2019 1.34.0.44950)                               06/06/2019 1.34.0.44950 Programs    
Windows 驱动程序包 - IAR Systems (IJET) IARUSB  (05/23/2012 2.05)                         

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MFXSTM32L152 寄存器映射表

内容可能存在问题,对此不负责.

通用寄存器

寄存器名称	地址 (十六进制)	描述	访问类型
MFXSTM32L152_REG_ADR_ID	0x00	芯片ID	只读 (R)
MFXSTM32L152_REG_ADR_FW_VERSION_MSB	0x01	芯片固件版本高字节	只读 (R)

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diff --git a/arch/arm/dts/imx6dl-riotboard.dts b/arch/arm/dts/imx6dl-riotboard.dts
index e7d9bfbfd0e..e09dc6e410f 100644
--- a/arch/arm/dts/imx6dl-riotboard.dts
+++ b/arch/arm/dts/imx6dl-riotboard.dts
@@ -176,7 +176,7 @@
 		VDDIO-supply = <&reg_3p3v>;
 	};
 
-	pmic: pf0100@8 {
+	pmic: pfuze100@8 {

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module rtl_bram(
    input  wire       clk,
    
    (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
    input  wire       rst,

    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
    input  wire [31:0] s_axil_awaddr,
    (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
    input  wire [2:0]  s_axil_awprot,

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module top(
	input [31:0] adr,
	input [31:0] dat_w,
	output reg [31:0] dat_r,
	input [3:0] sel,
	input cyc,
	input stb,
	output reg ack,
	input we,
	input [2:0] cti,

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module top(
    input wire clk_i,
    input wire rst_i,

    input wire sdi_csn_i,
    input wire sdi_clk_i,
    input wire sdi_dat_i,
    output wire sdi_dat_o,
    
    output wire [5:0] led

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module bram_axil(
    input  wire       clk,
    input  wire       rst,

    input  wire [31:0]  s_axil_awaddr,
    input  wire [2:0]  s_axil_awprot,
    input  wire        s_axil_awvaild,
    output wire        s_axil_awready,
    input  wire [31:0] s_axil_wdata,
    input  wire [3:0]  s_axil_wstrb,

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/01/08 18:22:57
// Design Name: 
// Module Name: ser_10to1
// Project Name: 
// Target Devices: