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February 16, 2015 13:36
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Intel Wi-Fi AC3160 pci register dump on NetBSD
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| PCI configuration registers: | |
| Common header: | |
| 0x00: 0x08b38086 0x00100006 0x02800083 0x00000010 | |
| Vendor Name: Intel (0x8086) | |
| Device Name: Dual Band Wireless AC 3160 (0x08b3) | |
| Command register: 0x0006 | |
| I/O space accesses: off | |
| Memory space accesses: on | |
| Bus mastering: on | |
| Special cycles: off | |
| MWI transactions: off | |
| Palette snooping: off | |
| Parity error checking: off | |
| Address/data stepping: off | |
| System error (SERR): off | |
| Fast back-to-back transactions: off | |
| Interrupt disable: off | |
| Status register: 0x0010 | |
| Interrupt status: inactive | |
| Capability List support: on | |
| 66 MHz capable: off | |
| User Definable Features (UDF) support: off | |
| Fast back-to-back capable: off | |
| Data parity error detected: off | |
| DEVSEL timing: fast (0x0) | |
| Slave signaled Target Abort: off | |
| Master received Target Abort: off | |
| Master received Master Abort: off | |
| Asserted System Error (SERR): off | |
| Parity error detected: off | |
| Class Name: network (0x02) | |
| Subclass Name: miscellaneous (0x80) | |
| Interface: 0x00 | |
| Revision ID: 0x83 | |
| BIST: 0x00 | |
| Header Type: 0x00 (0x00) | |
| Latency Timer: 0x00 | |
| Cache Line Size: 64bytes (0x10) | |
| Type 0 ("normal" device) header: | |
| 0x10: 0xf7d00004 0x00000000 0x00000000 0x00000000 | |
| 0x20: 0x00000000 0x00000000 0x00000000 0x81708086 | |
| 0x30: 0x00000000 0x000000c8 0x00000000 0x00000103 | |
| Base address register at 0x10 | |
| type: 64-bit nonprefetchable memory | |
| base: 0x00000000f7d00000, not sized | |
| Base address register at 0x18 | |
| not implemented(?) | |
| Base address register at 0x1c | |
| not implemented(?) | |
| Base address register at 0x20 | |
| not implemented(?) | |
| Base address register at 0x24 | |
| not implemented(?) | |
| Cardbus CIS Pointer: 0x00000000 | |
| Subsystem vendor ID: 0x8086 | |
| Subsystem ID: 0x8170 | |
| Expansion ROM Base Address: 0x00000000 | |
| Capability list pointer: 0xc8 | |
| Reserved @ 0x38: 0x00000000 | |
| Maximum Latency: 0x00 | |
| Minimum Grant: 0x00 | |
| Interrupt pin: 0x01 (pin A) | |
| Interrupt line: 0x03 | |
| Capability register at 0xc8 | |
| type: 0x01 (Power Management) | |
| Capability register at 0xd0 | |
| type: 0x05 (MSI) | |
| Capability register at 0x40 | |
| type: 0x10 (PCI Express) | |
| PCI Power Management Capabilities Register | |
| Capabilities register: 0xc823 | |
| Version: 1.2 | |
| PME# clock: off | |
| Device specific initialization: on | |
| 3.3V auxiliary current: self-powered | |
| D1 power management state support: off | |
| D2 power management state support: off | |
| PME# support D0: on | |
| PME# support D1: off | |
| PME# support D2: off | |
| PME# support D3 hot: on | |
| PME# support D3 cold: on | |
| Control/status register: 0x0000 | |
| Power state: D0 | |
| PCI Express reserved: off | |
| No soft reset: off | |
| PME# assertion: disabled | |
| PME# status: off | |
| Bridge Support Extensions register: 0x00 | |
| B2/B3 support: off | |
| Bus Power/Clock Control Enable: off | |
| Data register: 0x0d | |
| PCI Message Signaled Interrupt | |
| Message Control register: 0x0080 | |
| MSI Enabled: off | |
| Multiple Message Capable: no (1 vector) | |
| Multiple Message Enabled: off (1 vector) | |
| 64 Bit Address Capable: on | |
| Per-Vector Masking Capable: off | |
| Message Address (lower) register: 0x00000000 | |
| Message Address (upper) register: 0x00000000 | |
| Message Data register: 0x00000000 | |
| PCI Express Capabilities Register | |
| Capability register: 0002 | |
| Capability version: 2 | |
| Device type: PCI Express Endpoint device | |
| Slot implemented: off | |
| Interrupt Message Number: 0 | |
| Device Capabilities Register: 0x10008ec0 | |
| Max Payload Size Supported: 128 bytes max | |
| Phantom Functions Supported: not available | |
| Extended Tag Field Supported: 5bit | |
| Endpoint L0 Acceptable Latency: 256ns to less than 512ns | |
| Endpoint L1 Acceptable Latency: More than 64us | |
| Attention Button Present: off | |
| Attention Indicator Present: off | |
| Power Indicator Present: off | |
| Role-Based Error Report: on | |
| Captured Slot Power Limit Value: 0 | |
| Captured Slot Power Limit Scale: 0 | |
| Function-Level Reset Capability: on | |
| Device Control Register: 0x0c00 | |
| Correctable Error Reporting Enable: off | |
| Non Fatal Error Reporting Enable: off | |
| Fatal Error Reporting Enable: off | |
| Unsupported Request Reporting Enable: off | |
| Enable Relaxed Ordering: off | |
| Max Payload Size: 128 byte | |
| Extended Tag Field Enable: off | |
| Phantom Functions Enable: off | |
| Aux Power PM Enable: on | |
| Enable No Snoop: on | |
| Max Read Request Size: 128 byte | |
| Device Status Register: 0x0019 | |
| Correctable Error Detected: on | |
| Non Fatal Error Detected: off | |
| Fatal Error Detected: off | |
| Unsupported Request Detected: on | |
| Aux Power Detected: on | |
| Transaction Pending: off | |
| Link Capabilities Register: 0x0006ec11 | |
| Maximum Link Speed: 2.5GT/s | |
| Maximum Link Width: x1 lanes | |
| Active State PM Support: L0s and L1 supported | |
| L0 Exit Latency: 2us - 4us | |
| L1 Exit Latency: 16us to less than 32us | |
| Port Number: 0 | |
| Clock Power Management: on | |
| Surprise Down Error Report: off | |
| Data Link Layer Link Active: off | |
| Link BW Notification Capable: off | |
| ASPM Optionally Compliance: off | |
| Link Control Register: 0x0142 | |
| Active State PM Control: L1 Entry Enabled | |
| Read Completion Boundary Control: 64bytes | |
| Link Disable: off | |
| Retrain Link: off | |
| Common Clock Configuration: on | |
| Extended Synch: off | |
| Enable Clock Power Management: on | |
| Hardware Autonomous Width Disable: off | |
| Link Bandwidth Management Interrupt Enable: off | |
| Link Autonomous Bandwidth Interrupt Enable: off | |
| Link Status Register: 0x1011 | |
| Negotiated Link Speed: 2.5GT/s | |
| Negotiated Link Width: x1 lanes | |
| Training Error: off | |
| Link Training: off | |
| Slot Clock Configuration: on | |
| Data Link Layer Link Active: off | |
| Link Bandwidth Management Status: off | |
| Link Autonomous Bandwidth Status: off | |
| Device Capabilities 2: 0x00080812 | |
| Completion Timeout Ranges Supported: 2 | |
| Completion Timeout Disable Supported: on | |
| ARI Forwarding Supported: off | |
| AtomicOp Routing Supported: off | |
| 32bit AtomicOp Completer Supported: off | |
| 64bit AtomicOp Completer Supported: off | |
| 128-bit CAS Completer Supported: off | |
| No RO-enabled PR-PR passing: off | |
| LTR Mechanism Supported: on | |
| TPH Completer Supported: 0 | |
| OBFF Supported: WAKE# only | |
| Extended Fmt Field Supported: off | |
| End-End TLP Prefix Supported: off | |
| Max End-End TLP Prefixes: 0 | |
| Device Control 2: 0x0405 | |
| Completion Timeout Value: 16ms to 55ms | |
| Completion Timeout Disabled: off | |
| ARI Forwarding Enabled: off | |
| AtomicOp Rquester Enabled: off | |
| AtomicOp Egress Blocking: off | |
| IDO Request Enabled: off | |
| IDO Completion Enabled: off | |
| LTR Mechanism Enabled: on | |
| OBFF: Disabled | |
| End-End TLP Prefix Blocking on: off | |
| Link Capabilities 2: 0x00000000 | |
| Supported Link Speed Vector: | |
| Crosslink Supported: off | |
| Link Control 2: 0x0001 | |
| Target Link Speed: 2.5GT/s | |
| Enter Compliance Enabled: off | |
| HW Autonomous Speed Disabled: off | |
| Selectable De-emphasis: off | |
| Transmit Margin: 0 | |
| Enter Modified Compliance: off | |
| Compliance SOS: off | |
| Compliance Present/De-emphasis: 0 | |
| Link Status 2: 0x0001 | |
| Current De-emphasis Level: on | |
| Equalization Complete: off | |
| Equalization Phase 1 Successful: off | |
| Equalization Phase 2 Successful: off | |
| Equalization Phase 3 Successful: off | |
| Link Equalization Request: off | |
| Device-dependent header: | |
| 0x40: 0x00020010 0x10008ec0 0x00190c00 0x0006ec11 | |
| 0x50: 0x10110142 0x00000000 0x00000000 0x00000000 | |
| 0x60: 0x00000000 0x00080812 0x00000405 0x00000000 | |
| 0x70: 0x00010001 0x00000000 0x00000000 0x00000000 | |
| 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 | |
| 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 | |
| 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 | |
| 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 | |
| 0xc0: 0x00000000 0x00000000 0xc823d001 0x0d000000 | |
| 0xd0: 0x00804005 0x00000000 0x00000000 0x00000000 | |
| 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 | |
| 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 |
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