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nraynaud/registers.ads

Created October 11, 2014 09:38
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started reworking Adacore's modeling of registers in STM32F4
Raw
registers.ads
--------------------------------------------------------------------
---
-----------
-- --
-- GNAT EXAMPLE --
-- --
-- Copyright (C) 2014, Free Software Foundation, Inc. --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- --
-- --
-- --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNAT was originally developed by the GNAT team at New York University. --
-- Extensive contributions were provided by Ada Core Technologies Inc. --
-- --
------------------------------------------------------------------------------
-- This file provides register declarations for those actually used by this
-- demonstration, for the STM32F4 (ARM Cortex M4F) microcontrollers from
-- ST Microelectronics.
with System;
with STM32F4; use STM32F4;
with STM32F4.GPIO;
with STM32F4.Reset_Clock_Control; use STM32F4.Reset_Clock_Control;
with STM32F4.SYSCONFIG_Control; use STM32F4.SYSCONFIG_Control;
with STM32F4.TIM;
package Registers is
pragma Warnings (Off, "*may call Last_Chance_Handler");
pragma Warnings (Off, "*may be incompatible with alignment of object");
RCC : RCC_Register with
Volatile,
Address => System'To_Address (RCC_Base);
package GPIOA is new STM32F4.GPIO(Address => GPIOA_Base, RCCBit=>0, MODER_Reset =>16#A800_0000#);
package GPIOB is new STM32F4.GPIO(Address => GPIOB_Base, RCCBit=>1, MODER_Reset =>16#0000_0280#);
package GPIOD is new STM32F4.GPIO(Address => GPIOD_Base, RCCBit=>3);
package GPIOE is new STM32F4.GPIO(Address => GPIOE_Base, RCCBit=>4);
package TIM1 is new STM32F4.TIM(
Register_Base => TIM1_Base,
RCC_RESET_REGISTER_Base => APB2RSTR_Base,
RCC_ENABLE_REGISTER_Base => APB2ENR_Base,
RCC_LOWPOW_REGISTER_Base => APB2LPENR_Base,
RCCBit => 0);
EXTI : EXTI_Register with
Volatile,
Address => System'To_Address (EXTI_Base);
pragma Import (Ada, EXTI);
SYSCFG : SYSCFG_Register with
Volatile,
Address => System'To_Address (SYSCFG_Base);
pragma Import (Ada, SYSCFG);
pragma Warnings (On, "*may call Last_Chance_Handler");
pragma Warnings (On, "*may be incompatible with alignment of object");
end Registers;
Raw
stm32f4-busses.ads
pragma Restrictions (No_Elaboration_Code);
package STM32F4.Busses is
type AHB1_type is record
GPIOA : Boolean;
GPIOB : Boolean;
GPIOC : Boolean;
GPIOD : Boolean;
GPIOE : Boolean;
GPIOF : Boolean;
GPIOG : Boolean;
GPIOH : Boolean;
GPIOI : Boolean;
CRC : Boolean;
FLITF : Boolean;-- enabled by default
SRAM1 : Boolean;-- enabled by default
SRAM2 : Boolean;-- enabled by default
BKPSRAM : Boolean;
CCMDATARAM : Boolean; --not for reset
DMA1 : Boolean;
DMA2 : Boolean;
ETHMAC : Boolean;
ETHMACTX : Boolean; --not for reset
ETHMACRX : Boolean; --not for reset
ETHMACPTP : Boolean; --not for reset
OTGHS : Boolean;
OTGHSULPI : Boolean;
end record with Size => 32;
for AHB1_type use record
GPIOA at 0 range 0 .. 0;
GPIOB at 0 range 1 .. 1;
GPIOC at 0 range 2 .. 2;
GPIOD at 0 range 3 .. 3;
GPIOE at 0 range 4 .. 4;
GPIOF at 0 range 5 .. 5;
GPIOG at 0 range 6 .. 6;
GPIOH at 0 range 7 .. 7;
GPIOI at 0 range 8 .. 8;
CRC at 0 range 12 .. 12;
FLITF at 0 range 15 .. 15;
SRAM1 at 0 range 16 .. 16;
SRAM2 at 0 range 17 .. 17;
BKPSRAM at 0 range 18 .. 18;
CCMDATARAM at 0 range 20 .. 20;
DMA1 at 0 range 21 .. 21;
DMA2 at 0 range 22 .. 22;
ETHMAC at 0 range 25 .. 25;
ETHMACTX at 0 range 26 .. 26;
ETHMACRX at 0 range 27 .. 27;
ETHMACPTP at 0 range 28 .. 28;
OTGHS at 0 range 29 .. 29;
OTGHSULPI at 0 range 30 .. 30;
end record ;
type AHB2_type is record
DCMI : Boolean;
CRYPT : Boolean;
HASH : Boolean;
RNG : Boolean;
OTGFS : Boolean;
end record with Size => 32;
for AHB2_type use record
DCMI at 0 range 0 .. 0;
CRYPT at 0 range 4 .. 4;
HASH at 0 range 5 .. 5;
RNG at 0 range 6 .. 6;
OTGFS at 0 range 7 .. 7;
end record;
type APB2_type is record
TIM1: Boolean;
TIM8: Boolean;
USART1: Boolean;
USART6: Boolean;
ADC1: Boolean;
ADC2: Boolean;
ADC3: Boolean;
SDIO: Boolean;
SPI1: Boolean;
SYSCFG: Boolean;
TIM9: Boolean;
TIM10: Boolean;
TIM11: Boolean;
end record with Size =>32;
for APB2_type use record
TIM1 at 0 range 0 .. 0;
TIM8 at 0 range 1 .. 1;
USART1 at 0 range 4 .. 4;
USART6 at 0 range 5 .. 5;
ADC1 at 0 range 8 .. 8;--reset all the ADCs
ADC2 at 0 range 9 .. 9;
ADC3 at 0 range 10 .. 10;
SDIO at 0 range 11 .. 11;
SPI1 at 0 range 12 .. 12;
SYSCFG at 0 range 14 .. 14;
TIM9 at 0 range 16 .. 16;
TIM10 at 0 range 17 .. 17;
TIM11 at 0 range 18 .. 18;
end record;
end STM32F4.Busses;
Raw
stm32f4-genericperipheral.ads
with System;
with STM32F4; use STM32F4;
generic
RCC_ENABLE_REGISTER_Base : Natural;
RCC_RESET_REGISTER_Base : Natural;
RCC_LOWPOW_REGISTER_Base : Natural;
RCCBit : Natural;
package STM32F4.GenericPeripheral is
RCC_ENABLE : Boolean with Atomic,
Address => System'To_Address (Peripheral_Alias_Base+ (RCC_ENABLE_REGISTER_Base - Peripheral_Base)*32 + RCCBit*4);
RCC_RESET : Boolean with Atomic,
Address => System'To_Address (Peripheral_Alias_Base+ (RCC_RESET_REGISTER_Base - Peripheral_Base)*32 + RCCBit*4);
RCC_LOWPOWER : Boolean with Atomic,
Address => System'To_Address (Peripheral_Alias_Base+ (RCC_LOWPOW_REGISTER_Base - Peripheral_Base)*32 + RCCBit*4);
end STM32F4.GenericPeripheral;
Raw
stm32f4-gpio.ads
------------------------------------------------
--------------
------
----------------
-- --
-- GNAT EXAMPLE --
-- --
-- Copyright (C) 2014, Free Software Foundation, Inc. --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- --
-- --
-- --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNAT was originally developed by the GNAT team at New York University. --
-- Extensive contributions were provided by Ada Core Technologies Inc. --
-- --
------------------------------------------------------------------------------
-- This file provides register definitions for the STM32F4 (ARM Cortex M4F)
-- microcontrollers from ST Microelectronics.
pragma Restrictions (No_Elaboration_Code);
with System;
with Ada.Unchecked_Conversion;
with STM32F4.GenericPeripheral;
generic
Address : Natural;
RCCBit : Natural;
MODER_Reset : Word := 16#0000_0000#;
package STM32F4.GPIO is
package peripheral is new STM32F4.GenericPeripheral (
RCC_RESET_REGISTER_Base => AHB1RSTR_Base,
RCC_ENABLE_REGISTER_Base => AHB1ENR_Base,
RCC_LOWPOW_REGISTER_Base => AHB1LPENR_Base,
RCCBit => RCCBit);
-- MODER constants
type ModeType is (Input, Output, Alternate, Analog);
for ModeType use (Input => 0, Output => 1, Alternate => 2, Analog => 3);
type MODER_type is array (0 .. 15) of ModeType with Pack, Size => 32;
-- OTYPER constants
type OutputType is (PushPull, OpenDrain);
for OutputType use (PushPull => 0, OpenDrain => 1);
type OTYPER_type is array (0 .. 15) of OutputType with Pack, Size => 16;
-- OSPEEDR constants
type SpeedType is (S2MHz,S25MHz,S50MHz, S100MHz);
for SpeedType use (S2MHz=>0,S25MHz=>1,S50MHz=>2, S100MHz=>3);
type OSPEEDR_type is array(0..15) of SpeedType with Pack, Size => 32;
-- PUPDR constants
type PullType is (No_Pull, Pull_Up, Pull_Down);
for PullType use (No_Pull=>0, Pull_Up=>1, Pull_Down =>2);
type PUPDR_type is array(0..15) of PullType with Pack, Size => 32;
-- AFL constants
AF_USART1 : constant Bits_4 := 7;
type GPIO_Register is record
MODER : MODER_type; -- mode register
OTYPER : OTYPER_type; -- output type register
OSPEEDR : OSPEEDR_type; -- output speed register
PUPDR : PUPDR_type; -- pull-up/pull-down register
IDR : Word; -- input data register
ODR : Word; -- output data register
BSRR : Word; -- bit set/reset register
LCKR : Word; -- configuration lock register
AFRL : Bits_8x4; -- alternate function low register
AFRH : Bits_8x4; -- alternate function high register
end record;
for GPIO_Register use record
MODER at 0 range 0 .. 31;
OTYPER at 4 range 0 .. 15;
OSPEEDR at 8 range 0 .. 31;
PUPDR at 12 range 0 .. 31;
IDR at 16 range 0 .. 31;
ODR at 20 range 0 .. 31;
BSRR at 24 range 0 .. 31;
LCKR at 28 range 0 .. 31;
AFRL at 32 range 0 .. 31;
AFRH at 36 range 0 .. 31;
end record;
Device : GPIO_Register with Volatile, Address => System'To_Address (Address);
RCC_ENABLE_addr : constant Natural :=Peripheral_Alias_Base + (AHB1ENR_Base - Peripheral_Base)*32 + RCCBit*4;
RCC_ENABLE : Boolean with Atomic , Address => System'To_Address (RCC_ENABLE_addr);
MODERResetValue : constant MODER_type;
private
function As_MODER_Reset is new Ada.Unchecked_Conversion ( Source => Word, Target => MODER_type);
MODERResetValue : constant MODER_type := As_MODER_Reset(MODER_Reset);
end STM32F4.GPIO;
Raw
stm32f4-reset_clock_control.ads
------------------------------------------------------------
----
------------------
-- --
-- GNAT EXAMPLE --
-- --
-- Copyright (C) 2014, Free Software Foundation, Inc. --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- --
-- --
-- --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNAT was originally developed by the GNAT team at New York University. --
-- Extensive contributions were provided by Ada Core Technologies Inc. --
-- --
------------------------------------------------------------------------------
-- This file provides register definitions for the STM32F4 (ARM Cortex M4F)
-- microcontrollers from ST Microelectronics.
pragma Restrictions (No_Elaboration_Code);
with STM32F4.Busses; use STM32F4.Busses;
package STM32F4.Reset_Clock_Control is
type RCC_Register is record
CR : Word; -- RCC clock control register at 16#00#
PLLCFGR : Word; -- RCC PLL configuration register at 16#04#
CFGR : Word; -- RCC clock configuration register at 16#08#
CIR : Word; -- RCC clock interrupt register at 16#0C#
AHB1RSTR : AHB1_type; -- RCC AHB1 peripheral reset register at
--16#10#
AHB2RSTR : AHB2_type; -- RCC AHB2 peripheral reset register at 16#14#
AHB3RSTR : Word; -- RCC AHB3 peripheral reset register at 16#18#
Reserved_0: Word; -- Reserved at 16#1C#
APB1RSTR : Word; -- RCC APB1 peripheral reset register at 16#20#
APB2RSTR : APB2_type; -- RCC APB2 peripheral reset register at 16#24#
Reserved_1: Word; -- Reserved at 16#28#
Reserved_2: Word; -- Reserved at 16#2c#
AHB1ENR : AHB1_type; -- RCC AHB1 peripheral clock register at
--16#30#
AHB2ENR : AHB2_type; -- RCC AHB2 peripheral clock register at 16#34#
AHB3ENR : Word; -- RCC AHB3 peripheral clock register at 16#38#
Reserved_3: Word; -- Reserved at 16#0C#
APB1ENR : Word; -- RCC APB1 peripheral clock enable at 16#40#
APB2ENR : APB2_type; -- RCC APB2 peripheral clock enable at 16#44#
Reserved_4: Word; -- Reserved at 16#48#
Reserved_5: Word; -- Reserved at 16#4c#
AHB1LPENR: AHB1_type; -- RCC AHB1 periph. low power clk en. at
--16#50#
AHB2LPENR: AHB2_type; -- RCC AHB2 periph. low power clk en. at 16#54#
AHB3LPENR: Word; -- RCC AHB3 periph. low power clk en. at 16#58#
Reserved_6: Word; -- Reserved, 16#5C#
APB1LPENR: Word; -- RCC APB1 periph. low power clk en. at 16#60#
APB2LPENR: APB2_type; -- RCC APB2 periph. low power clk en. at 16#64#
Reserved_7: Word; -- Reserved at 16#68#
Reserved_8: Word; -- Reserved at 16#6C#
BDCR : Word; -- RCC Backup domain control register at 16#70#
CSR : Word; -- RCC clock control/status register at 16#74#
Reserved_9: Word; -- Reserved at 16#78#
Reserved_10: Word; -- Reserved at 16#7C#
SSCGR : Word; -- RCC spread spectrum clk gen. reg. at 16#80#
PLLI2SCFGR: Word; -- RCC PLLI2S configuration register at 16#84#
end record;
for RCC_Register use record
CR at 0 range 0 .. 31;
PLLCFGR at 4 range 0 .. 31;
CFGR at 8 range 0 .. 31;
CIR at 12 range 0 .. 31;
AHB1RSTR at 16 range 0 .. 31;
AHB2RSTR at 20 range 0 .. 31;
AHB3RSTR at 24 range 0 .. 31;
Reserved_0 at 28 range 0 .. 31;
APB1RSTR at 32 range 0 .. 31;
APB2RSTR at 36 range 0 .. 31;
Reserved_1 at 40 range 0 .. 31;
Reserved_2 at 44 range 0 .. 31;
AHB1ENR at 48 range 0 .. 31;
AHB2ENR at 52 range 0 .. 31;
AHB3ENR at 56 range 0 .. 31;
Reserved_3 at 60 range 0 .. 31;
APB1ENR at 64 range 0 .. 31;
APB2ENR at 68 range 0 .. 31;
Reserved_4 at 72 range 0 .. 31;
Reserved_5 at 76 range 0 .. 31;
AHB1LPENR at 80 range 0 .. 31;
AHB2LPENR at 84 range 0 .. 31;
AHB3LPENR at 88 range 0 .. 31;
Reserved_6 at 92 range 0 .. 31;
APB1LPENR at 96 range 0 .. 31;
APB2LPENR at 100 range 0 .. 31;
Reserved_7 at 104 range 0 .. 31;
Reserved_8 at 108 range 0 .. 31;
BDCR at 112 range 0 .. 31;
CSR at 116 range 0 .. 31;
Reserved_9 at 120 range 0 .. 31;
Reserved_10 at 124 range 0 .. 31;
SSCGR at 128 range 0 .. 31;
PLLI2SCFGR at 132 range 0 .. 31;
end record;
-- Constants for RCC CR register
HSION : constant Word := 2 ** 0; -- Internal high-speed clock enable
HSIRDY : constant Word := 2 ** 1; -- Internal high-speed clock ready
HSEON : constant Word := 2 ** 16; -- External high-speed clock enable
HSERDY : constant Word := 2 ** 17; -- External high-speed clock ready
HSEBYP : constant Word := 2 ** 18; -- External HS clk. resonator bypass
CSSON : constant Word := 2 ** 19; -- Clock security system enable
PLLON : constant Word := 2 ** 24; -- Main PLL enable
PLLRDY : constant Word := 2 ** 25; -- Main PLL ready
PLLI2SON : constant Word := 2 ** 26; -- Main PLL enable
PLLI2SRDY : constant Word := 2 ** 27; -- Main PLL ready
PLLSRC_HSE : constant := 2 ** 22; -- PLL source clock is HSE
-- Constants for RCC CFGR register
-- AHB prescaler
HPRE_DIV1 : constant Word := 16#00#; -- AHB is SYSCLK
HPRE_DIV2 : constant Word := 16#80#; -- AHB is SYSCLK / 2
HPRE_DIV4 : constant Word := 16#90#; -- AHB is SYSCLK / 4
HPRE_DIV8 : constant Word := 16#A0#; -- AHB is SYSCLK / 8
HPRE_DIV16 : constant Word := 16#B0#; -- AHB is SYSCLK / 16
HPRE_DIV64 : constant Word := 16#C0#; -- AHB is SYSCLK / 64
HPRE_DIV128 : constant Word := 16#D0#; -- AHB is SYSCLK / 128
HPRE_DIV256 : constant Word := 16#E0#; -- AHB is SYSCLK / 256
HPRE_DIV512 : constant Word := 16#F0#; -- AHB is SYSCLK / 512
-- APB1 prescaler
PPRE1_DIV1 : constant Word := 16#0000#; -- APB1 is HCLK / 1
PPRE1_DIV2 : constant Word := 16#1000#; -- APB1 is HCLK / 2
PPRE1_DIV4 : constant Word := 16#1400#; -- APB1 is HCLK / 4
PPRE1_DIV8 : constant Word := 16#1800#; -- APB1 is HCLK / 8
PPRE1_DIV16 : constant Word := 16#1C00#; -- APB1 is HCLK / 16
-- APB2 prescaler
PPRE2_DIV1 : constant Word := 16#0000#; -- APB2 is HCLK / 1
PPRE2_DIV2 : constant Word := 16#8000#; -- APB2 is HCLK / 2
PPRE2_DIV4 : constant Word := 16#A000#; -- APB2 is HCLK / 4
PPRE2_DIV8 : constant Word := 16#C000#; -- APB2 is HCLK / 8
PPRE2_DIV16 : constant Word := 16#E000#; -- APB2 is HCLK / 16
-- MCO1 clock selector
MCO1SEL_HSI : constant Word := 0 * 2 ** 21; -- HSI clock on MC01 pin
MCO1SEL_LSE : constant Word := 1 * 2 ** 21; -- LSE clock on MC01 pin
MCO1SEL_HSE : constant Word := 2 * 2 ** 21; -- HSE clock on MC01 pin
MCO1SEL_PLL : constant Word := 3 * 2 ** 21; -- PLL clock on MC01 pin
-- MCO1 prescaler
MCO1PRE_DIV1 : constant Word := 0 * 2 ** 24; -- MC01 divides by 1
MCO1PRE_DIV2 : constant Word := 4 * 2 ** 24; -- MC01 divides by 2
MCO1PRE_DIV3 : constant Word := 5 * 2 ** 24; -- MC01 divides by 3
MCO1PRE_DIV4 : constant Word := 6 * 2 ** 24; -- MC01 divides by 4
MCO1PRE_DIV5 : constant Word := 7 * 2 ** 24; -- MC01 divides by 5
-- MCO2 clock selector
MCO2SEL_SYSCLK : constant Word := 0 * 2 ** 30; -- SYSCLK clock on MCO2 pin
MCO2SEL_PLLI2S : constant Word := 1 * 2 ** 30; -- SYSCLK clock on MCO2 pin
MCO2SEL_HSE : constant Word := 2 * 2 ** 30; -- SYSCLK clock on MCO2 pin
MCO2SEL_PLL : constant Word := 3 * 2 ** 30; -- SYSCLK clock on MCO2 pin
-- MCO2 prescaler
MCO2PRE_DIV1 : constant Word := 0 * 2 ** 27; -- MCO2 divides by 1
MCO2PRE_DIV2 : constant Word := 4 * 2 ** 27; -- MCO2 divides by 4
MCO2PRE_DIV3 : constant Word := 5 * 2 ** 27; -- MCO2 divides by 5
MCO2PRE_DIV4 : constant Word := 6 * 2 ** 27; -- MCO2 divides by 6
MCO2PRE_DIV5 : constant Word := 7 * 2 ** 27; -- MCO2 divides by 7
-- I2S clock source
I2SSRC_PLLI2S : constant Word := 0 * 2 ** 23; -- I2SSRC is PLLI2S
I2SSRC_PCKIN : constant Word := 1 * 2 ** 23; -- I2SSRC is I2S_CKIN
-- System clock switch
SW_HSI : constant Word := 16#0#; -- HSI selected as system clock
SW_HSE : constant Word := 16#1#; -- HSI selected as system clock
SW_PLL : constant Word := 16#2#; -- PLL selected as system clock
-- System clock switch status
SWS_HSI : constant Word := 16#0#; -- HSI used as system clock
SWS_HSE : constant Word := 16#4#; -- HSI used as system clock
SWS_PLL : constant Word := 16#8#; -- PLL used as system clock
-- Constants for RCC CR register
LSION : constant Word := 2 ** 0; -- Int. low-speed clock enable
LSIRDY : constant Word := 2 ** 1; -- Int. low-speed clock enable
end STM32F4.Reset_Clock_Control;
Raw
stm32f4.ads
-------------------------------------------------
-------------------------------
-- --
-- GNAT EXAMPLE --
-- --
-- Copyright (C) 2014, Free Software Foundation, Inc. --
-- --
-- GNAT is free software; you can redistribute it and/or modify it under --
-- terms of the GNU General Public License as published by the Free Soft- --
-- ware Foundation; either version 3, or (at your option) any later ver- --
-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
-- or FITNESS FOR A PARTICULAR PURPOSE. --
-- --
-- --
-- --
-- --
-- --
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
-- <http://www.gnu.org/licenses/>. --
-- --
-- GNAT was originally developed by the GNAT team at New York University. --
-- Extensive contributions were provided by Ada Core Technologies Inc. --
-- --
------------------------------------------------------------------------------
-- This file provides type definitions for the STM32F4 (ARM Cortex M4F)
-- microcontrollers from ST Microelectronics.
pragma Restrictions (No_Elaboration_Code);
with Interfaces;
package STM32F4 is
type Word is new Interfaces.Unsigned_32; -- for shift/rotate
type Half_Word is new Interfaces.Unsigned_16; -- for shift/rotate
type Byte is new Interfaces.Unsigned_8; -- for shift/rotate
type Bits_1 is mod 2 ** 1 with Size => 1;
type Bits_2 is mod 2**2 with Size => 2;
type Bits_4 is mod 2**4 with Size => 4;
type Bits_32x1 is array (0 .. 31) of Bits_1 with Pack, Size => 32;
type Bits_16x2 is array (0 .. 15) of Bits_2 with Pack, Size => 32;
type Bits_8x4 is array (0 .. 7) of Bits_4 with Pack, Size => 32;
-- Define address bases for the various system components
Peripheral_Base : constant := 16#4000_0000#;
-- bit banding alias
Peripheral_Alias_Base : constant := 16#4200_0000#;
APB1_Peripheral_Base : constant := Peripheral_Base;
APB2_Peripheral_Base : constant := Peripheral_Base + 16#0001_0000#;
AHB1_Peripheral_Base : constant := Peripheral_Base + 16#0002_0000#;
AHB2_Peripheral_Base : constant := Peripheral_Base + 16#1000_0000#;
AHB3_Peripheral_Base : constant := Peripheral_Base + 16#A000_0000#;
FSMC_Base : constant := AHB3_Peripheral_Base + 16#0000#;
RNG_Base : constant := AHB2_Peripheral_Base + 16#6_0800#;
HASH_Base : constant := AHB2_Peripheral_Base + 16#6_0400#;
CRYP_Base : constant := AHB2_Peripheral_Base + 16#6_0000#;
DCMI_Base : constant := AHB2_Peripheral_Base + 16#5_0000#;
USBFS_Base : constant := AHB2_Peripheral_Base + 16#0_0000#;
USBHS_Base : constant := AHB1_Peripheral_Base + 16#2_0000#;
ETH_Base : constant := AHB1_Peripheral_Base + 16#8000#;
DMA2_Base : constant := AHB1_Peripheral_Base + 16#6400#;
DMA1_Base : constant := AHB1_Peripheral_Base + 16#6000#;
BKPSRAM_Base : constant := AHB1_Peripheral_Base + 16#4000#;
FLASH_Base : constant := AHB1_Peripheral_Base + 16#3C00#;
RCC_Base : constant := AHB1_Peripheral_Base + 16#3800#;
CRC_Base : constant := AHB1_Peripheral_Base + 16#3000#;
GPIOI_Base : constant := AHB1_Peripheral_Base + 16#2000#;
GPIOH_Base : constant := AHB1_Peripheral_Base + 16#1C00#;
GPIOG_Base : constant := AHB1_Peripheral_Base + 16#1800#;
GPIOF_Base : constant := AHB1_Peripheral_Base + 16#1400#;
GPIOE_Base : constant := AHB1_Peripheral_Base + 16#1000#;
GPIOD_Base : constant := AHB1_Peripheral_Base + 16#0C00#;
GPIOC_Base : constant := AHB1_Peripheral_Base + 16#0800#;
GPIOB_Base : constant := AHB1_Peripheral_Base + 16#0400#;
GPIOA_Base : constant := AHB1_Peripheral_Base + 16#0000#;
TIM11_Base : constant := APB2_Peripheral_Base + 16#4800#;
TIM10_Base : constant := APB2_Peripheral_Base + 16#4400#;
TIM9_Base : constant := APB2_Peripheral_Base + 16#4000#;
EXTI_Base : constant := APB2_Peripheral_Base + 16#3C00#;
SYSCFG_Base : constant := APB2_Peripheral_Base + 16#3800#;
SPI1_Base : constant := APB2_Peripheral_Base + 16#3000#;
SDIO_Base : constant := APB2_Peripheral_Base + 16#2C00#;
ADC_Base : constant := APB2_Peripheral_Base + 16#2000#;
USART6_Base : constant := APB2_Peripheral_Base + 16#1400#;
USART1_Base : constant := APB2_Peripheral_Base + 16#1000#;
TIM8_Base : constant := APB2_Peripheral_Base + 16#0400#;
TIM1_Base : constant := APB2_Peripheral_Base + 16#0000#;
DAC_Base : constant := APB1_Peripheral_Base + 16#7400#;
PWR_Base : constant := APB1_Peripheral_Base + 16#7000#;
CAN2_Base : constant := APB1_Peripheral_Base + 16#6800#;
CAN1_Base : constant := APB1_Peripheral_Base + 16#6400#;
I2C3_Base : constant := APB1_Peripheral_Base + 16#5C00#;
I2C2_Base : constant := APB1_Peripheral_Base + 16#5800#;
I2C1_Base : constant := APB1_Peripheral_Base + 16#5400#;
UART5_Base : constant := APB1_Peripheral_Base + 16#5000#;
UART4_Base : constant := APB1_Peripheral_Base + 16#4C00#;
USART3_Base : constant := APB1_Peripheral_Base + 16#4800#;
USART2_Base : constant := APB1_Peripheral_Base + 16#4400#;
I2S3_Base : constant := APB1_Peripheral_Base + 16#4000#;
SPI3_Base : constant := APB1_Peripheral_Base + 16#3C00#;
SPI2_Base : constant := APB1_Peripheral_Base + 16#3800#;
I2S2_Base : constant := APB1_Peripheral_Base + 16#3400#;
IWDG_Base : constant := APB1_Peripheral_Base + 16#3000#;
WWDG_Base : constant := APB1_Peripheral_Base + 16#2C00#;
RTC_Base : constant := APB1_Peripheral_Base + 16#2800#;
TIM14_Base : constant := APB1_Peripheral_Base + 16#2000#;
TIM13_Base : constant := APB1_Peripheral_Base + 16#1C00#;
TIM12_Base : constant := APB1_Peripheral_Base + 16#1800#;
TIM7_Base : constant := APB1_Peripheral_Base + 16#1400#;
TIM6_Base : constant := APB1_Peripheral_Base + 16#1000#;
TIM5_Base : constant := APB1_Peripheral_Base + 16#0C00#;
TIM4_Base : constant := APB1_Peripheral_Base + 16#0800#;
TIM3_Base : constant := APB1_Peripheral_Base + 16#0400#;
TIM2_Base : constant := APB1_Peripheral_Base + 16#0000#;
AHB1RSTR_Base : constant :=RCC_Base + 16;
AHB1ENR_Base : constant :=RCC_Base + 48;
AHB1LPENR_Base : constant :=RCC_Base + 80;
APB2RSTR_Base : constant :=RCC_Base +36;
APB2ENR_Base :constant:= RCC_Base +68;
APB2LPENR_Base:constant :=RCC_Base +00;
end STM32F4;
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