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nvsofts/boot_fail_psmini.log

Last active December 4, 2018 20:13
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PlayStation Classic boot failed (maybe rework of eMMC was failed)
Raw
boot_fail_psmini.log
���������������������������������oot from normal
mt_pll_init +
CLK_GATING_CTRL1:d891923e
after set, CLK_GATING_CTRL1:d891923e
CLK_GATING_CTRL2:7afdbf10
[PWRAP] pmic ID: 2092.
[EMI] MDL number = 0
[EMI] PCDDR3
Vcore HV NV LV, Vdram HV NV LV
0x5f 0x48 0x3f, 0xc 0x0 0x3
get dram size from AUXADC1 0 0
[EMI] Use Common DDR3 x32 emi settings
[EMI] Config emi settings:
EMI_CONA=0x2012, EMI_CONH=0x3
EMI_RANK0=0x40000000, EMI_RANK1=0x0
EMI_CONA=0x2012
EMI_CONF=0x4210000
EMI_CONH=0x3
[DramcSwImpedanceCal] FINAL: DRVP=7, DRVN=6
PCDDR3 Pinmux 0
SSC OFF
DRAM Clock: 1584MHz
[Write Leveling]
WriteLevelingMoveDQSInsteadOfCLK
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
WL Clk delay = 0, CA CLK delay = 0
No need to update CA/CS delay because the CLK delay is small than CA training.
Final Clk output delay = 0
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS0 delay = 36
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS1 delay = 35
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS2 delay = 33
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS3 delay = 32
[DramcWriteLeveling] ====Done====
[Gating]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
[Byte 0]First pass (1, 3, 12)
[Byte 1]First pass (1, 3, 12)
[Byte 2]First pass (1, 3, 12)
[Byte 3]First pass (1, 3, 12)
[Byte 0]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 3]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 2]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 1]Bigger pass win(1, 5, 7) Pass tap=59
===============================================================================
dqs input gating widnow, final delay value
Frequency=1600 rank=0
===============================================================================
R0 FINAL: GW best DQS0 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS1 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 59]
R0 FINAL: GW best DQS2 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS3 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
R0 FINAL: GW best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
[DramcRxdqsGatingCal] ====Done====
[DATLAT]
DATLAT Default value = 0xf
5, 0xFFFFFFFF, sum=0
6, 0xFFFFFFFF, sum=0
7, 0xFFFFFFFF, sum=0
8, 0xFFFFFFFF, sum=0
9, 0xFFFFFFFF, sum=0
10, 0xFFFFFFFF, sum=0
11, 0xFFFFFFFF, sum=0
12, 0xFFFFFFFF, sum=0
13, 0x200000, sum=0
14, 0x0, sum=1
15, 0x0, sum=2
16, 0x0, sum=3
17, 0x0, sum=4
18, 0x0, sum=5
pattern=5 first_step=14 total pass=6 best_step=16
R0 FINAL: DATLAT = 16 [14 ~ 19]
[DramcRxdatlatCal] ====Done====
[RX]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
RX Window Sum 948
R0 FINAL: RX Bit 0, 13 (-3 ~ 30) 34
R0 FINAL: RX Bit 1, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 2, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 3, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 4, 14 (2 ~ 27) 26
R0 FINAL: RX Bit 5, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 6, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 7, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 8, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 9, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 10, 15 (0 ~ 31) 32
R0 FINAL: RX Bit 11, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 12, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 13, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 14, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 15, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 16, 17 (2 ~ 33) 32
R0 FINAL: RX Bit 17, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 18, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 19, 17 (1 ~ 33) 33
R0 FINAL: RX Bit 20, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 21, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 22, 15 (1 ~ 30) 30
R0 FINAL: RX Bit 23, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 24, 14 (1 ~ 28) 28
R0 FINAL: RX Bit 25, 17 (4 ~ 30) 27
R0 FINAL: RX Bit 26, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 27, 15 (3 ~ 28) 26
R0 FINAL: RX Bit 28, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 29, 15 (1 ~ 30) 30
R0 FINAL: RX Bit 30, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 31, 16 (3 ~ 30) 28
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
DQS Delay :
DQS0 = 0, DQS1 = 0, DQS2 = 0, DQS3 = 0
DQM Delay :
DQM0 = 13, DQM1 = 14, DQM2 = 16, DQM3 = 15
DQ Delay :
DQ0 =13, DQ1 =14, DQ2 =15, DQ3 =13
DQ4 =14, DQ5 =14, DQ6 =14, DQ7 =14
DQ8 =14, DQ9 =15, DQ10 =15, DQ11 =14
DQ12 =14, DQ13 =15, DQ14 =14, DQ15 =14
DQ16 =17, DQ17 =16, DQ18 =16, DQ19 =17
DQ20 =15, DQ21 =16, DQ22 =15, DQ23 =16
DQ24 =14, DQ25 =17, DQ26 =15, DQ27 =15
DQ28 =15, DQ29 =15, DQ30 =16, DQ31 =16
________________________________________________________________________
[DramcRxWindowPerbitCal] ====Done====
[TX]
[DramcTxWindowPerbitCal] Frequency=1600, Rank=0, calType=2
[DramcTxWindowPerbitCal] Begin, TX DQ(2, 0), DQ OEN(1, 2)
TX Window Sum 848
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
R0 FINAL: TX Bit0 (38~64) 27 51, Bit8 (39~64) 26 51, Bit16 (38~63) 26 50, Bit24 (34~60) 27 47
R0 FINAL: TX Bit1 (37~63) 27 50, Bit9 (40~65) 26 52, Bit17 (36~62) 27 49, Bit25 (37~62) 26 49
R0 FINAL: TX Bit2 (38~64) 27 51, Bit10 (40~65) 26 52, Bit18 (37~63) 27 50, Bit26 (36~61) 26 48
R0 FINAL: TX Bit3 (37~63) 27 50, Bit11 (38~64) 27 51, Bit19 (36~63) 28 49, Bit27 (36~61) 26 48
R0 FINAL: TX Bit4 (39~63) 25 51, Bit12 (38~63) 26 50, Bit20 (35~62) 28 48, Bit28 (36~61) 26 48
R0 FINAL: TX Bit5 (40~64) 25 52, Bit13 (39~64) 26 51, Bit21 (37~63) 27 50, Bit29 (35~61) 27 48
R0 FINAL: TX Bit6 (38~63) 26 50, Bit14 (38~63) 26 50, Bit22 (35~62) 28 48, Bit30 (35~61) 27 48
R0 FINAL: TX Bit7 (38~63) 26 50, Bit15 (40~63) 24 51, Bit23 (38~64) 27 51, Bit31 (36~63) 28 49
==================================================================
Byte0, PI DQ Delay 51 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte1, PI DQ Delay 51 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte2, PI DQ Delay 49 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
Byte3, PI DQ Delay 48 Delay2 48
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 48)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 48)
[DramcTxWindowPerbitCal] ====Done====
[DramcRxdqsGatingPostProcess] p->frequency 1600
[DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3
Settings after calibration ...
=== [DramcRunTimeConfig] ===
ZQCS_ENABLE: ON
LOWPOWER_GOLDEN_SETTINGS(DCM): ON
SPM_CONTROL_AFTERK: ON
TEMP_SENSOR_ENABLE: OFF
ENABLE_PER_BANK_REFRESH: OFF
HW_SAVE_FOR_SR: OFF
=========================
0:dram_rank_size:40000000
dram size 0x40000000.
[MEM] complex R/W mem test pass
CLK_MUX_REG =0x27109726
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
phase: [map:1ffffff] [maxlen:25] [final:8]
Final cmd pad delay: 8
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
phase error: [map:0]
Final data pad delay: ff
hs200 tuning data error!
[eMMC] Size: 14910 MB, Max.Speed: 200000 kHz, blklen(512), nblks(30535680), ro(0)
starting app fitboot
failed to open MISC
choose first boot partition:BOOTIMG1 , tee choose: TEE1
Partition [BOOTIMG1] is not exist.
Partition [TEE1] is not exist.
load boot image failed
�����������������oot from normal
mt_pll_init +
CLK_GATING_CTRL1:d891923e
after set, CLK_GATING_CTRL1:d891923e
CLK_GATING_CTRL2:7afdbf10
[PWRAP] pmic ID: 2092.
[EMI] MDL number = 0
[EMI] PCDDR3
Vcore HV NV LV, Vdram HV NV LV
0x5f 0x48 0x3f, 0xc 0x0 0x3
get dram size from AUXADC1 0 0
[EMI] Use Common DDR3 x32 emi settings
[EMI] Config emi settings:
EMI_CONA=0x2012, EMI_CONH=0x3
EMI_RANK0=0x40000000, EMI_RANK1=0x0
EMI_CONA=0x2012
EMI_CONF=0x4210000
EMI_CONH=0x3
[DramcSwImpedanceCal] FINAL: DRVP=7, DRVN=6
PCDDR3 Pinmux 0
SSC OFF
DRAM Clock: 1584MHz
[Write Leveling]
WriteLevelingMoveDQSInsteadOfCLK
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
WL Clk delay = 0, CA CLK delay = 0
No need to update CA/CS delay because the CLK delay is small than CA training.
Final Clk output delay = 0
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS0 delay = 37
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS1 delay = 36
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS2 delay = 33
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS3 delay = 33
[DramcWriteLeveling] ====Done====
[Gating]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
[Byte 0]First pass (1, 3, 12)
[Byte 1]First pass (1, 3, 12)
[Byte 2]First pass (1, 3, 12)
[Byte 3]First pass (1, 3, 12)
[Byte 0]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 3]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 1]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 2]Bigger pass win(1, 5, 7) Pass tap=59
===============================================================================
dqs input gating widnow, final delay value
Frequency=1600 rank=0
===============================================================================
R0 FINAL: GW best DQS0 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS1 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS2 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 59]
R0 FINAL: GW best DQS3 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
R0 FINAL: GW best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
[DramcRxdqsGatingCal] ====Done====
[DATLAT]
DATLAT Default value = 0xf
5, 0xFFFFFFFF, sum=0
6, 0xFFFFFFFF, sum=0
7, 0xFFFFFFFF, sum=0
8, 0xFFFFFFFF, sum=0
9, 0xFFFFFFFF, sum=0
10, 0xFFFFFFFF, sum=0
11, 0xFFFFFFFF, sum=0
12, 0xFFFFFFFF, sum=0
13, 0x0, sum=1
14, 0x0, sum=2
15, 0x0, sum=3
16, 0x0, sum=4
17, 0x0, sum=5
pattern=5 first_step=13 total pass=6 best_step=15
R0 FINAL: DATLAT = 15 [13 ~ 18]
[DramcRxdatlatCal] ====Done====
[RX]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
RX Window Sum 949
R0 FINAL: RX Bit 0, 13 (-3 ~ 30) 34
R0 FINAL: RX Bit 1, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 2, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 3, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 4, 14 (2 ~ 27) 26
R0 FINAL: RX Bit 5, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 6, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 7, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 8, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 9, 15 (-1 ~ 32) 34
R0 FINAL: RX Bit 10, 15 (0 ~ 31) 32
R0 FINAL: RX Bit 11, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 12, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 13, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 14, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 15, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 16, 17 (2 ~ 33) 32
R0 FINAL: RX Bit 17, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 18, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 19, 17 (1 ~ 33) 33
R0 FINAL: RX Bit 20, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 21, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 22, 15 (1 ~ 30) 30
R0 FINAL: RX Bit 23, 16 (0 ~ 32) 33
R0 FINAL: RX Bit 24, 14 (0 ~ 28) 29
R0 FINAL: RX Bit 25, 17 (4 ~ 30) 27
R0 FINAL: RX Bit 26, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 27, 15 (2 ~ 28) 27
R0 FINAL: RX Bit 28, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 29, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 30, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 31, 16 (3 ~ 30) 28
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
DQS Delay :
DQS0 = 0, DQS1 = 0, DQS2 = 0, DQS3 = 0
DQM Delay :
DQM0 = 13, DQM1 = 14, DQM2 = 16, DQM3 = 15
DQ Delay :
DQ0 =13, DQ1 =13, DQ2 =15, DQ3 =13
DQ4 =14, DQ5 =14, DQ6 =14, DQ7 =14
DQ8 =15, DQ9 =15, DQ10 =15, DQ11 =14
DQ12 =15, DQ13 =15, DQ14 =14, DQ15 =15
DQ16 =17, DQ17 =16, DQ18 =17, DQ19 =17
DQ20 =15, DQ21 =17, DQ22 =15, DQ23 =16
DQ24 =14, DQ25 =17, DQ26 =15, DQ27 =15
DQ28 =16, DQ29 =16, DQ30 =16, DQ31 =16
________________________________________________________________________
[DramcRxWindowPerbitCal] ====Done====
[TX]
[DramcTxWindowPerbitCal] Frequency=1600, Rank=0, calType=2
[DramcTxWindowPerbitCal] Begin, TX DQ(2, 0), DQ OEN(1, 2)
TX Window Sum 851
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
R0 FINAL: TX Bit0 (39~64) 26 51, Bit8 (40~65) 26 52, Bit16 (37~64) 28 50, Bit24 (35~61) 27 48
R0 FINAL: TX Bit1 (38~65) 28 51, Bit9 (41~67) 27 54, Bit17 (36~63) 28 49, Bit25 (38~63) 26 50
R0 FINAL: TX Bit2 (40~65) 26 52, Bit10 (41~67) 27 54, Bit18 (37~63) 27 50, Bit26 (37~62) 26 49
R0 FINAL: TX Bit3 (38~64) 27 51, Bit11 (40~65) 26 52, Bit19 (36~63) 28 49, Bit27 (37~62) 26 49
R0 FINAL: TX Bit4 (40~64) 25 52, Bit12 (40~64) 25 52, Bit20 (35~62) 28 48, Bit28 (37~62) 26 49
R0 FINAL: TX Bit5 (41~65) 25 53, Bit13 (40~65) 26 52, Bit21 (37~64) 28 50, Bit29 (37~62) 26 49
R0 FINAL: TX Bit6 (39~64) 26 51, Bit14 (39~64) 26 51, Bit22 (35~63) 29 49, Bit30 (36~63) 28 49
R0 FINAL: TX Bit7 (39~64) 26 51, Bit15 (41~64) 24 52, Bit23 (37~64) 28 50, Bit31 (38~63) 26 50
==================================================================
Byte0, PI DQ Delay 52 Delay2 52
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 52)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 52)
Byte1, PI DQ Delay 52 Delay2 52
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 52)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 52)
Byte2, PI DQ Delay 49 Delay2 49
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 49)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 49)
Byte3, PI DQ Delay 49 Delay2 49
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 49)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 49)
[DramcTxWindowPerbitCal] ====Done====
[DramcRxdqsGatingPostProcess] p->frequency 1600
[DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3
Settings after calibration ...
=== [DramcRunTimeConfig] ===
ZQCS_ENABLE: ON
LOWPOWER_GOLDEN_SETTINGS(DCM): ON
SPM_CONTROL_AFTERK: ON
TEMP_SENSOR_ENABLE: OFF
ENABLE_PER_BANK_REFRESH: OFF
HW_SAVE_FOR_SR: OFF
=========================
0:dram_rank_size:40000000
dram size 0x40000000.
[MEM] complex R/W mem test pass
CLK_MUX_REG =0x27109726
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
phase: [map:1ffffff] [maxlen:25] [final:8]
Final cmd pad delay: 8
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
Final data pad delay: ff
hs200 tuning data error!
[eMMC] Size: 14910 MB, Max.Speed: 200000 kHz, blklen(512), nblks(30535680), ro(0)
starting app fitboot
failed to open MISC
choose first boot partition:BOOTIMG1 , tee choose: TEE1
Partition [BOOTIMG1] is not exist.
Partition [TEE1] is not exist.
load boot image failed
oot from normal
mt_pll_init +
CLK_GATING_CTRL1:d891923e
after set, CLK_GATING_CTRL1:d891923e
CLK_GATING_CTRL2:7afdbf10
[PWRAP] pmic ID: 2092.
[EMI] MDL number = 0
[EMI] PCDDR3
Vcore HV NV LV, Vdram HV NV LV
0x5f 0x48 0x3f, 0xc 0x0 0x3
get dram size from AUXADC1 0 0
[EMI] Use Common DDR3 x32 emi settings
[EMI] Config emi settings:
EMI_CONA=0x2012, EMI_CONH=0x3
EMI_RANK0=0x40000000, EMI_RANK1=0x0
EMI_CONA=0x2012
EMI_CONF=0x4210000
EMI_CONH=0x3
[DramcSwImpedanceCal] FINAL: DRVP=7, DRVN=6
PCDDR3 Pinmux 0
SSC OFF
DRAM Clock: 1584MHz
[Write Leveling]
WriteLevelingMoveDQSInsteadOfCLK
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
WL Clk delay = 0, CA CLK delay = 0
No need to update CA/CS delay because the CLK delay is small than CA training.
Final Clk output delay = 0
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS0 delay = 37
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS1 delay = 36
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS2 delay = 34
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS3 delay = 34
[DramcWriteLeveling] ====Done====
[Gating]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
[Byte 0]First pass (1, 3, 12)
[Byte 1]First pass (1, 3, 12)
[Byte 2]First pass (1, 3, 12)
[Byte 3]First pass (1, 3, 12)
[Byte 3]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 0]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 2]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 1]Bigger pass win(1, 5, 7) Pass tap=59
===============================================================================
dqs input gating widnow, final delay value
Frequency=1600 rank=0
===============================================================================
R0 FINAL: GW best DQS0 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS1 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 59]
R0 FINAL: GW best DQS2 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS3 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
[DramcRxdqsGatingCal] ====Done====
[DATLAT]
DATLAT Default value = 0xf
5, 0xFFFFFFFF, sum=0
6, 0xFFFFFFFF, sum=0
7, 0xFFFFFFFF, sum=0
8, 0xFFFFFFFF, sum=0
9, 0xFFFFFFFF, sum=0
10, 0xFFFFFFFF, sum=0
11, 0xFFFFFFFF, sum=0
12, 0xFFFFFFFF, sum=0
13, 0x0, sum=1
14, 0x0, sum=2
15, 0x0, sum=3
16, 0x0, sum=4
17, 0x0, sum=5
pattern=5 first_step=13 total pass=6 best_step=15
R0 FINAL: DATLAT = 15 [13 ~ 18]
[DramcRxdatlatCal] ====Done====
[RX]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
RX Window Sum 943
R0 FINAL: RX Bit 0, 13 (-3 ~ 30) 34
R0 FINAL: RX Bit 1, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 2, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 3, 13 (-3 ~ 29) 33
R0 FINAL: RX Bit 4, 14 (2 ~ 27) 26
R0 FINAL: RX Bit 5, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 6, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 7, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 8, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 9, 15 (-1 ~ 32) 34
R0 FINAL: RX Bit 10, 15 (0 ~ 31) 32
R0 FINAL: RX Bit 11, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 12, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 13, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 14, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 15, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 16, 17 (2 ~ 33) 32
R0 FINAL: RX Bit 17, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 18, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 19, 17 (1 ~ 33) 33
R0 FINAL: RX Bit 20, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 21, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 22, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 23, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 24, 14 (1 ~ 28) 28
R0 FINAL: RX Bit 25, 17 (4 ~ 30) 27
R0 FINAL: RX Bit 26, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 27, 16 (4 ~ 28) 25
R0 FINAL: RX Bit 28, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 29, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 30, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 31, 16 (3 ~ 30) 28
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
DQS Delay :
DQS0 = 0, DQS1 = 0, DQS2 = 0, DQS3 = 0
DQM Delay :
DQM0 = 13, DQM1 = 14, DQM2 = 16, DQM3 = 15
DQ Delay :
DQ0 =13, DQ1 =13, DQ2 =15, DQ3 =13
DQ4 =14, DQ5 =14, DQ6 =14, DQ7 =13
DQ8 =15, DQ9 =15, DQ10 =15, DQ11 =14
DQ12 =15, DQ13 =15, DQ14 =14, DQ15 =14
DQ16 =17, DQ17 =17, DQ18 =17, DQ19 =17
DQ20 =15, DQ21 =17, DQ22 =16, DQ23 =16
DQ24 =14, DQ25 =17, DQ26 =15, DQ27 =16
DQ28 =15, DQ29 =16, DQ30 =16, DQ31 =16
________________________________________________________________________
[DramcRxWindowPerbitCal] ====Done====
[TX]
[DramcTxWindowPerbitCal] Frequency=1600, Rank=0, calType=2
[DramcTxWindowPerbitCal] Begin, TX DQ(2, 0), DQ OEN(1, 2)
TX Window Sum 854
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
R0 FINAL: TX Bit0 (39~65) 27 52, Bit8 (40~65) 26 52, Bit16 (38~64) 27 51, Bit24 (36~62) 27 49
R0 FINAL: TX Bit1 (38~65) 28 51, Bit9 (41~67) 27 54, Bit17 (37~63) 27 50, Bit25 (39~64) 26 51
R0 FINAL: TX Bit2 (39~65) 27 52, Bit10 (41~68) 28 54, Bit18 (38~64) 27 51, Bit26 (38~63) 26 50
R0 FINAL: TX Bit3 (38~65) 28 51, Bit11 (40~65) 26 52, Bit19 (37~64) 28 50, Bit27 (38~62) 25 50
R0 FINAL: TX Bit4 (40~65) 26 52, Bit12 (40~65) 26 52, Bit20 (36~63) 28 49, Bit28 (38~63) 26 50
R0 FINAL: TX Bit5 (41~65) 25 53, Bit13 (40~65) 26 52, Bit21 (38~64) 27 51, Bit29 (38~63) 26 50
R0 FINAL: TX Bit6 (39~65) 27 52, Bit14 (39~65) 27 52, Bit22 (36~63) 28 49, Bit30 (37~63) 27 50
R0 FINAL: TX Bit7 (39~65) 27 52, Bit15 (41~65) 25 53, Bit23 (39~64) 26 51, Bit31 (38~64) 27 51
==================================================================
Byte0, PI DQ Delay 52 Delay2 53
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 53)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 53)
Byte1, PI DQ Delay 53 Delay2 53
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 53)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 53)
Byte2, PI DQ Delay 50 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte3, PI DQ Delay 50 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
[DramcTxWindowPerbitCal] ====Done====
[DramcRxdqsGatingPostProcess] p->frequency 1600
[DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3
Settings after calibration ...
=== [DramcRunTimeConfig] ===
ZQCS_ENABLE: ON
LOWPOWER_GOLDEN_SETTINGS(DCM): ON
SPM_CONTROL_AFTERK: ON
TEMP_SENSOR_ENABLE: OFF
ENABLE_PER_BANK_REFRESH: OFF
HW_SAVE_FOR_SR: OFF
=========================
0:dram_rank_size:40000000
dram size 0x40000000.
[MEM] complex R/W mem test pass
CLK_MUX_REG =0x27109726
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
phase: [map:1ffffff] [maxlen:25] [final:8]
Final cmd pad delay: 8
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
phase error: [map:0]
Final data pad delay: ff
hs200 tuning data error!
[eMMC] Size: 14910 MB, Max.Speed: 200000 kHz, blklen(512), nblks(30535680), ro(0)
starting app fitboot
failed to open MISC
choose first boot partition:BOOTIMG1 , tee choose: TEE1
Partition [BOOTIMG1] is not exist.
Partition [TEE1] is not exist.
load boot image failed
���������oot from normal
mt_pll_init +
CLK_GATING_CTRL1:d891923e
after set, CLK_GATING_CTRL1:d891923e
CLK_GATING_CTRL2:7afdbf10
[PWRAP] pmic ID: 2092.
[EMI] MDL number = 0
[EMI] PCDDR3
Vcore HV NV LV, Vdram HV NV LV
0x5f 0x48 0x3f, 0xc 0x0 0x3
get dram size from AUXADC1 0 0
[EMI] Use Common DDR3 x32 emi settings
[EMI] Config emi settings:
EMI_CONA=0x2012, EMI_CONH=0x3
EMI_RANK0=0x40000000, EMI_RANK1=0x0
EMI_CONA=0x2012
EMI_CONF=0x4210000
EMI_CONH=0x3
[DramcSwImpedanceCal] FINAL: DRVP=7, DRVN=6
PCDDR3 Pinmux 0
SSC OFF
DRAM Clock: 1584MHz
[Write Leveling]
WriteLevelingMoveDQSInsteadOfCLK
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
WL Clk delay = 0, CA CLK delay = 0
No need to update CA/CS delay because the CLK delay is small than CA training.
Final Clk output delay = 0
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS0 delay = 37
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS1 delay = 35
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS2 delay = 34
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS3 delay = 34
[DramcWriteLeveling] ====Done====
[Gating]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
[Byte 0]First pass (1, 3, 12)
[Byte 1]First pass (1, 3, 12)
[Byte 2]First pass (1, 3, 12)
[Byte 3]First pass (1, 3, 12)
[Byte 3]Bigger pass win(1, 5, 4) Pass tap=56
[Byte 0]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 2]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 1]Bigger pass win(1, 5, 7) Pass tap=59
===============================================================================
dqs input gating widnow, final delay value
Frequency=1600 rank=0
===============================================================================
R0 FINAL: GW best DQS0 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS1 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 59]
R0 FINAL: GW best DQS2 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS3 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 56]
R0 FINAL: GW best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
R0 FINAL: GW best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
[DramcRxdqsGatingCal] ====Done====
[DATLAT]
DATLAT Default value = 0xf
5, 0xFFFFFFFF, sum=0
6, 0xFFFFFFFF, sum=0
7, 0xFFFFFFFF, sum=0
8, 0xFFFFFFFF, sum=0
9, 0xFFFFFFFF, sum=0
10, 0xFFFFFFFF, sum=0
11, 0xFFFFFFFF, sum=0
12, 0xFFFFFFFF, sum=0
13, 0x0, sum=1
14, 0x0, sum=2
15, 0x0, sum=3
16, 0x0, sum=4
17, 0x0, sum=5
pattern=5 first_step=13 total pass=6 best_step=15
R0 FINAL: DATLAT = 15 [13 ~ 18]
[DramcRxdatlatCal] ====Done====
[RX]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
RX Window Sum 950
R0 FINAL: RX Bit 0, 13 (-3 ~ 30) 34
R0 FINAL: RX Bit 1, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 2, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 3, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 4, 14 (1 ~ 27) 27
R0 FINAL: RX Bit 5, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 6, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 7, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 8, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 9, 15 (-1 ~ 32) 34
R0 FINAL: RX Bit 10, 15 (0 ~ 31) 32
R0 FINAL: RX Bit 11, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 12, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 13, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 14, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 15, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 16, 17 (2 ~ 33) 32
R0 FINAL: RX Bit 17, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 18, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 19, 17 (1 ~ 33) 33
R0 FINAL: RX Bit 20, 15 (1 ~ 30) 30
R0 FINAL: RX Bit 21, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 22, 15 (1 ~ 30) 30
R0 FINAL: RX Bit 23, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 24, 14 (1 ~ 28) 28
R0 FINAL: RX Bit 25, 16 (3 ~ 30) 28
R0 FINAL: RX Bit 26, 16 (3 ~ 29) 27
R0 FINAL: RX Bit 27, 15 (3 ~ 28) 26
R0 FINAL: RX Bit 28, 16 (3 ~ 29) 27
R0 FINAL: RX Bit 29, 16 (3 ~ 30) 28
R0 FINAL: RX Bit 30, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 31, 16 (3 ~ 30) 28
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
DQS Delay :
DQS0 = 0, DQS1 = 0, DQS2 = 0, DQS3 = 0
DQM Delay :
DQM0 = 13, DQM1 = 14, DQM2 = 16, DQM3 = 15
DQ Delay :
DQ0 =13, DQ1 =13, DQ2 =15, DQ3 =13
DQ4 =14, DQ5 =14, DQ6 =14, DQ7 =13
DQ8 =14, DQ9 =15, DQ10 =15, DQ11 =14
DQ12 =14, DQ13 =15, DQ14 =14, DQ15 =14
DQ16 =17, DQ17 =16, DQ18 =16, DQ19 =17
DQ20 =15, DQ21 =17, DQ22 =15, DQ23 =16
DQ24 =14, DQ25 =16, DQ26 =16, DQ27 =15
DQ28 =16, DQ29 =16, DQ30 =16, DQ31 =16
________________________________________________________________________
[DramcRxWindowPerbitCal] ====Done====
[TX]
[DramcTxWindowPerbitCal] Frequency=1600, Rank=0, calType=2
[DramcTxWindowPerbitCal] Begin, TX DQ(2, 0), DQ OEN(1, 2)
TX Window Sum 850
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
R0 FINAL: TX Bit0 (39~65) 27 52, Bit8 (39~65) 27 52, Bit16 (38~64) 27 51, Bit24 (36~62) 27 49
R0 FINAL: TX Bit1 (38~65) 28 51, Bit9 (40~65) 26 52, Bit17 (37~63) 27 50, Bit25 (38~64) 27 51
R0 FINAL: TX Bit2 (39~65) 27 52, Bit10 (39~65) 27 52, Bit18 (38~64) 27 51, Bit26 (38~63) 26 50
R0 FINAL: TX Bit3 (38~64) 27 51, Bit11 (38~63) 26 50, Bit19 (38~64) 27 51, Bit27 (38~62) 25 50
R0 FINAL: TX Bit4 (40~65) 26 52, Bit12 (40~63) 24 51, Bit20 (36~63) 28 49, Bit28 (38~63) 26 50
R0 FINAL: TX Bit5 (41~65) 25 53, Bit13 (38~65) 28 51, Bit21 (38~64) 27 51, Bit29 (37~63) 27 50
R0 FINAL: TX Bit6 (39~65) 27 52, Bit14 (38~62) 25 50, Bit22 (36~63) 28 49, Bit30 (37~63) 27 50
R0 FINAL: TX Bit7 (39~64) 26 51, Bit15 (39~62) 24 50, Bit23 (38~64) 27 51, Bit31 (38~64) 27 51
==================================================================
Byte0, PI DQ Delay 52 Delay2 52
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 52)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 52)
Byte1, PI DQ Delay 51 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte2, PI DQ Delay 50 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
Byte3, PI DQ Delay 50 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
[DramcTxWindowPerbitCal] ====Done====
[DramcRxdqsGatingPostProcess] p->frequency 1600
[DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3
Settings after calibration ...
=== [DramcRunTimeConfig] ===
ZQCS_ENABLE: ON
LOWPOWER_GOLDEN_SETTINGS(DCM): ON
SPM_CONTROL_AFTERK: ON
TEMP_SENSOR_ENABLE: OFF
ENABLE_PER_BANK_REFRESH: OFF
HW_SAVE_FOR_SR: OFF
=========================
0:dram_rank_size:40000000
dram size 0x40000000.
[MEM] complex R/W mem test pass
CLK_MUX_REG =0x27109726
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
phase: [map:1ffffff] [maxlen:25] [final:8]
Final cmd pad delay: 8
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
Final data pad delay: ff
hs200 tuning data error!
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[eMMC] Size: 14910 MB, Max.Speed: 200000 kHz, blklen(512), nblks(30535680), ro(0)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[eMMC] MMCv4 but HS unsupported
Raw
boot_fail_psmini2.log
l_init +
CLK_GATING_CTRL1:d891b23e
after set, CLK_GATING_CTRL1:d891923e
CLK_GATING_CTRL2:7afdbf10
[PWRAP] pmic ID: 2092.
[EMI] MDL number = 0
[EMI] PCDDR3
Vcore HV NV LV, Vdram HV NV LV
0x5f 0x48 0x3f, 0xc 0x0 0x3
get dram size from AUXADC1 0 0
[EMI] Use Common DDR3 x32 emi settings
[EMI] Config emi settings:
EMI_CONA=0x2012, EMI_CONH=0x3
EMI_RANK0=0x40000000, EMI_RANK1=0x0
EMI_CONA=0x2012
EMI_CONF=0x4210000
EMI_CONH=0x3
[DramcSwImpedanceCal] FINAL: DRVP=7, DRVN=6
PCDDR3 Pinmux 0
SSC OFF
DRAM Clock: 1584MHz
[Write Leveling]
WriteLevelingMoveDQSInsteadOfCLK
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
WL Clk delay = 0, CA CLK delay = 0
No need to update CA/CS delay because the CLK delay is small than CA training.
Final Clk output delay = 0
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS0 delay = 36
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS1 delay = 36
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS2 delay = 34
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS3 delay = 34
[DramcWriteLeveling] ====Done====
[Gating]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
[Byte 0]First pass (1, 3, 12)
[Byte 1]First pass (1, 3, 12)
[Byte 2]First pass (1, 3, 12)
[Byte 3]First pass (1, 3, 12)
[Byte 3]Bigger pass win(1, 5, 4) Pass tap=56
[Byte 0]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 1]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 2]Bigger pass win(1, 5, 6) Pass tap=58
===============================================================================
dqs input gating widnow, final delay value
Frequency=1600 rank=0
===============================================================================
R0 FINAL: GW best DQS0 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS1 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS2 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS3 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 56]
R0 FINAL: GW best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
R0 FINAL: GW best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
[DramcRxdqsGatingCal] ====Done====
[DATLAT]
DATLAT Default value = 0xf
5, 0xFFFFFFFF, sum=0
6, 0xFFFFFFFF, sum=0
7, 0xFFFFFFFF, sum=0
8, 0xFFFFFFFF, sum=0
9, 0xFFFFFFFF, sum=0
10, 0xFFFFFFFF, sum=0
11, 0xFFFFFFFF, sum=0
12, 0xFFFFFFFF, sum=0
13, 0x0, sum=1
14, 0x0, sum=2
15, 0x0, sum=3
16, 0x0, sum=4
17, 0x0, sum=5
pattern=5 first_step=13 total pass=6 best_step=15
R0 FINAL: DATLAT = 15 [13 ~ 18]
[DramcRxdatlatCal] ====Done====
[RX]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
RX Window Sum 947
R0 FINAL: RX Bit 0, 14 (-2 ~ 30) 33
R0 FINAL: RX Bit 1, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 2, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 3, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 4, 14 (1 ~ 27) 27
R0 FINAL: RX Bit 5, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 6, 15 (1 ~ 29) 29
R0 FINAL: RX Bit 7, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 8, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 9, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 10, 16 (1 ~ 31) 31
R0 FINAL: RX Bit 11, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 12, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 13, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 14, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 15, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 16, 17 (1 ~ 33) 33
R0 FINAL: RX Bit 17, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 18, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 19, 17 (1 ~ 33) 33
R0 FINAL: RX Bit 20, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 21, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 22, 15 (1 ~ 30) 30
R0 FINAL: RX Bit 23, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 24, 14 (1 ~ 28) 28
R0 FINAL: RX Bit 25, 16 (3 ~ 30) 28
R0 FINAL: RX Bit 26, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 27, 15 (3 ~ 28) 26
R0 FINAL: RX Bit 28, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 29, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 30, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 31, 16 (3 ~ 30) 28
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
DQS Delay :
DQS0 = 0, DQS1 = 0, DQS2 = 0, DQS3 = 0
DQM Delay :
DQM0 = 13, DQM1 = 14, DQM2 = 16, DQM3 = 15
DQ Delay :
DQ0 =14, DQ1 =13, DQ2 =15, DQ3 =13
DQ4 =14, DQ5 =14, DQ6 =15, DQ7 =13
DQ8 =15, DQ9 =15, DQ10 =16, DQ11 =14
DQ12 =15, DQ13 =15, DQ14 =14, DQ15 =14
DQ16 =17, DQ17 =16, DQ18 =16, DQ19 =17
DQ20 =15, DQ21 =16, DQ22 =15, DQ23 =16
DQ24 =14, DQ25 =16, DQ26 =15, DQ27 =15
DQ28 =15, DQ29 =16, DQ30 =16, DQ31 =16
________________________________________________________________________
[DramcRxWindowPerbitCal] ====Done====
[TX]
[DramcTxWindowPerbitCal] Frequency=1600, Rank=0, calType=2
[DramcTxWindowPerbitCal] Begin, TX DQ(2, 0), DQ OEN(1, 2)
TX Window Sum 846
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
R0 FINAL: TX Bit0 (37~64) 28 50, Bit8 (40~65) 26 52, Bit16 (39~64) 26 51, Bit24 (36~62) 27 49
R0 FINAL: TX Bit1 (37~64) 28 50, Bit9 (41~67) 27 54, Bit17 (37~63) 27 50, Bit25 (39~64) 26 51
R0 FINAL: TX Bit2 (38~65) 28 51, Bit10 (41~66) 26 53, Bit18 (38~64) 27 51, Bit26 (38~63) 26 50
R0 FINAL: TX Bit3 (37~62) 26 49, Bit11 (39~65) 27 52, Bit19 (37~64) 28 50, Bit27 (38~62) 25 50
R0 FINAL: TX Bit4 (39~63) 25 51, Bit12 (40~64) 25 52, Bit20 (36~63) 28 49, Bit28 (38~63) 26 50
R0 FINAL: TX Bit5 (40~64) 25 52, Bit13 (40~65) 26 52, Bit21 (38~64) 27 51, Bit29 (38~63) 26 50
R0 FINAL: TX Bit6 (38~63) 26 50, Bit14 (39~64) 26 51, Bit22 (36~63) 28 49, Bit30 (37~63) 27 50
R0 FINAL: TX Bit7 (38~62) 25 50, Bit15 (41~64) 24 52, Bit23 (38~64) 27 51, Bit31 (38~64) 27 51
==================================================================
Byte0, PI DQ Delay 50 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte1, PI DQ Delay 52 Delay2 52
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 52)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 52)
Byte2, PI DQ Delay 50 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte3, PI DQ Delay 50 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
[DramcTxWindowPerbitCal] ====Done====
[DramcRxdqsGatingPostProcess] p->frequency 1600
[DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3
Settings after calibration ...
=== [DramcRunTimeConfig] ===
ZQCS_ENABLE: ON
LOWPOWER_GOLDEN_SETTINGS(DCM): ON
SPM_CONTROL_AFTERK: ON
TEMP_SENSOR_ENABLE: OFF
ENABLE_PER_BANK_REFRESH: OFF
HW_SAVE_FOR_SR: OFF
=========================
0:dram_rank_size:40000000
dram size 0x40000000.
[MEM] complex R/W mem test pass
CLK_MUX_REG =0x27109726
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
phase: [map:1ffffff] [maxlen:25] [final:8]
Final cmd pad delay: 8
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
phase error: [map:0]
Final data pad delay: ff
hs200 tuning data error!
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[eMMC] Size: 14910 MB, Max.Speed: 200000 kHz, blklen(512), nblks(30535680), ro(0)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[MSDC]<CHECKME> Unexpected INT(0x3000)
[eMMC] MMCv4 but HS unsupported
����������������������������������������������vl_init +
CLK_GATING_CTRL1:d891b23e
after set, CLK_GATING_CTRL1:d891923e
CLK_GATING_CTRL2:7afdbf10
[PWRAP] pmic ID: 2092.
[EMI] MDL number = 0
[EMI] PCDDR3
Vcore HV NV LV, Vdram HV NV LV
0x5f 0x48 0x3f, 0xc 0x0 0x3
get dram size from AUXADC1 0 0
[EMI] Use Common DDR3 x32 emi settings
[EMI] Config emi settings:
EMI_CONA=0x2012, EMI_CONH=0x3
EMI_RANK0=0x40000000, EMI_RANK1=0x0
EMI_CONA=0x2012
EMI_CONF=0x4210000
EMI_CONH=0x3
[DramcSwImpedanceCal] FINAL: DRVP=7, DRVN=6
PCDDR3 Pinmux 0
SSC OFF
DRAM Clock: 1584MHz
[Write Leveling]
WriteLevelingMoveDQSInsteadOfCLK
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
WL Clk delay = 0, CA CLK delay = 0
No need to update CA/CS delay because the CLK delay is small than CA training.
Final Clk output delay = 0
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS0 delay = 36
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS1 delay = 35
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS2 delay = 34
R0 FINAL: WriteLeveling DQS:(2, 0) OEN:(1, 2) DQS3 delay = 34
[DramcWriteLeveling] ====Done====
[Gating]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
[Byte 0]First pass (1, 3, 12)
[Byte 1]First pass (1, 3, 12)
[Byte 2]First pass (1, 3, 12)
[Byte 3]First pass (1, 3, 12)
[Byte 0]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 3]Bigger pass win(1, 5, 5) Pass tap=57
[Byte 1]Bigger pass win(1, 5, 6) Pass tap=58
[Byte 2]Bigger pass win(1, 5, 6) Pass tap=58
===============================================================================
dqs input gating widnow, final delay value
Frequency=1600 rank=0
===============================================================================
R0 FINAL: GW best DQS0 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS1 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS2 P0 delay(2T, 0.5T, PI) = (1, 4, 9) [tap = 58]
R0 FINAL: GW best DQS3 P0 delay(2T, 0.5T, PI) = (1, 4, 8) [tap = 57]
R0 FINAL: GW best DQS0 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
R0 FINAL: GW best DQS1 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS2 P1 delay(2T, 0.5T, PI) = (1, 6, 9)
R0 FINAL: GW best DQS3 P1 delay(2T, 0.5T, PI) = (1, 6, 8)
[DramcRxdqsGatingCal] ====Done====
[DATLAT]
DATLAT Default value = 0xf
5, 0xFFFFFFFF, sum=0
6, 0xFFFFFFFF, sum=0
7, 0xFFFFFFFF, sum=0
8, 0xFFFFFFFF, sum=0
9, 0xFFFFFFFF, sum=0
10, 0xFFFFFFFF, sum=0
11, 0xFFFFFFFF, sum=0
12, 0xFFFFFFFF, sum=0
13, 0x0, sum=1
14, 0x0, sum=2
15, 0x0, sum=3
16, 0x0, sum=4
17, 0x0, sum=5
pattern=5 first_step=13 total pass=6 best_step=15
R0 FINAL: DATLAT = 15 [13 ~ 18]
[DramcRxdatlatCal] ====Done====
[RX]
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
RX Window Sum 949
R0 FINAL: RX Bit 0, 13 (-3 ~ 30) 34
R0 FINAL: RX Bit 1, 13 (-2 ~ 29) 32
R0 FINAL: RX Bit 2, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 3, 13 (-3 ~ 29) 33
R0 FINAL: RX Bit 4, 14 (2 ~ 27) 26
R0 FINAL: RX Bit 5, 14 (-1 ~ 30) 32
R0 FINAL: RX Bit 6, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 7, 14 (-1 ~ 29) 31
R0 FINAL: RX Bit 8, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 9, 15 (-1 ~ 32) 34
R0 FINAL: RX Bit 10, 15 (0 ~ 31) 32
R0 FINAL: RX Bit 11, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 12, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 13, 15 (-1 ~ 31) 33
R0 FINAL: RX Bit 14, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 15, 14 (0 ~ 29) 30
R0 FINAL: RX Bit 16, 17 (2 ~ 33) 32
R0 FINAL: RX Bit 17, 16 (1 ~ 32) 32
R0 FINAL: RX Bit 18, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 19, 16 (0 ~ 33) 34
R0 FINAL: RX Bit 20, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 21, 17 (2 ~ 32) 31
R0 FINAL: RX Bit 22, 15 (0 ~ 30) 31
R0 FINAL: RX Bit 23, 16 (0 ~ 32) 33
R0 FINAL: RX Bit 24, 14 (0 ~ 28) 29
R0 FINAL: RX Bit 25, 17 (4 ~ 30) 27
R0 FINAL: RX Bit 26, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 27, 15 (3 ~ 28) 26
R0 FINAL: RX Bit 28, 15 (2 ~ 29) 28
R0 FINAL: RX Bit 29, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 30, 16 (2 ~ 30) 29
R0 FINAL: RX Bit 31, 16 (3 ~ 30) 28
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
DQS Delay :
DQS0 = 0, DQS1 = 0, DQS2 = 0, DQS3 = 0
DQM Delay :
DQM0 = 13, DQM1 = 14, DQM2 = 16, DQM3 = 15
DQ Delay :
DQ0 =13, DQ1 =13, DQ2 =15, DQ3 =13
DQ4 =14, DQ5 =14, DQ6 =14, DQ7 =14
DQ8 =15, DQ9 =15, DQ10 =15, DQ11 =14
DQ12 =15, DQ13 =15, DQ14 =14, DQ15 =14
DQ16 =17, DQ17 =16, DQ18 =17, DQ19 =16
DQ20 =15, DQ21 =17, DQ22 =15, DQ23 =16
DQ24 =14, DQ25 =17, DQ26 =15, DQ27 =15
DQ28 =15, DQ29 =16, DQ30 =16, DQ31 =16
________________________________________________________________________
[DramcRxWindowPerbitCal] ====Done====
[TX]
[DramcTxWindowPerbitCal] Frequency=1600, Rank=0, calType=2
[DramcTxWindowPerbitCal] Begin, TX DQ(2, 0), DQ OEN(1, 2)
TX Window Sum 842
===============================================================================
Dram Type= 4, Freqency= 1600, rank 0
odt_onoff= 0, Byte mode= 0, Read_DBI= 0, Write DBI= 0
===============================================================================
R0 FINAL: TX Bit0 (38~64) 27 51, Bit8 (39~64) 26 51, Bit16 (38~64) 27 51, Bit24 (36~62) 27 49
R0 FINAL: TX Bit1 (37~64) 28 50, Bit9 (39~65) 27 52, Bit17 (37~63) 27 50, Bit25 (39~64) 26 51
R0 FINAL: TX Bit2 (38~65) 28 51, Bit10 (40~65) 26 52, Bit18 (38~64) 27 51, Bit26 (38~62) 25 50
R0 FINAL: TX Bit3 (37~63) 27 50, Bit11 (38~64) 27 51, Bit19 (38~64) 27 51, Bit27 (38~62) 25 50
R0 FINAL: TX Bit4 (39~62) 24 50, Bit12 (39~64) 26 51, Bit20 (36~63) 28 49, Bit28 (38~63) 26 50
R0 FINAL: TX Bit5 (40~64) 25 52, Bit13 (39~64) 26 51, Bit21 (38~64) 27 51, Bit29 (38~63) 26 50
R0 FINAL: TX Bit6 (38~62) 25 50, Bit14 (38~62) 25 50, Bit22 (36~63) 28 49, Bit30 (37~63) 27 50
R0 FINAL: TX Bit7 (38~62) 25 50, Bit15 (40~62) 23 51, Bit23 (38~64) 27 51, Bit31 (38~64) 27 51
==================================================================
Byte0, PI DQ Delay 51 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte1, PI DQ Delay 51 Delay2 51
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 51)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 51)
Byte2, PI DQ Delay 50 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
Byte3, PI DQ Delay 50 Delay2 50
Final DQ PI Delay(LargeUI, SmallUI, PI) =(2 ,0, 50)
OEN DQ PI Delay(LargeUI, SmallUI, PI) =(1 ,2, 50)
[DramcTxWindowPerbitCal] ====Done====
[DramcRxdqsGatingPostProcess] p->frequency 1600
[DramcRxdqsGatingPostProcess] s1ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 3, u1TXDLY_Cal_min 3
Settings after calibration ...
=== [DramcRunTimeConfig] ===
ZQCS_ENABLE: ON
LOWPOWER_GOLDEN_SETTINGS(DCM): ON
SPM_CONTROL_AFTERK: ON
TEMP_SENSOR_ENABLE: OFF
ENABLE_PER_BANK_REFRESH: OFF
HW_SAVE_FOR_SR: OFF
=========================
0:dram_rank_size:40000000
dram size 0x40000000.
[MEM] complex R/W mem test pass
CLK_MUX_REG =0x27109726
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
[MSDC] cmd21 CRCERR! (0x400)
phase: [map:1ffffff] [maxlen:25] [final:8]
Final cmd pad delay: 8
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA DAT CRC error(8000h)
phase error: [map:0]
Final data pad delay: ff
hs200 tuning data error!
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[eMMC] Size: 14910 MB, Max.Speed: 200000 kHz, blklen(512), nblks(30535680), ro(0)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC]<CHECKME> Unexpected INT(0x8000)
[MSDC] DMA DAT CRC error(8000h)
[MSDC] DMA failed! err(2)
[MSDC] Abort: MSDC_FIFOCS=0h MSDC_PS=817f0002h SDC_STS=0h
[MSDC] Abort: MSDC_FIFOCS=0h MSDC_PS=817f0002h SDC_STS=0h
[MSDC] Abort: MSDC_FIFOCS=0h MSDC_PS=817f0002h SDC_STS=0h
[MSDC] Abort: MSDC_FIFOCS=0h MSDC_PS=817f0002h SDC_STS=0h
starting app fitboot
block devices:
mmc0, size 15634268160, bsize 512, ref 1, label <null> (no erase geometry)
mmc0boot0, size 4194304, bsize 512, ref 1, label <null> (no erase geometry)
mmc0boot1, size 4194304, bsize 512, ref 1, label <null> (no erase geometry)
mmc0rpmb, size 4194304, bsize 512, ref 2, label <null> (no erase geometry)
fastboot_init()
[USB] udc_start_cond
MT_USB0_IRQ_ID: 104
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