project4

Cars_in_a_row.v

module Cars_in_a_row {
  input wire clk,
  output [9:0] width, // width, spacing and pos
  output [9:0] spacing,
  output [9:0] posy
};

reg [9:0] posy_ = 0;
reg [9:0] spacing_ = 300;
reg [9:0] width_ = 200;

always @ (posedge clk)
  posy_ <= posy_ + 1;

assign posy = posy_;
assign spacing = spacing_;
assign width = width_;

endmodule

Clock.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:38:37 05/03/2015 
// Design Name: 
// Module Name:    Clock 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Clock(
  input clk,
  output buttons,
  output animate_objects,
);
   
integer counter = 0;
reg buttons_ = 0;
reg animate_object_ = 0;

always @ (posedge clk or posedge reset)
begin
  counter = counter + 1;
  if(counter%8333333==0)
  begin
    animate_object_ = ~animate_object_;
    counter = 0;
  end
end

assign buttons = buttons_;
assign animate_objects = animate_object_;

endmodule

Main.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:16:52 05/19/2015 
// Design Name: 
// Module Name:    Main
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Main(
  input wire clk,reset,
  input [3:0] button, // UDLR
  output wire hsync,vsync,
  output [2:0] red, // three bit signal to drive color red
  output [2:0] green, // three bit signal to drive color green
  output [1:0] blue // two bit signal to drive color blue (human eye is less sensitive to color blue)
);
     

// defining constants
localparam HD = 1280; // horizontal display area
localparam HF = 48; // front porch (right border)
localparam HB = 248; //right porch (left border)
localparam HR = 112; // horizontal retrace
localparam VD = 1024; // vertical display area
localparam VF = 1; // front porch (bottom border)
localparam VB = 38; // back porch (top border)
localparam VR = 3; // vertical retrace
localparam h_end = 1688; // total horizontal timing
localparam v_end = 1066; // total vertical timing
//localparam sq_size = 20; // size of square
localparam sq_x_l = 500; //  left coordinate of square
localparam sq_x_r = 510; //  right coord
localparam sq_y_t = 500; //  top
localparam sq_y_b = 510;

// Instantiation of clock
reg buttons;
reg animate_objects;
Clock clock( .clk(clk), .buttons(buttons), .animate_objects(animate_objects));

//horizontal and vertical counter

reg [10:0] h_count_reg,v_count_reg ; // registers for sequential horizontal and vertical counters
reg[10:0] h_count_next , v_count_next;
//reg v_sync_reg , h_sync_reg ;
//wire v_sync_next , h_sync_next ;
reg v_sync_next , h_sync_next = 0 ;

always @ ( posedge clk , posedge reset)
if (reset)
begin
    v_count_reg <= 0;
    h_count_reg <= 0 ;
    //v_sync_reg <= 1'b0;
    //h_sync_reg <= 1'b0;
end
else
begin
    v_count_reg <= v_count_next;
    h_count_reg <= h_count_next;
    //v_sync_reg <= v_sync_next ;
    //h_sync_reg <= h_sync_next ;
end

// horizontal and vertical counters
always @(posedge clk) 
begin
    if(h_count_next < h_end-1)
    begin         
        h_count_next <= h_count_next + 1;
    end else 
    begin
        h_count_next <= 0;       
        if(v_count_next < v_end-1)
            v_count_next <= v_count_next + 1;
        else
            v_count_next <= 0;
    end
end

// horizontal and vertical synchronization signals
always @(posedge clk)
if(h_count_reg < HR)
    h_sync_next <= 1;
else
    h_sync_next <= 0;
            
    
//VSync logic        
    
always @(posedge clk)
if(v_count_reg < VR)
    v_sync_next <= 1;
else
    v_sync_next <= 0;

assign hsync = h_sync_next;
assign vsync = v_sync_next;


    
reg h_video_on,v_video_on; // these registers ensure that the display signals are sent only 
//when the pixels are within the display region of the monitor.
//horizontal logic

always @(posedge clk) 
if((h_count_reg >= HR + HF) && (h_count_reg< HR + HF + HD))
    h_video_on <= 1;
else
    h_video_on <= 0;
            
    
//Vertical logic
    
always @(posedge clk)
if((v_count_reg >= VR + VF) && (v_count_reg < VR + VF+ VD))
    v_video_on <= 1;
else
    v_video_on <= 0;

reg video_on;

always @(posedge clk)
if(h_video_on && v_video_on)
    video_on <= 1;
else
    video_on <= 0;


reg [9:0] pixel_x,pixel_y; // registers to describe current position of pixel within display area.

always @(posedge clk)
if(h_video_on)
    pixel_x <= h_count_reg - HR - HF;
else
    pixel_x <= 0;

always @(posedge clk) 
if(v_video_on)
pixel_y <= v_count_reg - VR - VF;
else
pixel_y <= 0;

//color output
reg [7:0] coloroutput; // 8 bit register which describes which color has to be displayed but only when video_on signal is turned on.

always @(posedge clk)
if(~video_on)
    coloroutput <= 0;
else
begin
    if((pixel_x > sq_x_l && pixel_x < sq_x_r) && (pixel_y > sq_y_t && pixel_y < sq_y_b ))
        coloroutput[7:0] <= 8'b11100000;
    else 
    begin
        coloroutput [7:0] <= 8'b00000011;
    end
end


assign red = coloroutput[7:5];
assign green = coloroutput[4:2] ;
assign blue = coloroutput[1:0] ;


endmodule