timer_thing.core

CAPI=2:

name : ::timer:0

filesets:
  rtl:
    files:
      - hdl/timer_thing.sv : {file_type : systemVerilogSource}

  tb:
    files:
      - inc/higgs_helper.hpp : {is_include_file : true}
      - test_0.cpp : {is_include_file : true}
      - tb.cpp
    file_type : cppSource

targets:
  sim:
    default_tool : verilator
    filesets : [rtl, tb]
    toplevel : timer_thing
    tools:
      verilator:
        verilator_options : [-trace]