olofk · May 17, 2018 18:07
diff --git a/define_test.v b/define_test.v
 `default_nettype none
 module m(output wire a, input wire b);
   assign `A = b;
 endmodule
diff --git a/define_test.ys b/define_test.ys
 verilog_defines -DA=a
 read_verilog define_test.v
 synth_ice40 -top m -blif m.blif
diff --git a/doesntwork.sh b/doesntwork.sh
 yosys -p 'verilog_defines -DA=a; synth_ice40 -top m -blif m.blif' define_test.v
diff --git a/works.sh b/works.sh
 yosys -s define_test.ys
	`default_nettype none
	module m(output wire a, input wire b);
	assign `A = b;
	endmodule
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