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@olofk
Last active October 18, 2020 20:22
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`default_nettype none
module corescore_qf
(input wire i_rst_n,
output wire redled,
output wire blueled,
output wire greenled);
wire i_clk;
wire clk;
qlal4s3b_cell_macro u_qlal4s3b_cell_macro
(
.Sys_Clk0 (i_clk),
.Sys_Clk0_Rst (),
.Sys_Clk1 (),
.Sys_Clk1_Rst ());
gclkbuff u_gclkbuff_clock0 (.A(i_clk), .Z(clk));
reg [22:0] cnt;
reg rst_r;
assign blueled = cnt[22] | i_rst_n;
always @(posedge clk)
cnt <= cnt + 1;
endmodule
set_io redled 34
set_io greenled 39
set_io blueled 38
set_io i_rst_n 62
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