a.sv

module t
  (input a,
   output [3:0] b);

   genvar 	i;
   //generate <== Should be optional for sv vlog2005
   for (i=0 ; i<4 ; i=i+1) begin : genblock
     assign b[i] = a;
   end
   //endgenerate <== Should be optional for sv vlog2005
endmodule

qgen.tcl

project_new qgen -overwrite
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES
set_global_assignment -name TOP_LEVEL_ENTITY t
set_global_assignment -name SYSTEMVERILOG_FILE a.sv

run.sh

quartus_tcl -t qgen.tcl
quartus_map qgen