simple3.cvm

;; Prime value
%%prime 21888242871839275222246405745257275088548364400416034343698204186575808495617


;; Memory of signals
%%signals 49


;; Heap of components
%%components_heap 15


;; Types (for each field we store name type offset size nDims dims)


;; Main template
%%start B_2


;; Component creation mode (implicit/explicit)
%%components implicit


;; Witness (signal list)
%%witness 0 1 2 3 4 5 6


;; Input signals
%%input 3
"in1" ff 2 2 2
"in2" ff 2 3 2
"in3" ff 2 2 2


%%template A_0 [ ff 2 2 2] [ ff 2 2 2] [8] [ ]
x_0 = i64.1
;; getting dest
ff.store i64.0 ff.2
;; end of store bucket
;;line 15
x_1 = i64.4
x_2 = i64.0
x_3 = i64.4
loop
i64.if x_3 
x_4 = get_signal x_1
set_signal x_2 x_4
x_1 = i64.add x_1 i64.1
x_2 = i64.add x_2 i64.1
x_3 = i64.sub x_3 i64.1
continue
end
break
end
;; end of store bucket

%%template A_1 [ ff 2 3 2] [ ff 2 3 2] [12] [ ]
x_5 = i64.2
;;line 0
;; getting dest
ff.store i64.0 ff.3
;; end of store bucket
;;line 17
;; getting dest
ff.store i64.1 ff.0
;; end of store bucket
;; loop bucket. Line 17
loop
;; compute bucket
;; load bucket
x_6 = ff.load i64.1
;; end of load bucket
;; OP(LESSER)
x_7 = ff.lt x_6 ff.3
;; end of compute bucket
ff.if x_7
;;line 18
;; load bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_8 = ff.load i64.1
;; end of load bucket
;; OP(TO_ADDRESS)
x_9 = i64.wrap_ff x_8
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_10 = i64.mul i64.2 x_9
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_11 = i64.add x_10 i64.1
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_12 = i64.add x_11 i64.6
;; end of compute bucket
x_13 = get_signal x_12
;; end of load bucket
;; getting dest
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
;;line 18
x_14 = ff.load i64.1
;; end of load bucket
;; OP(TO_ADDRESS)
x_15 = i64.wrap_ff x_14
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_16 = i64.mul i64.2 x_15
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_17 = i64.add x_16 i64.0
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_18 = i64.add x_17 i64.0
;; end of compute bucket
;;line 18
set_signal x_18 x_13
;; end of store bucket
;;line 19
;; load bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_19 = ff.load i64.1
;; end of load bucket
;; OP(TO_ADDRESS)
x_20 = i64.wrap_ff x_19
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_21 = i64.mul i64.2 x_20
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_22 = i64.add x_21 i64.0
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_23 = i64.add x_22 i64.6
;; end of compute bucket
x_24 = get_signal x_23
;; end of load bucket
;; getting dest
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
;;line 19
x_25 = ff.load i64.1
;; end of load bucket
;; OP(TO_ADDRESS)
x_26 = i64.wrap_ff x_25
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_27 = i64.mul i64.2 x_26
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_28 = i64.add x_27 i64.1
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_29 = i64.add x_28 i64.0
;; end of compute bucket
;;line 19
set_signal x_29 x_24
;; end of store bucket
;;line 17
;; compute bucket
;; load bucket
x_30 = ff.load i64.1
;; end of load bucket
;; OP(ADD)
x_31 = ff.add x_30 ff.1
;; end of compute bucket
;; getting dest
ff.store i64.1 x_31
;; end of store bucket
continue
end
end
;; end of loop bucket

%%template B_2 [ ff 2 3 2] [ ff 2 2 2 ff 2 3 2 ff 2 2 2] [20] [ 0 1 0 ]
x_32 = i64.7
;;line 0
;; getting dest
ff.store i64.0 ff.2
;; end of store bucket
;; getting dest
ff.store i64.1 ff.3
;; end of store bucket
;; getting dest
ff.store i64.2 ff.2
;; end of store bucket
;;line 32
;; getting dest
ff.store i64.3 ff.0
;; end of store bucket
;; getting dest
ff.store i64.4 ff.0
;; end of store bucket
;; getting dest
ff.store i64.5 ff.0
;; end of store bucket
;; getting dest
ff.store i64.3 ff.2
;; end of store bucket
;; getting dest
ff.store i64.4 ff.3
;; end of store bucket
;; getting dest
ff.store i64.5 ff.2
;; end of store bucket
;;line 36
;; getting dest
ff.store i64.6 ff.0
;; end of store bucket
;; loop bucket. Line 36
loop
;; compute bucket
;; load bucket
x_33 = ff.load i64.6
;; end of load bucket
;; OP(LESSER)
x_34 = ff.lt x_33 ff.3
;; end of compute bucket
ff.if x_34
;; branch bucket
;; compute bucket
;; load bucket
;;line 38
x_35 = ff.load i64.6
;; end of load bucket
;; OP(EQ(Single(1)))
x_36 = ff.eq x_35 ff.0
;; end of compute bucket
ff.if x_36
;;line 39
;; is subcomponent mapped
x_41 = get_template_id i64.0
x_42 = get_template_signal_position x_41 i64.1
x_37 = i64.6
x_38 = x_42
x_43 = get_template_id i64.0
x_44 = i64.eq x_43 0
i64.if x_44
x_39 = i64.3
else
x_45 = i64.eq x_43 1
i64.if x_45
x_39 = i64.5
else
x_39 = i64.0
end
end
x_46 = i64.3
x_47 = i64.lt x_46 x_39
i64.if x_47
x_39 = x_46
end
loop
i64.if x_39 
x_40 = get_signal x_37
set_cmp_input_cnt i64.0 x_38 x_40
x_37 = i64.add x_37 i64.1
x_38 = i64.add x_38 i64.1
x_39 = i64.sub x_39 i64.1
continue
end
break
end
x_40 = get_signal x_37
set_cmp_input_cnt_check i64.0 x_38 x_40
;; end of store bucket
;; assert bucket
;; compute bucket
;; load bucket
;;line 40
;; is subcomponent mapped
x_48 = get_template_id i64.0
x_49 = get_template_signal_position x_48 i64.1
x_50 = get_cmp_signal i64.0 x_49
;; end of load bucket
;; load bucket
x_51 = get_signal i64.6
;; end of load bucket
;; OP(EQ(Single(4)))
x_53 = i64.4
loop
i64.if x_53 
x_54 = ff.eq x_50 x_51
ff.if x_54 
x_53 = i64.sub x_53 i64.1
x_50 = i64.add x_50 i64.1
x_51 = i64.add x_51 i64.1
continue
end
end
break
end
;; end of compute bucket
x_55 = ff.eqz x_52
ff.if x_55
error i64.0
end
;; end of assert bucket
;;line 38
else
;; branch bucket
;; compute bucket
;; load bucket
;;line 41
x_56 = ff.load i64.6
;; end of load bucket
;; OP(EQ(Single(1)))
x_57 = ff.eq x_56 ff.1
;; end of compute bucket
ff.if x_57
;;line 42
;; is subcomponent mapped
x_62 = get_template_id i64.1
x_63 = get_template_signal_position x_62 i64.1
x_58 = i64.10
x_59 = x_63
x_64 = get_template_id i64.1
x_65 = i64.eq x_64 0
i64.if x_65
x_60 = i64.3
else
x_66 = i64.eq x_64 1
i64.if x_66
x_60 = i64.5
else
x_60 = i64.0
end
end
x_67 = i64.5
x_68 = i64.lt x_67 x_60
i64.if x_68
x_60 = x_67
end
loop
i64.if x_60 
x_61 = get_signal x_58
set_cmp_input_cnt i64.1 x_59 x_61
x_58 = i64.add x_58 i64.1
x_59 = i64.add x_59 i64.1
x_60 = i64.sub x_60 i64.1
continue
end
break
end
x_61 = get_signal x_58
set_cmp_input_cnt_check i64.1 x_59 x_61
;; end of store bucket
;; assert bucket
;; compute bucket
;; load bucket
;;line 43
x_69 = get_signal i64.10
;; end of load bucket
;; load bucket
;; is subcomponent mapped
x_70 = get_template_id i64.1
x_71 = get_template_signal_position x_70 i64.1
x_72 = get_cmp_signal i64.1 x_71
;; end of load bucket
;; OP(EQ(Multiple([(0, 4), (1, 6)])))
x_76 = get_template_id i64.1
x_77 = i64.eq x_76 0
i64.if x_77
x_74 = i64.4
else
x_78 = i64.eq x_76 1
i64.if x_78
x_74 = i64.6
else
x_74 = i64.0
end
end
loop
i64.if x_74 
x_75 = ff.eq x_69 x_72
ff.if x_75 
x_74 = i64.sub x_74 i64.1
x_69 = i64.add x_69 i64.1
x_72 = i64.add x_72 i64.1
continue
end
end
break
end
;; end of compute bucket
x_79 = ff.eqz x_73
ff.if x_79
error i64.0
end
;; end of assert bucket
;;line 41
else
;;line 45
;; is subcomponent mapped
x_84 = get_template_id i64.2
x_85 = get_template_signal_position x_84 i64.1
x_80 = i64.16
x_81 = x_85
x_86 = get_template_id i64.2
x_87 = i64.eq x_86 0
i64.if x_87
x_82 = i64.3
else
x_88 = i64.eq x_86 1
i64.if x_88
x_82 = i64.5
else
x_82 = i64.0
end
end
x_89 = i64.3
x_90 = i64.lt x_89 x_82
i64.if x_90
x_82 = x_89
end
loop
i64.if x_82 
x_83 = get_signal x_80
set_cmp_input_cnt i64.2 x_81 x_83
x_80 = i64.add x_80 i64.1
x_81 = i64.add x_81 i64.1
x_82 = i64.sub x_82 i64.1
continue
end
break
end
x_83 = get_signal x_80
set_cmp_input_cnt_check i64.2 x_81 x_83
;; end of store bucket
;; assert bucket
;; compute bucket
;; load bucket
;;line 46
;; is subcomponent mapped
x_91 = get_template_id i64.2
x_92 = get_template_signal_position x_91 i64.1
x_93 = get_cmp_signal i64.2 x_92
;; end of load bucket
;; load bucket
x_94 = get_signal i64.16
;; end of load bucket
;; OP(EQ(Single(4)))
x_96 = i64.4
loop
i64.if x_96 
x_97 = ff.eq x_93 x_94
ff.if x_97 
x_96 = i64.sub x_96 i64.1
x_93 = i64.add x_93 i64.1
x_94 = i64.add x_94 i64.1
continue
end
end
break
end
;; end of compute bucket
x_98 = ff.eqz x_95
ff.if x_98
error i64.0
end
;; end of assert bucket
;; assert bucket
;; compute bucket
;; load bucket
;;line 47
x_99 = get_signal i64.16
;; end of load bucket
;; load bucket
;; is subcomponent mapped
x_100 = get_template_id i64.2
x_101 = get_template_signal_position x_100 i64.1
x_102 = get_cmp_signal i64.2 x_101
;; end of load bucket
;; OP(EQ(Multiple([(0, 4), (1, 6)])))
x_106 = get_template_id i64.2
x_107 = i64.eq x_106 0
i64.if x_107
x_104 = i64.4
else
x_108 = i64.eq x_106 1
i64.if x_108
x_104 = i64.6
else
x_104 = i64.0
end
end
loop
i64.if x_104 
x_105 = ff.eq x_99 x_102
ff.if x_105 
x_104 = i64.sub x_104 i64.1
x_99 = i64.add x_99 i64.1
x_102 = i64.add x_102 i64.1
continue
end
end
break
end
;; end of compute bucket
x_109 = ff.eqz x_103
ff.if x_109
error i64.0
end
;; end of assert bucket
end
;; end of branch bucket
end
;; end of branch bucket
;;line 49
;; is subcomponent mapped
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_110 = ff.load i64.6
;; end of load bucket
;; OP(TO_ADDRESS)
x_111 = i64.wrap_ff x_110
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_112 = i64.mul i64.1 x_111
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_113 = i64.add x_112 i64.0
;; end of compute bucket
x_114 = get_template_id x_113
x_115 = get_template_signal_position x_114 i64.0
x_116 = i64.0
x_117 =  get_template_signal_size x_114 i64.0
x_118 = i64.mul x_116 x_117
x_119 = i64.add x_115 x_116
;; end of load bucket
;;line 49
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_124 = ff.load i64.6
;; end of load bucket
;; OP(TO_ADDRESS)
x_125 = i64.wrap_ff x_124
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_126 = i64.mul i64.2 x_125
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_127 = i64.add x_126 i64.0
;; end of compute bucket
x_120 = x_119
x_121 = x_127
x_122 = i64.2
loop
i64.if x_122 
x_123 = get_cmp_signal x_113 x_120
set_signal x_121 x_123
x_120 = i64.add x_120 i64.1
x_121 = i64.add x_121 i64.1
x_122 = i64.sub x_122 i64.1
continue
end
break
end
;; end of store bucket
;; assert bucket
;; compute bucket
;; load bucket
;;line 50
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_128 = ff.load i64.6
;; end of load bucket
;; OP(TO_ADDRESS)
x_129 = i64.wrap_ff x_128
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_130 = i64.mul i64.2 x_129
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_131 = i64.add x_130 i64.0
;; end of compute bucket
x_132 = get_signal x_131
;; end of load bucket
;; load bucket
;;line 50
;; is subcomponent mapped
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_133 = ff.load i64.6
;; end of load bucket
;; OP(TO_ADDRESS)
x_134 = i64.wrap_ff x_133
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_135 = i64.mul i64.1 x_134
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_136 = i64.add x_135 i64.0
;; end of compute bucket
x_137 = get_template_id x_136
x_138 = get_template_signal_position x_137 i64.0
x_139 = i64.0
x_140 =  get_template_signal_size x_137 i64.0
x_141 = i64.mul x_139 x_140
x_142 = i64.add x_138 x_139
;; end of load bucket
x_143 = get_cmp_signal x_136 x_142
;; end of load bucket
;; OP(EQ(Single(2)))
;;line 50
x_145 = i64.2
loop
i64.if x_145 
x_146 = ff.eq x_132 x_143
ff.if x_146 
x_145 = i64.sub x_145 i64.1
x_132 = i64.add x_132 i64.1
x_143 = i64.add x_143 i64.1
continue
end
end
break
end
;; end of compute bucket
x_147 = ff.eqz x_144
ff.if x_147
error i64.0
end
;; end of assert bucket
;;line 36
;; compute bucket
;; load bucket
x_148 = ff.load i64.6
;; end of load bucket
;; OP(ADD)
x_149 = ff.add x_148 ff.1
;; end of compute bucket
;; getting dest
ff.store i64.6 x_149
;; end of store bucket
continue
end
end
;; end of loop bucket