circom20.cvm

;; Prime value
%%prime 21888242871839275222246405745257275088548364400416034343698204186575808495617


;; Memory of signals
%%signals 44


;; Heap of components
%%components_heap 16


;; Types (for each field we store name type offset size nDims dims)
%%type $bus_0
       $x $ff 0 1 0 
       $y $ff 1 1 0 
%%type $bus_1
       $start $$bus_0 0 2 0 
       $end $$bus_0 2 2 0 
%%type $bus_2
       $v $$bus_1 0 4 1  2


;; Main template
%%start Main_2


;; Component creation mode (implicit/explicit)
%%components implicit


;; Witness (signal list)
%%witness 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 30 31 32 33 35 36


%%template Tmpl1_0 [ ff 0 ] [ ff 1 2] [3] [ ]
x_0 = i64.0
;;line 20
;; compute bucket
;; load bucket
x_1 = get_signal i64.1
;; end of load bucket
;; load bucket
x_2 = get_signal i64.2
;; end of load bucket
;; OP(MUL)
x_3 = ff.mul x_1 x_2
;; end of compute bucket
;; getting dest
set_signal i64.0 x_3
;; end of store bucket

%%template Tmpl2_1 [ ff 0 ] [ ff 1 3] [4] [ ]
x_4 = i64.0
;;line 26
;; compute bucket
;; compute bucket
;; load bucket
x_5 = get_signal i64.1
;; end of load bucket
;; load bucket
x_6 = get_signal i64.2
;; end of load bucket
;; OP(MUL)
x_7 = ff.mul x_5 x_6
;; end of compute bucket
;; load bucket
x_8 = get_signal i64.3
;; end of load bucket
;; OP(ADD)
x_9 = ff.add x_7 x_8
;; end of compute bucket
;; getting dest
set_signal i64.0 x_9
;; end of store bucket

%%template Main_2 [ ff 2 2 3 bus_1 0 ] [ ff 1 5 ff 0  bus_2 0 ] [33] [ 0 -1 0 1 ]
x_10 = i64.2
;;line 39
;; compute bucket
;; load bucket
x_11 = get_signal i64.16
;; end of load bucket
;; load bucket
x_12 = get_signal i64.17
;; end of load bucket
;; OP(MUL)
x_13 = ff.mul x_11 x_12
;; end of compute bucket
;; getting dest
set_signal i64.29 x_13
;; end of store bucket
;;line 40
;; compute bucket
;; load bucket
x_14 = get_signal i64.18
;; end of load bucket
;; load bucket
x_15 = get_signal i64.19
;; end of load bucket
;; OP(MUL)
x_16 = ff.mul x_14 x_15
;; end of compute bucket
;; getting dest
set_signal i64.30 x_16
;; end of store bucket
;;line 41
;; compute bucket
;; load bucket
x_17 = get_signal i64.20
;; end of load bucket
;; load bucket
x_18 = get_signal i64.21
;; end of load bucket
;; OP(MUL)
x_19 = ff.mul x_17 x_18
;; end of compute bucket
;; getting dest
set_signal i64.31 x_19
;; end of store bucket
;;line 42
;; compute bucket
;; load bucket
x_20 = get_signal i64.22
;; end of load bucket
;; load bucket
x_21 = get_signal i64.23
;; end of load bucket
;; OP(MUL)
x_22 = ff.mul x_20 x_21
;; end of compute bucket
;; getting dest
set_signal i64.32 x_22
;; end of store bucket
;;line 44
;; compute bucket
;; load bucket
x_23 = get_signal i64.29
;; end of load bucket
;; load bucket
x_24 = get_signal i64.30
;; end of load bucket
;; OP(MUL)
x_25 = ff.mul x_23 x_24
;; end of compute bucket
;; getting dest
set_signal i64.25 x_25
;; end of store bucket
;;line 45
;; compute bucket
;; load bucket
x_26 = get_signal i64.31
;; end of load bucket
;; load bucket
x_27 = get_signal i64.32
;; end of load bucket
;; OP(MUL)
x_28 = ff.mul x_26 x_27
;; end of compute bucket
;; getting dest
set_signal i64.26 x_28
;; end of store bucket
;;line 47
;; compute bucket
;; load bucket
x_29 = get_signal i64.25
;; end of load bucket
;; load bucket
x_30 = get_signal i64.26
;; end of load bucket
;; OP(MUL)
x_31 = ff.mul x_29 x_30
;; end of compute bucket
;; getting dest
set_signal i64.24 x_31
;; end of store bucket
;;line 50
;; getting dest
ff.store i64.0 ff.0
;; end of store bucket
;; loop bucket. Line 50
loop
;; compute bucket
;; load bucket
x_32 = ff.load i64.0
;; end of load bucket
;; OP(LESSER)
x_33 = ff.lt x_32 ff.3
;; end of compute bucket
ff.if x_33
;; branch bucket
;; compute bucket
;; load bucket
;;line 51
x_34 = ff.load i64.0
;; end of load bucket
;; OP(NOT_EQ)
x_35 = ff.neq x_34 ff.1
;; end of compute bucket
ff.if x_35
;; branch bucket
;; compute bucket
;; load bucket
;;line 52
x_36 = ff.load i64.0
;; end of load bucket
;; OP(EQ(Single(1)))
x_37 = ff.eq x_36 ff.0
;; end of compute bucket
ff.if x_37
;; getting dest
ff.store i64.1 ff.0
;; end of store bucket
else
;; getting dest
ff.store i64.1 ff.2
;; end of store bucket
end
;; end of branch bucket
;;line 54
;; load bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_38 = ff.load i64.1
;; end of load bucket
;; OP(MOD)
x_39 = ff.rem x_38 ff.3
;; end of compute bucket
;; OP(TO_ADDRESS)
x_40 = i64.wrap_ff x_39
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_41 = i64.mul i64.1 x_40
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_42 = i64.add x_41 i64.10
;; end of compute bucket
x_43 = get_signal x_42
;; end of load bucket
;; getting dest
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
;;line 54
x_44 = ff.load i64.0
;; end of load bucket
;; OP(TO_ADDRESS)
x_45 = i64.wrap_ff x_44
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_46 = i64.mul i64.1 x_45
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_47 = i64.add x_46 i64.0
;; end of compute bucket
;;line 54
set_cmp_input_cnt_check x_47 i64.1 x_43
;; end of store bucket
;;line 55
;; load bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
x_48 = ff.load i64.1
;; end of load bucket
;; OP(MOD)
x_49 = ff.rem x_48 ff.3
;; end of compute bucket
;; OP(ADD)
x_50 = ff.add x_49 ff.1
;; end of compute bucket
;; OP(TO_ADDRESS)
x_51 = i64.wrap_ff x_50
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_52 = i64.mul i64.1 x_51
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_53 = i64.add x_52 i64.10
;; end of compute bucket
x_54 = get_signal x_53
;; end of load bucket
;; getting dest
;; compute bucket
;; compute bucket
;; compute bucket
;; load bucket
;;line 55
x_55 = ff.load i64.0
;; end of load bucket
;; OP(TO_ADDRESS)
x_56 = i64.wrap_ff x_55
;; end of compute bucket
;; OP(MUL_ADDRESS)
;;line 0
x_57 = i64.mul i64.1 x_56
;; end of compute bucket
;; OP(ADD_ADDRESS)
x_58 = i64.add x_57 i64.0
;; end of compute bucket
;;line 55
set_cmp_input_cnt_check x_58 i64.2 x_54
;; end of store bucket
;;line 51
end
;; end of branch bucket
;;line 50
;; compute bucket
;; load bucket
x_59 = ff.load i64.0
;; end of load bucket
;; OP(ADD)
x_60 = ff.add x_59 ff.1
;; end of compute bucket
;; getting dest
ff.store i64.0 x_60
;; end of store bucket
continue
end
end
;; end of loop bucket
;;line 66
;; load bucket
x_61 = get_cmp_signal i64.0 i64.0
;; end of load bucket
;; getting dest
set_cmp_input i64.3 i64.1 x_61
;; end of store bucket
;;line 67
;; load bucket
x_62 = get_cmp_signal i64.2 i64.0
;; end of load bucket
;; getting dest
set_cmp_input i64.3 i64.2 x_62
;; end of store bucket
;;line 68
;; load bucket
x_63 = get_signal i64.14
;; end of load bucket
;; getting dest
set_cmp_input_run i64.3 i64.3 x_63
;; end of store bucket
;;line 70
;; compute bucket
;; load bucket
x_64 = get_signal i64.16
;; end of load bucket
;; load bucket
x_65 = get_signal i64.17
;; end of load bucket
;; OP(MUL)
x_66 = ff.mul x_64 x_65
;; end of compute bucket
;; getting dest
set_signal i64.0 x_66
;; end of store bucket
;;line 71
;; compute bucket
;; load bucket
x_67 = get_signal i64.18
;; end of load bucket
;; load bucket
x_68 = get_signal i64.19
;; end of load bucket
;; OP(MUL)
x_69 = ff.mul x_67 x_68
;; end of compute bucket
;; getting dest
set_signal i64.1 x_69
;; end of store bucket
;;line 72
;; compute bucket
;; load bucket
x_70 = get_signal i64.20
;; end of load bucket
;; load bucket
x_71 = get_signal i64.21
;; end of load bucket
;; OP(MUL)
x_72 = ff.mul x_70 x_71
;; end of compute bucket
;; getting dest
set_signal i64.2 x_72
;; end of store bucket
;;line 73
;; compute bucket
;; load bucket
x_73 = get_signal i64.22
;; end of load bucket
;; load bucket
x_74 = get_signal i64.23
;; end of load bucket
;; OP(MUL)
x_75 = ff.mul x_73 x_74
;; end of compute bucket
;; getting dest
set_signal i64.3 x_75
;; end of store bucket
;;line 74
;; load bucket
x_76 = get_cmp_signal i64.3 i64.0
;; end of load bucket
;; getting dest
set_signal i64.4 x_76
;; end of store bucket
;;line 75
;; compute bucket
;; compute bucket
;; load bucket
x_77 = get_signal i64.24
;; end of load bucket
;; load bucket
x_78 = get_cmp_signal i64.3 i64.0
;; end of load bucket
;; OP(MUL)
x_79 = ff.mul x_77 x_78
;; end of compute bucket
;; load bucket
x_80 = get_signal i64.15
;; end of load bucket
;; OP(ADD)
x_81 = ff.add x_79 x_80
;; end of compute bucket
;; getting dest
set_signal i64.5 x_81
;; end of store bucket
;;line 78
x_82 = i64.16
x_83 = i64.6
x_84 = i64.4
loop
i64.if x_84 
x_85 = get_signal x_82
set_signal x_83 x_85
x_82 = i64.add x_82 i64.1
x_83 = i64.add x_83 i64.1
x_84 = i64.sub x_84 i64.1
continue
end
break
end
;; end of store bucket

circuit20.circom

pragma circom  2.1.6;

bus Point() {
    signal x;
    signal y;
}

bus Vector() {
    Point start;
    Point end;
}

bus TwoVectors() {
    Vector v[2];
}

template Tmpl1() {
    signal input in[2];
    signal output out;
    out <== in[0] * in[1];
}

template Tmpl2() {
    signal input in[3];
    signal output out;
    out <== in[0] * in[1] + in[2];
}

template Main() {
    signal input a[5];
    signal input inB;
    TwoVectors input v;
    signal output out[2][3];
    Vector output v2;
    signal s;
    signal s2[4];
    signal s4[4];

    s4[0] <== v.v[0].start.x * v.v[0].start.y;
    s4[1] <== v.v[0].end.x * v.v[0].end.y;
    s4[2] <== v.v[1].start.x * v.v[1].start.y;
    s4[3] <== v.v[1].end.x * v.v[1].end.y;

    s2[0] <== s4[0] * s4[1];
    s2[1] <== s4[2] * s4[3];

    s <== s2[0] * s2[1];

    component c1[3];
    for (var i = 0; i < 3; i++) {
        if (i != 1) {
            var idx = i == 0 ? 0 : (i - 1) * 2;
            c1[i] = Tmpl1();
            c1[i].in[0] <== a[idx%3];
            c1[i].in[1] <== a[idx%3+1];
        }
    }

    component b = Tmpl2();
    b.in[0] <== c1[0].out;
    b.in[1] <== c1[2].out;
    b.in[2] <== a[4];

    out[0][0] <== v.v[0].start.x * v.v[0].start.y;
    out[0][1] <== v.v[0].end.x * v.v[0].end.y;
    out[0][2] <== v.v[1].start.x * v.v[1].start.y;
    out[1][0] <== v.v[1].end.x * v.v[1].end.y;
    out[1][1] <== b.out;
    out[1][2] <== s * b.out + inB;

    v2 <== v.v[0];
}

component main = Main();

circuit20.sym

1,1,2,main.out[0][0]
2,2,2,main.out[0][1]
3,3,2,main.out[0][2]
4,4,2,main.out[1][0]
5,5,2,main.out[1][1]
6,6,2,main.out[1][2]
7,7,2,main.v2.start.x
8,8,2,main.v2.start.y
9,9,2,main.v2.end.x
10,10,2,main.v2.end.y
11,11,2,main.a[0]
12,12,2,main.a[1]
13,13,2,main.a[2]
14,14,2,main.a[3]
15,15,2,main.a[4]
16,16,2,main.inB
17,-1,2,main.v.v[0].start.x
18,-1,2,main.v.v[0].start.y
19,-1,2,main.v.v[0].end.x
20,-1,2,main.v.v[0].end.y
21,17,2,main.v.v[1].start.x
22,18,2,main.v.v[1].start.y
23,19,2,main.v.v[1].end.x
24,20,2,main.v.v[1].end.y
25,21,2,main.s
26,22,2,main.s2[0]
27,23,2,main.s2[1]
28,-1,2,main.s2[2]
29,-1,2,main.s2[3]
30,24,2,main.s4[0]
31,25,2,main.s4[1]
32,26,2,main.s4[2]
33,27,2,main.s4[3]
34,-1,1,main.b.out
35,28,1,main.b.in[0]
36,29,1,main.b.in[1]
37,-1,1,main.b.in[2]
38,-1,0,main.c1[0].out
39,-1,0,main.c1[0].in[0]
40,-1,0,main.c1[0].in[1]
41,-1,0,main.c1[2].out
42,-1,0,main.c1[2].in[0]
43,-1,0,main.c1[2].in[1]