PHY

gistfile1.txt

&ecspi2 {
	cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "okay";

	switch@0 {
		compatible = "nxp,sja1105q";
		reg = <0>;
		spi-max-frequency = <4000000>;
		spi-rx-delay-us = <1>;
		spi-tx-delay-us = <1>;
		spi-cpha;

		clocks = <&clk25m>;

		pinctrl-0 = <&pinctrl_sja1105_rst>;
		pinctrl-names = "default";
		reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				label = "ethphy0";
				phy-handle = <&ethphy0>;
				phy-mode = "mii";
			};

			port@1 {
				reg = <1>;
				label = "ethphy1";
				phy-handle = <&ethphy1>;
				phy-mode = "mii";
			};

			port@2 {
				reg = <2>;
				status = "disabled";
			};

			port@3 {
				reg = <3>;
				status = "disabled";
			};

			port@4 {
				reg = <4>;
				label = "cpu";
				ethernet = <&fec>;
				phy-mode = "mii";
				rx-internal-delay-ps = <2000>;
				tx-internal-delay-ps = <2000>;

				fixed-link {
					speed = <100>;
					full-duplex;
				};
			};
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "mii";
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};