coreboot-p34v2

# Porting coreboot to a Haswell / Lynx Point laptop: GIGABYTE P34V2

## autoport
### patch coreboot repo for LynxPoint support in autoport
https://review.coreboot.org/c/coreboot/+/30890
`git fetch https://review.coreboot.org/coreboot refs/changes/90/30890/2 && git cherry-pick FETCH_HEAD`

https://review.coreboot.org/c/coreboot/+/31759
`git fetch https://review.coreboot.org/coreboot refs/changes/59/31759/2 && git cherry-pick FETCH_HEAD`

### build autoport
see readme

### generate sources
`autoport --make-logs`

generates:

- devicetree.cb
- gpio.c
- hda_verb.c
- mainboard.c

### fix SPD addresses in romstage.c
see https://hannuhartikainen.fi/blog/hacking-ddr3-spd/
 -> use i2c-tools
 
```sh
🐢  modprobe i2c-dev
```

```sh
🐢  modprobe eeprom
🐢  decode-dimms | grep Decoding
Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0050
Decoding EEPROM: /sys/bus/i2c/drivers/eeprom/7-0052
```
 
```sh
 🐢  ls -l /sys/bus/i2c/drivers/eeprom/
total 0
lrwxrwxrwx 1 root root    0 Apr  4 01:46 6-0050 -> ../../../../devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/i2c-6/6-0050/
lrwxrwxrwx 1 root root    0 Apr  4 01:46 7-0050 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0050/
lrwxrwxrwx 1 root root    0 Apr  4 01:46 7-0052 -> ../../../../devices/pci0000:00/0000:00:1f.3/i2c-7/7-0052/
--w------- 1 root root 4096 Apr  4 01:47 bind
lrwxrwxrwx 1 root root    0 Apr  4 01:47 module -> ../../../../module/eeprom/
--w------- 1 root root 4096 Apr  4 01:46 uevent
--w------- 1 root root 4096 Apr  4 01:47 unbind
dan@orangexmg /etc/pacman.d ‹node v11.10.1›
```

#### look for SMBus

```sh
🐢  i2cdetect -l
i2c-3   unknown         i915 gmbus dpc                          N/A
i2c-1   unknown         i915 gmbus vga                          N/A
i2c-6   unknown         DPDDC-A                                 N/A
i2c-4   unknown         i915 gmbus dpb                          N/A
i2c-2   unknown         i915 gmbus panel                        N/A
i2c-0   unknown         i915 gmbus ssc                          N/A
i2c-7   unknown         SMBus I801 adapter at f040              N/A
i2c-5   unknown         i915 gmbus dpd                          N/A
```

```sh
🐢  i2cdetect -r 7
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-7 using receive byte commands.
I will probe address range 0x03-0x77.
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- --
50: UU -- UU -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
```

## RAM init
menuconfig:
Chipset ->
  Add a System Agent Binary
  (mrc.bin) Intel System Agent path and filename

To obtain it, see https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html
TL;DR:

```sh
make -C util/cbfstool
cd util/chromeos
./crosfirmware.sh peppy
../cbfstool/cbfstool coreboot-*.bin extract -f mrc.bin -n mrc.bin -r RO_SECTION
```

## VBT

### extract CSMCORE
UEFITool: search for string VBT, disable Unicode (!)

### find VBT position
r2, xxd:
  - search for `$VBT` and note down the address
  - find the end and note down the address
  - calculate the length

###
extract the region:
`dd if=Section_Raw_CSMCORE_CSMCORE_body.raw of=vbt.bin skip=254216 count=4400 bs=1`

### verify binary
`intelvbttool -f vbt.bin -d`

## debug output

Activate flash debug output:

menuconfig:
Console ->
  SPI Flash console output

CBFS generates fmap

### logs

```
coreboot-4.9-1225-g8f54cb2bd3 Thu Apr  4 18:12:07 UTC 2019 romstage starting (log level: 7)...
Disabling Watchdog reboot... done.
SMBus controller enabled.
Setting up static northbridge registers... done.
Started PEG10 link training.
Temporarily hiding PEG10.
Initializing IGD...
Back from haswell_early_initialization()
CPU id(306c3) ucode:00000000 Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz
AES supported, TXT NOT supported, VT supported
PCH type: HM87, device id: 8c4b, rev id 5
Starting UEFI PEI System Agent
FMAP: area RW_MRC_CACHE found @ 720000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
FMAP: area COREBOOT found @ 730200 (851456 bytes)
CBFS: Locating 'mrc.bin'
CBFS: Found @ offset 6fdc0 size 2e6e4
System Agent: Starting up...
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)
System Agent: Initializing PCH (SA Init)
System Agent: Initializing PCH (Me UMA)
System Agent: Initializing Memory
System Agent: Done.
Sanity checking heap.
```

## TODO

- find ucode updates ( https://downloadcenter.intel.com/download/28087/Linux-Processor-Microcode-Data-File )

EC: SCH5317