fulladder_tc.v

`timescale 1ns/1ps

module fulladder_tc;
reg ain,bin,cin;
wire cout,sout;

initial begin
     $dumpfile("wave.vcd");
     $dumpvars(0, fulladder_u);
     $monitor("ain:%d,bin:%d,cin:%d,cout:%d,sout:%d", ain,bin,cin,cout,sout);
end

fulladder fulladder_u(.ain(ain),.bin(bin),.cin(cin),.cout(cout),.sout(sout));

initial begin
  #0 ain = 0; bin = 0; cin = 0;
  #100 ain = 0; bin = 0; cin = 1;
  #100 ain = 0; bin = 1; cin = 0;
  #100 ain = 0; bin = 1; cin = 1;
  #100 ain = 1; bin = 0; cin = 0;
  #100 ain = 1; bin = 0; cin = 1;
  #100 ain = 1; bin = 1; cin = 0;
  #100 ain = 1; bin = 1; cin = 1;
  $finish;
end

endmodule