Comparison of different register naming convention

reg-style-compare.c

/*
 * Convention 1: Freescale style
 */

/* register address */
unsigned long ctrl_addr = HW_ICOLL_CTRL_ADDR; /* get address */
/* read/write register */
unsigned long value = HW_ICOLL_STATUS; /* read */
HW_ICOLL_STATUS = value; /* write */
/* fields define */
unsigned bit_pos_of_field = BP_ICOLL_ENABLE_TYPE; /* for example 16 */
unsigned bit_mask_of_field = BM_ICOLL_ENABLE_TYPE; /* for example 0x30000 */
/* producing a value for a field */
unsigned field_value = BF_ICOLL_ENABLE_TYPE(2); /* gives ((2) << BP_ICOLL_ENABLE_TYPE) & BM_ICOLL_ENABLE_TYPE */
/* some field have named values */
unsigned named_field_value = BV_ICOLL_ENABLE_TYPE_FIQ; /* would be 2 */
/* one can produce such valus using the _V suffix */
unsigned field_value = BF_ICOLL_ENABLE_TYPE_V(FIQ); /* gives BF_ICOLL_ENABLE_TYPE(BV_ICOLL_ENABLE_TYPE_FIQ) */
/* ORing several fields */
unsigned val = BF_OR(ICOLL_ENABLE, TYPE_V(FIQ), PRIO(3), TZ(1)); /* same as BF_ICOLL_ENABLE_TYPE_V(FIQ) | BF_ICOLL_ENABLE_PRIO(3) | ... */
unsigned mask = BM_OR(ICOLL_ENABLE, TYPE, PRIO, TZ); /* same as BM_ICOLL_ENABLE_TYPE | BM_ICOLL_ENABLE_PRIO | ... */
/* reading a register and extracting one field */
unsigned long status = BR_ICOLL_STATUS(PENDING);
/* writing to a register using field ORing:
 * BW_reg(index, fields) is the same as HW_REG(index) = BF_OR(reg, fields);
 * BM_reg(index, fields) is the same as HW_REG(index) = BM_OR(reg, fields);
 */
BW_ICOLL_CLR(STATUS(status)); /* (clear interrupt) write register (CLR variant) */
BM_ICOLL_CTRL_CLR(SFTRST, CLKGATE);
BW_ICOLL_CTRL(TZ_LOCK_V(LOCKED));
/* you can do any combination of the above, using indexes too */
BW_ICOLL_ENABLE(10, CPU0_TZ(1), CPU0_TYPE_V(FIQ), CPU0_PRIO_V(NMI), CPU1_PRIO_V(MASKED), CPU2_PRIO_V(MASKED), CPU3_PRIO_V(MASKED));
/* can even have several indices */
unsigned value = BR_CPU_GPIO_PORT_IN(10, 7, VALUE);
BW_CPU_GPIO_PORT_OE_SET(12, 3, ENABLE(0x5f), MASK(0x5f));
/* writing one or more fields (read-modify-write) */
BF_WR(ICOLL_ENABLE, CPU0_TZ(1), CPU0_TYPE_V(FIQ), CPU0_PRIO_V(NMI), CPU1_PRIO_V(MASKED), CPU2_PRIO_V(MASKED), CPU3_PRIO_V(MASKED));

/*
 * Convention 2: experiment A
 */
/* unchanged: BP_*, BM_*, BV_* */
jz_orf(ICOLL_ENABLE, TYPE_V(FIQ), PRIO(3), TZ(1)); /* same as BF_OR */
jz_orm(ICOLL_ENABLE, TYPE, PRIO, TZ); /* same as BM_OR */
jz_read(ICOLL_CTRL); /* read register */
jz_read(GPIO_OUT(3, 5)); /* read with index */
jz_write(ICOLL_CTRL, value); /* write register */
jz_write(GPIO_OUT(3, 5), value); /* write register with index */
jz_readf(ICOLL_STATUS, PENDING); /* read field */
jz_readf(SSP_CTRL(1), BUSY); /* read field with index */
jz_writef(ICOLL_ENABLE, TZ(1), TYPE_V(FIQ), PRIO_V(NMI)); /* read-modify-write */
jz_writef(SSP_CTRL(1), MODE_V(SD), WIDTH_V(4), DIV(32)); /* read-modify-write with index */
jz_write(ICOLL_ENABLE_SET, 0x33);
jz_write(ICOLL_ENABLE_CLR, 0x33);
jz_overwritef(ICOLL_ENABLE_SET, TZ(1), TYPE_V(FIQ), PRIO_V(NMI)); /* write an OR of fields */
jz_setf(DMA_CTRL, KICK(1), SEMA(1)); /* shortcut for jz_worf for the _SET variant, or jw_writef is there is not SET variant */
jz_clrf(DMA_CTRL, KICK(1), SEMA(1)); /* shortcut for jz_worf for the _SET variant, or jw_writef is there is not CLR variant */
jz_csf(DMA_CTRL, KICK(1), SEMA(1)); /* equivalent of jz_clrm(DMA_CTRL, KICK, SEMA) followed by jz_setf(DMA_CTRL, KICK(1), SEMA(1)) */