header file

regs-int.h

/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * vsoc2000 version: 0.5
 * vsoc2000 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_VSOC2000_REGS_INT_H__
#define __HEADERGEN_VSOC2000_REGS_INT_H__

#define HW_ICOLL_CTRL_ADDR              (0x80000000 + 0x0)
#define HW_ICOLL_CTRL                   (*(volatile uint8_t *)HW_ICOLL_CTRL_ADDR)
#define BW_ICOLL_CTRL(...)              HW_ICOLL_CTRL = BF_OR(ICOLL_CTRL, __VA_ARGS__)
#define BR_ICOLL_CTRL(_f)               ((HW_ICOLL_CTRL & BM_ICOLL_CTRL_##_f) & BP_ICOLL_CTRL_##_f)
#define HW_ICOLL_CTRL_SET_ADDR          (HW_ICOLL_CTRL_ADDR + 0x4)
#define HW_ICOLL_CTRL_SET               (*(volatile uint8_t *)HW_ICOLL_CTRL_SET_ADDR)
#define BW_ICOLL_CTRL_SET(...)          HW_ICOLL_CTRL_SET = BF_OR(ICOLL_CTRL, __VA_ARGS__)
#define BR_ICOLL_CTRL_SET(_f)           ((HW_ICOLL_CTRL_SET & BM_ICOLL_CTRL_##_f) & BP_ICOLL_CTRL_##_f)
#define HW_ICOLL_CTRL_CLR_ADDR          (HW_ICOLL_CTRL_ADDR + 0x8)
#define HW_ICOLL_CTRL_CLR               (*(volatile uint8_t *)HW_ICOLL_CTRL_CLR_ADDR)
#define BW_ICOLL_CTRL_CLR(...)          HW_ICOLL_CTRL_CLR = BF_OR(ICOLL_CTRL, __VA_ARGS__)
#define BR_ICOLL_CTRL_CLR(_f)           ((HW_ICOLL_CTRL_CLR & BM_ICOLL_CTRL_##_f) & BP_ICOLL_CTRL_##_f)
#define BP_ICOLL_CTRL_CLKGATE           7
#define BM_ICOLL_CTRL_CLKGATE           0x80
#define BF_ICOLL_CTRL_CLKGATE(_v)       (((_v) << BP_ICOLL_CTRL_CLKGATE) & BM_ICOLL_CTRL_CLKGATE)
#define BF_ICOLL_CTRL_CLKGATE_V(_e)     BF_ICOLL_CTRL_CLKGATE(BV_ICOLL_CTRL_CLKGATE__##_e)
#define BP_ICOLL_CTRL_SFTRST            6
#define BM_ICOLL_CTRL_SFTRST            0x40
#define BF_ICOLL_CTRL_SFTRST(_v)        (((_v) << BP_ICOLL_CTRL_SFTRST) & BM_ICOLL_CTRL_SFTRST)
#define BF_ICOLL_CTRL_SFTRST_V(_e)      BF_ICOLL_CTRL_SFTRST(BV_ICOLL_CTRL_SFTRST__##_e)
#define BP_ICOLL_CTRL_TZ_LOCK           5
#define BM_ICOLL_CTRL_TZ_LOCK           0x20
#define BV_ICOLL_CTRL_TZ_LOCK__UNLOCKED 0x0
#define BV_ICOLL_CTRL_TZ_LOCK__LOCKED   0x1
#define BF_ICOLL_CTRL_TZ_LOCK(_v)       (((_v) << BP_ICOLL_CTRL_TZ_LOCK) & BM_ICOLL_CTRL_TZ_LOCK)
#define BF_ICOLL_CTRL_TZ_LOCK_V(_e)     BF_ICOLL_CTRL_TZ_LOCK(BV_ICOLL_CTRL_TZ_LOCK__##_e)

#define HW_ICOLL_STATUS_ADDR            (0x80000000 + 0x10)
#define HW_ICOLL_STATUS                 (*(volatile uint32_t *)HW_ICOLL_STATUS_ADDR)
#define BW_ICOLL_STATUS(...)            HW_ICOLL_STATUS = BF_OR(ICOLL_STATUS, __VA_ARGS__)
#define BR_ICOLL_STATUS(_f)             ((HW_ICOLL_STATUS & BM_ICOLL_STATUS_##_f) & BP_ICOLL_STATUS_##_f)
#define HW_ICOLL_STATUS_CLR_ADDR        (HW_ICOLL_STATUS_ADDR + 0x8)
#define HW_ICOLL_STATUS_CLR             (*(volatile uint32_t *)HW_ICOLL_STATUS_CLR_ADDR)
#define BW_ICOLL_STATUS_CLR(...)        HW_ICOLL_STATUS_CLR = BF_OR(ICOLL_STATUS, __VA_ARGS__)
#define BR_ICOLL_STATUS_CLR(_f)         ((HW_ICOLL_STATUS_CLR & BM_ICOLL_STATUS_##_f) & BP_ICOLL_STATUS_##_f)
#define BP_ICOLL_STATUS_STATUS          0
#define BM_ICOLL_STATUS_STATUS          0xffffffff
#define BF_ICOLL_STATUS_STATUS(_v)      (((_v) << BP_ICOLL_STATUS_STATUS) & BM_ICOLL_STATUS_STATUS)
#define BF_ICOLL_STATUS_STATUS_V(_e)    BF_ICOLL_STATUS_STATUS(BV_ICOLL_STATUS_STATUS__##_e)

#define HW_ICOLL_ENABLE_ADDR(_n1)           (0x80000000 + 0x20 + (_n1) * 0x10)
#define HW_ICOLL_ENABLE(_n1)                (*(volatile uint16_t *)HW_ICOLL_ENABLE_ADDR(_n1))
#define BW_ICOLL_ENABLE(_n1,...)            HW_ICOLL_ENABLE(_n1) = BF_OR(ICOLL_ENABLE, __VA_ARGS__)
#define BR_ICOLL_ENABLE(_n1,_f)             ((HW_ICOLL_ENABLE(_n1) & BM_ICOLL_ENABLE_##_f) & BP_ICOLL_ENABLE_##_f)
#define HW_ICOLL_ENABLE_SET_ADDR(_n1)       (HW_ICOLL_ENABLE_ADDR(_n1) + 0x4)
#define HW_ICOLL_ENABLE_SET(_n1)            (*(volatile uint16_t *)HW_ICOLL_ENABLE_SET_ADDR(_n1))
#define BW_ICOLL_ENABLE_SET(_n1,...)        HW_ICOLL_ENABLE_SET(_n1) = BF_OR(ICOLL_ENABLE, __VA_ARGS__)
#define BR_ICOLL_ENABLE_SET(_n1,_f)         ((HW_ICOLL_ENABLE_SET(_n1) & BM_ICOLL_ENABLE_##_f) & BP_ICOLL_ENABLE_##_f)
#define HW_ICOLL_ENABLE_CLR_ADDR(_n1)       (HW_ICOLL_ENABLE_ADDR(_n1) + 0x8)
#define HW_ICOLL_ENABLE_CLR(_n1)            (*(volatile uint16_t *)HW_ICOLL_ENABLE_CLR_ADDR(_n1))
#define BW_ICOLL_ENABLE_CLR(_n1,...)        HW_ICOLL_ENABLE_CLR(_n1) = BF_OR(ICOLL_ENABLE, __VA_ARGS__)
#define BR_ICOLL_ENABLE_CLR(_n1,_f)         ((HW_ICOLL_ENABLE_CLR(_n1) & BM_ICOLL_ENABLE_##_f) & BP_ICOLL_ENABLE_##_f)
#define BP_ICOLL_ENABLE_CPU3_PRIO           14
#define BM_ICOLL_ENABLE_CPU3_PRIO           0xc000
#define BV_ICOLL_ENABLE_CPU3_PRIO__MASKED   0x0
#define BV_ICOLL_ENABLE_CPU3_PRIO__LOW      0x1
#define BV_ICOLL_ENABLE_CPU3_PRIO__HIGH     0x2
#define BV_ICOLL_ENABLE_CPU3_PRIO__NMI      0x3
#define BF_ICOLL_ENABLE_CPU3_PRIO(_v)       (((_v) << BP_ICOLL_ENABLE_CPU3_PRIO) & BM_ICOLL_ENABLE_CPU3_PRIO)
#define BF_ICOLL_ENABLE_CPU3_PRIO_V(_e)     BF_ICOLL_ENABLE_CPU3_PRIO(BV_ICOLL_ENABLE_CPU3_PRIO__##_e)
#define BP_ICOLL_ENABLE_CPU3_TYPE           13
#define BM_ICOLL_ENABLE_CPU3_TYPE           0x2000
#define BV_ICOLL_ENABLE_CPU3_TYPE__IRQ      0x0
#define BV_ICOLL_ENABLE_CPU3_TYPE__FIQ      0x1
#define BF_ICOLL_ENABLE_CPU3_TYPE(_v)       (((_v) << BP_ICOLL_ENABLE_CPU3_TYPE) & BM_ICOLL_ENABLE_CPU3_TYPE)
#define BF_ICOLL_ENABLE_CPU3_TYPE_V(_e)     BF_ICOLL_ENABLE_CPU3_TYPE(BV_ICOLL_ENABLE_CPU3_TYPE__##_e)
#define BP_ICOLL_ENABLE_CPU3_TZ             12
#define BM_ICOLL_ENABLE_CPU3_TZ             0x1000
#define BF_ICOLL_ENABLE_CPU3_TZ(_v)         (((_v) << BP_ICOLL_ENABLE_CPU3_TZ) & BM_ICOLL_ENABLE_CPU3_TZ)
#define BF_ICOLL_ENABLE_CPU3_TZ_V(_e)       BF_ICOLL_ENABLE_CPU3_TZ(BV_ICOLL_ENABLE_CPU3_TZ__##_e)
#define BP_ICOLL_ENABLE_CPU2_PRIO           10
#define BM_ICOLL_ENABLE_CPU2_PRIO           0xc00
#define BV_ICOLL_ENABLE_CPU2_PRIO__MASKED   0x0
#define BV_ICOLL_ENABLE_CPU2_PRIO__LOW      0x1
#define BV_ICOLL_ENABLE_CPU2_PRIO__HIGH     0x2
#define BV_ICOLL_ENABLE_CPU2_PRIO__NMI      0x3
#define BF_ICOLL_ENABLE_CPU2_PRIO(_v)       (((_v) << BP_ICOLL_ENABLE_CPU2_PRIO) & BM_ICOLL_ENABLE_CPU2_PRIO)
#define BF_ICOLL_ENABLE_CPU2_PRIO_V(_e)     BF_ICOLL_ENABLE_CPU2_PRIO(BV_ICOLL_ENABLE_CPU2_PRIO__##_e)
#define BP_ICOLL_ENABLE_CPU2_TYPE           9
#define BM_ICOLL_ENABLE_CPU2_TYPE           0x200
#define BV_ICOLL_ENABLE_CPU2_TYPE__IRQ      0x0
#define BV_ICOLL_ENABLE_CPU2_TYPE__FIQ      0x1
#define BF_ICOLL_ENABLE_CPU2_TYPE(_v)       (((_v) << BP_ICOLL_ENABLE_CPU2_TYPE) & BM_ICOLL_ENABLE_CPU2_TYPE)
#define BF_ICOLL_ENABLE_CPU2_TYPE_V(_e)     BF_ICOLL_ENABLE_CPU2_TYPE(BV_ICOLL_ENABLE_CPU2_TYPE__##_e)
#define BP_ICOLL_ENABLE_CPU2_TZ             8
#define BM_ICOLL_ENABLE_CPU2_TZ             0x100
#define BF_ICOLL_ENABLE_CPU2_TZ(_v)         (((_v) << BP_ICOLL_ENABLE_CPU2_TZ) & BM_ICOLL_ENABLE_CPU2_TZ)
#define BF_ICOLL_ENABLE_CPU2_TZ_V(_e)       BF_ICOLL_ENABLE_CPU2_TZ(BV_ICOLL_ENABLE_CPU2_TZ__##_e)
#define BP_ICOLL_ENABLE_CPU1_PRIO           6
#define BM_ICOLL_ENABLE_CPU1_PRIO           0xc0
#define BV_ICOLL_ENABLE_CPU1_PRIO__MASKED   0x0
#define BV_ICOLL_ENABLE_CPU1_PRIO__LOW      0x1
#define BV_ICOLL_ENABLE_CPU1_PRIO__HIGH     0x2
#define BV_ICOLL_ENABLE_CPU1_PRIO__NMI      0x3
#define BF_ICOLL_ENABLE_CPU1_PRIO(_v)       (((_v) << BP_ICOLL_ENABLE_CPU1_PRIO) & BM_ICOLL_ENABLE_CPU1_PRIO)
#define BF_ICOLL_ENABLE_CPU1_PRIO_V(_e)     BF_ICOLL_ENABLE_CPU1_PRIO(BV_ICOLL_ENABLE_CPU1_PRIO__##_e)
#define BP_ICOLL_ENABLE_CPU1_TYPE           5
#define BM_ICOLL_ENABLE_CPU1_TYPE           0x20
#define BV_ICOLL_ENABLE_CPU1_TYPE__IRQ      0x0
#define BV_ICOLL_ENABLE_CPU1_TYPE__FIQ      0x1
#define BF_ICOLL_ENABLE_CPU1_TYPE(_v)       (((_v) << BP_ICOLL_ENABLE_CPU1_TYPE) & BM_ICOLL_ENABLE_CPU1_TYPE)
#define BF_ICOLL_ENABLE_CPU1_TYPE_V(_e)     BF_ICOLL_ENABLE_CPU1_TYPE(BV_ICOLL_ENABLE_CPU1_TYPE__##_e)
#define BP_ICOLL_ENABLE_CPU1_TZ             4
#define BM_ICOLL_ENABLE_CPU1_TZ             0x10
#define BF_ICOLL_ENABLE_CPU1_TZ(_v)         (((_v) << BP_ICOLL_ENABLE_CPU1_TZ) & BM_ICOLL_ENABLE_CPU1_TZ)
#define BF_ICOLL_ENABLE_CPU1_TZ_V(_e)       BF_ICOLL_ENABLE_CPU1_TZ(BV_ICOLL_ENABLE_CPU1_TZ__##_e)
#define BP_ICOLL_ENABLE_CPU0_PRIO           2
#define BM_ICOLL_ENABLE_CPU0_PRIO           0xc
#define BV_ICOLL_ENABLE_CPU0_PRIO__MASKED   0x0
#define BV_ICOLL_ENABLE_CPU0_PRIO__LOW      0x1
#define BV_ICOLL_ENABLE_CPU0_PRIO__HIGH     0x2
#define BV_ICOLL_ENABLE_CPU0_PRIO__NMI      0x3
#define BF_ICOLL_ENABLE_CPU0_PRIO(_v)       (((_v) << BP_ICOLL_ENABLE_CPU0_PRIO) & BM_ICOLL_ENABLE_CPU0_PRIO)
#define BF_ICOLL_ENABLE_CPU0_PRIO_V(_e)     BF_ICOLL_ENABLE_CPU0_PRIO(BV_ICOLL_ENABLE_CPU0_PRIO__##_e)
#define BP_ICOLL_ENABLE_CPU0_TYPE           1
#define BM_ICOLL_ENABLE_CPU0_TYPE           0x2
#define BV_ICOLL_ENABLE_CPU0_TYPE__IRQ      0x0
#define BV_ICOLL_ENABLE_CPU0_TYPE__FIQ      0x1
#define BF_ICOLL_ENABLE_CPU0_TYPE(_v)       (((_v) << BP_ICOLL_ENABLE_CPU0_TYPE) & BM_ICOLL_ENABLE_CPU0_TYPE)
#define BF_ICOLL_ENABLE_CPU0_TYPE_V(_e)     BF_ICOLL_ENABLE_CPU0_TYPE(BV_ICOLL_ENABLE_CPU0_TYPE__##_e)
#define BP_ICOLL_ENABLE_CPU0_TZ             0
#define BM_ICOLL_ENABLE_CPU0_TZ             0x1
#define BF_ICOLL_ENABLE_CPU0_TZ(_v)         (((_v) << BP_ICOLL_ENABLE_CPU0_TZ) & BM_ICOLL_ENABLE_CPU0_TZ)
#define BF_ICOLL_ENABLE_CPU0_TZ_V(_e)       BF_ICOLL_ENABLE_CPU0_TZ(BV_ICOLL_ENABLE_CPU0_TZ__##_e)

#endif /* __HEADERGEN_VSOC2000_REGS_INT_H__*/