counter verilog example.

counter.v

module counter # (
    parameter width = 4
) (
        input   clk,
        input   rstn,
        output  reg [width - 1:0]       out
);
    always @ (posedge clk) begin
        if (!rstn) begin
            out <= out + 1;
        end else
            out <= 0;
    end

endmodule

counter_tb.v

module counter_tb;
    localparam width = 4;

    reg clk;
    reg rstn;
    wire [width - 1:0] out;

    always #1 clk = ~clk;
    
    counter #(
        .width (width)
    ) COUNTER (
        .clk(clk),
        .rstn(rstn),
        .out(out)
    );

    initial begin
        $display("Initialize to 0.");
        clk = 0;
        rstn = 0;

        $monitor ("[%0t] rstn=0x%0h out=0x%0h", $time, rstn, out);

        #10 rstn <= 1;
        #30 rstn <= 0;
        #70 rstn <= 1;
        #95 rstn <= 0;

        $dumpfile("counter_tb.vcd");
        $dumpvars(0, counter_tb); // all vars dump

        #100 $finish;
    end 

endmodule