paranlee · December 5, 2021 15:13
diff --git a/fulladder.v b/fulladder.v
 module fulladder #(
    parameter width = 2
 ) (
    input [width:0] a,
    input [width:0] b,
    input c_in,
    output c_out,
    output [width:0] sum
 );

    assign { c_out, sum } = a + b + c_in;

 endmodule
diff --git a/iverilog.sh b/iverilog.sh
 iverilog -o fulladder.o fulladder.v
	module fulladder #(
	parameter width = 2
	) (
	input [width:0] a,
	input [width:0] b,
	input c_in,
	output c_out,
	output [width:0] sum
	);

	assign { c_out, sum } = a + b + c_in;

	endmodule
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