pashu123
/ embedding_to_f16.mlir
Created
April 30, 2024 17:00
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| module { | |
| func.func @decode_bs4(%arg0: !torch.vtensor<[4,?],si64>, %arg1: !torch.vtensor<[128256,4096],f16>) -> !torch.vtensor<[4,?,4096],f32> { | |
| %false = torch.constant.bool false | |
| %false_0 = torch.constant.bool false | |
| %int-1 = torch.constant.int -1 | |
| %int6 = torch.constant.int 6 | |
| %0 = torch.prims.convert_element_type %arg1, %int6 : !torch.vtensor<[128256,4096],f16>, !torch.int -> !torch.vtensor<[128256,4096],f32> | |
| %1 = torch.aten.embedding %0, %arg0, %int-1, %false_0, %false : !torch.vtensor<[128256,4096],f32>, !torch.vtensor<[4,?],si64>, !torch.int, !torch.bool, !torch.bool -> !torch.vtensor<[4,?,4096],f32> | |
| return %1 : !torch.vtensor<[4,?,4096],f32> | |
| } |
pashu123
/ batch_llama_3_8B.mlir
Created
April 30, 2024 16:12
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| #map = affine_map<(d0, d1, d2) -> (d1, d2)> | |
| #map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)> | |
| module @module { | |
| util.global private @__auto.token_embd.weight = #stream.parameter.named<"model"::"token_embd.weight"> : tensor<128256x4096xf16> | |
| util.global private @__auto.blk.0.attn_norm.weight = #stream.parameter.named<"model"::"blk.0.attn_norm.weight"> : tensor<4096xf32> | |
| util.global private @__auto.blk.0.attn_q.weight = #stream.parameter.named<"model"::"blk.0.attn_q.weight"> : tensor<4096x4096xf16> | |
| util.global private @__auto.blk.0.attn_k.weight = #stream.parameter.named<"model"::"blk.0.attn_k.weight"> : tensor<1024x4096xf16> | |
| util.global private @__auto.blk.0.attn_v.weight = #stream.parameter.named<"model"::"blk.0.attn_v.weight"> : tensor<1024x4096xf16> | |
| util.global private @__auto.constant_8192_64_torch.complex64 = dense_resource<__auto.constant_8192_64_torch.complex64> : tensor<8192x64xcomplex<f32>> | |
| util.global private @__auto.blk.0.attn_output.weight = #stream.parameter.named<"model"::"blk.0.attn_o |
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| import math | |
| def fma(a, b, c): | |
| return a * b + c | |
| def asin_core(a): | |
| s = a * a | |
| q = s * s | |
| r = 5.5579749017470502e-2 | |
| t = -6.2027913464120114e-2 |
pashu123
/ asm_broadcast.s
Created
April 24, 2024 13:03
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| .text | |
| .intel_syntax noprefix | |
| .file "broadcast_dispatch_0" | |
| .section .text.broadcast_dispatch_0_generic_Dx8640x3200_f16,"ax",@progbits | |
| .p2align 4, 0x90 | |
| .type broadcast_dispatch_0_generic_Dx8640x3200_f16,@function | |
| broadcast_dispatch_0_generic_Dx8640x3200_f16: | |
| .Lfunc_begin0: | |
| .file 1 "-" | |
| .loc 1 1 0 |
pashu123
/ only_broadcast.mlir
Created
April 24, 2024 13:02
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| // -----// IR Dump After AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- // | |
| #executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu = "znver4", cpu_features = "+prfchw,-cldemote,+avx,+aes,+sahf,+pclmul,-xop,+crc32,+xsaves,-avx512fp16,-usermsr,-sm4,-egpr,+sse4.1,+avx512ifma,+xsave,-avx512pf,+sse4.2,-tsxldtrk,-ptwrite,-widekl,-sm3,+invpcid,+64bit,+xsavec,-avx10.1-512,+avx512vpopcntdq,+cmov,-avx512vp2intersect,+avx512cd,+movbe,-avxvnniint8,-avx512er,-ccmp,-amx-int8,-kl,-avx10.1-256,-sha512,-avxvnni,-rtm,+adx,+avx2,-hreset,-movdiri,-serialize,+vpclmulqdq,+avx512vl,-uintr,-cf,+clflushopt,-raoint,-cmpccxadd,+bmi,-amx-tile,+sse,+gfni,-avxvnniint16,-amx-fp16,-ndd,+xsaveopt,+rdrnd,+avx512f,-amx-bf16,+avx512bf16,+avx512vnni,-push2pop2,+cx8,+avx512bw,+sse3,+pku,+fsgsbase,+clzero,+mwaitx,-lwp,+lzcnt,+sha,-movdir64b,-ppx,+wbnoinvd,-enqcmd,-prefetchwt1,-avxneconvert,-tbm,-pconfig,-amx-complex,+ssse3,+cx16,+bmi2,+fma,+popcnt,-avxifma,+f16c,+avx512bitalg,+rdpr |
pashu123
/ only_pack.mlir
Created
April 24, 2024 12:58
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| // -----// IR Dump After AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- // | |
| #executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu = "znver4", cpu_features = "+prfchw,-cldemote,+avx,+aes,+sahf,+pclmul,-xop,+crc32,+xsaves,-avx512fp16,-usermsr,-sm4,-egpr,+sse4.1,+avx512ifma,+xsave,-avx512pf,+sse4.2,-tsxldtrk,-ptwrite,-widekl,-sm3,+invpcid,+64bit,+xsavec,-avx10.1-512,+avx512vpopcntdq,+cmov,-avx512vp2intersect,+avx512cd,+movbe,-avxvnniint8,-avx512er,-ccmp,-amx-int8,-kl,-avx10.1-256,-sha512,-avxvnni,-rtm,+adx,+avx2,-hreset,-movdiri,-serialize,+vpclmulqdq,+avx512vl,-uintr,-cf,+clflushopt,-raoint,-cmpccxadd,+bmi,-amx-tile,+sse,+gfni,-avxvnniint16,-amx-fp16,-ndd,+xsaveopt,+rdrnd,+avx512f,-amx-bf16,+avx512bf16,+avx512vnni,-push2pop2,+cx8,+avx512bw,+sse3,+pku,+fsgsbase,+clzero,+mwaitx,-lwp,+lzcnt,+sha,-movdir64b,-ppx,+wbnoinvd,-enqcmd,-prefetchwt1,-avxneconvert,-tbm,-pconfig,-amx-complex,+ssse3,+cx16,+bmi2,+fma,+popcnt,-avxifma,+f16c,+avx512bitalg,+rdpr |
pashu123
/ only_pack_1_1_16.s
Created
April 24, 2024 11:25
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| .text | |
| .intel_syntax noprefix | |
| .file "pack_dispatch_0" | |
| .section .rodata.cst32,"aM",@progbits,32 | |
| .p2align 5, 0x0 | |
| .LCPI0_0: | |
| .short 0 | |
| .short 16 | |
| .short 1 | |
| .short 17 |
pashu123
/ module_broadcast_pack_kernel_dispatch_0_embedded_elf_x86_64.s
Created
April 23, 2024 18:36
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| .text | |
| .intel_syntax noprefix | |
| .file "broadcast_pack_kernel_dispatch_0" | |
| .section .rodata.cst32,"aM",@progbits,32 | |
| .p2align 5, 0x0 | |
| .LCPI0_0: | |
| .short 0 | |
| .short 16 | |
| .short 1 | |
| .short 17 |
pashu123
/ tmp_ir.mlir
Created
April 23, 2024 18:32
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| // -----// IR Dump After AssignTargetDevicesPass (iree-hal-assign-target-devices) //----- // | |
| #executable_target_embedded_elf_x86_64_ = #hal.executable.target<"llvm-cpu", "embedded-elf-x86_64", {cpu = "znver4", cpu_features = "+prfchw,-cldemote,+avx,+aes,+sahf,+pclmul,-xop,+crc32,+xsaves,-avx512fp16,-usermsr,-sm4,-egpr,+sse4.1,+avx512ifma,+xsave,-avx512pf,+sse4.2,-tsxldtrk,-ptwrite,-widekl,-sm3,+invpcid,+64bit,+xsavec,-avx10.1-512,+avx512vpopcntdq,+cmov,-avx512vp2intersect,+avx512cd,+movbe,-avxvnniint8,-avx512er,-ccmp,-amx-int8,-kl,-avx10.1-256,-sha512,-avxvnni,-rtm,+adx,+avx2,-hreset,-movdiri,-serialize,+vpclmulqdq,+avx512vl,-uintr,-cf,+clflushopt,-raoint,-cmpccxadd,+bmi,-amx-tile,+sse,+gfni,-avxvnniint16,-amx-fp16,-ndd,+xsaveopt,+rdrnd,+avx512f,-amx-bf16,+avx512bf16,+avx512vnni,-push2pop2,+cx8,+avx512bw,+sse3,+pku,+fsgsbase,+clzero,+mwaitx,-lwp,+lzcnt,+sha,-movdir64b,-ppx,+wbnoinvd,-enqcmd,-prefetchwt1,-avxneconvert,-tbm,-pconfig,-amx-complex,+ssse3,+cx16,+bmi2,+fma,+popcnt,-avxifma,+f16c,+avx512bitalg,+rdpr |
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| %19 = scf.for %arg3 = %c0 to %11 step %c1 iter_args(%arg4 = %16) -> (tensor<?x4x64x16x1xf16>) { | |
| %20 = scf.for %arg5 = %c0 to %c4 step %c1 iter_args(%arg6 = %arg4) -> (tensor<?x4x64x16x1xf16>) { | |
| %21 = scf.for %arg7 = %c0 to %c64 step %c1 iter_args(%arg8 = %arg6) -> (tensor<?x4x64x16x1xf16>) { | |
| %22 = affine.apply affine_map<(d0) -> (d0 * 16)>(%arg5) | |
| %extracted_slice = tensor.extract_slice %18[%22, %arg7] [16, 1] [1, 1] : tensor<64x64xf16> to tensor<16x1xf16> | |
| %23 = tensor.empty() : tensor<1x16x1xf16> | |
| %24 = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1, d2)>], iterator_types = ["parallel", "parallel", "parallel"]} ins(%extracted_slice : tensor<16x1xf16>) outs(%23 : tensor<1x16x1xf16>) attrs = {lowering_config = #iree_codegen.lowering_config<tile_sizes = [[64, 64, 64], [1, 16, 1], [0, 0, 0], [0, 0, 0]]>} { | |
| ^bb0(%in: f16, %out: f16): | |
| linalg.y |