Coding Challenge for LFX Mentorship Fall-2022.

Questions

The first task is mandatory and selection will be based on the performance in the task. The second task is optional and a nice to have.

Write a python program which takes a valid RISC-V ISA string(described in Chapter 27 of the RISC-V specification(unpriv)) and generates coverpoints for each of the relevant bits in the extension field of misa register described in section 3.1.1 of the RISC-V privileged ISA. Briefly describe the events (i.e list out the possible exceptions and why) in the test which will occur while testing one such coverpoint. Refer to the csr_comb node described here to understand the format for the coverpoints. Example: for RV32IM, two relevant coverpoints are to check whether the bit at index 12 of misa is 0 and 1(misa && 0x1000 == 0x1000). Note - You can restrict yourself to list of ratified extensions for the sake of this task. The program need not check for the validity of the ISA string.
Write an assembly test which covers one of the coverpoints generated above. Bonus points if the test contains a trap handler.

All the files should contain your name/email address. This will help identify your submission.
Any additional information to be included can be mentioned in markdown files(like the description in task 1).
(Preferred) Create a github repository and check in all the files for submission over there. Raise an issue in the repository(the one which you have created) and tag @pawks and @neelgala indicating that it is ready for review. Please do not raise any issues to the RISCV repositories.
- Creating a repository - https://docs.github.com/en/get-started/quickstart/create-a-repo
- Creating an issue - https://docs.github.com/en/issues/tracking-your-work-with-issues/creating-an-issue
All submissions should be complete by August 3, 2022, 23:59(AOE).

What is a coverpoint? A coverpoint specifies a boolean expression over the fields of an architectural element(instruction/state) that is required to be satisfied at least once during execution. The fields which can be used in the expression varies based on the type of the coverpoint. For example, a rs2 coverpoint specifies that atleast one instruction of the given opcode should have the rs2 field set to the register(x2) specified in the coverpoint. More information about the different types of coverpoints and the available variables can be found here.
I need further clarifications on the challenge. How can I contact you? Create a new issue here. Make sure to check other issues to verify that the same query hasn't been answered already.