yosys/ghdl -> verilog (VHDL to Verilog with Yosys & GHDL)

gistfile1.txt

# make sure it's python 2.7
sudo update-alternatives --config python

# build ghdl
sudo apt install -y git make gnat zlib1g-dev
git clone https://github.com/ghdl/ghdl
cd ghdl
./configure --prefix=/usr/local
make
sudo make install

# build ghdl-yosys-plugin
git clone https://github.com/ghdl/ghdl-yosys-plugin
cd ghdl-yosys-plugin
make
sudo mkdir /usr/local/share/yosys/plugins
sudo cp ghdl.so /usr/local/share/yosys/plugins

# convert vhdl files
ls test
- ctc.vhdl
- ctc_channel.vhdl

# create .cf file
cd test
ghdl -a *.vhd

# load and compile
yosys -m ghdl
yosys> ghdl ctc
yosys> proc; opt; fsm; opt; memory; opt;

# write verilog
yosys> write_verilog ctc

ghdl synth --out=verilog
for example: ghdl synth --ieee=synopsys -fexplicit --out=verilog vdp > vdp.v
or:
ghdl -a --std=08 P65816_pkg.vhd BCDAdder.vhd AddSubBCD.vhd AddrGen.vhd MCode.vhd P65C816.vhd ALU.vhd
ghdl synth --std=08 --out=verilog P65C816 > P65C816.v