OpenSBI Mailing List Digest, 2026-Jan through 2026-May

Source: ~/opensbi-mail-archive/2026-{January,February,March,April,May}.txt. Approximately 526 messages across five months, with ~76 from Anup Patel (de-facto maintainer) leading review, and substantial new platform/feature work landing or in flight.

The digest is organized by topic. The first section is a deep dive on Tenstorrent contributors, since the reader is at Tenstorrent and asked for detail there. Subsequent sections cover the broader upstream picture so a NotebookLM "deep dive" episode has enough scaffolding to draw connections, debates, and architectural threads.

1. Tenstorrent contributors

Three Tenstorrent participants on the OpenSBI list during this window: Nicholas Piggin ([email protected], the long-time Linux MM/PowerPC kernel hacker), Evgeny Voevodin ([email protected] / @oss.tenstorrent.com), and Anirudh Srinivasan ([email protected]). Their work is largely converging on bring-up of the Tenstorrent Atlantis SoC.

1.1 Nicholas Piggin — Atlantis platform, dbtr fixes, PMP refactor

49 messages, the second-most active contributor on the list after Anup. Three separate but converging series.

(a) platform: generic: Tenstorrent Atlantis support — initial platform glue.

v1: 2026-03-10, Message-Id [email protected]. 4 patches.
- 1/4: Add Atlantis as a generic-platform. Enables single_fw_region option, verifies and prints HART PMA CSR configuration. Creates platform/generic/tenstorrent/{ascalon.c,atlantis.c,pma.c,Kconfig,objects.mk} and docs/platform/tt-atlantis.md. ~330 LOC.
- 2/4: Move PMP encoding into a new file (precursor to standalone PMP refactor).
- 3/4: Add hart_ prefix to PMP functions.
- 4/4: platform: generic: tenstorrent: Add RISC-V IOMMU support. Atlantis IOMMU is described as using PMP MMRs in the same encoding as the hart PMP CSRs, motivating shared encoding helpers. Depends on a Linux device-tree binding RFC for tenstorrent,riscv-iommu posted to linux-riscv (Message-Id [email protected]).
- The cover notes "Atlantis hardware is not yet released, and QEMU models are in the process of being upstreamed, but at the moment not complete" — Atlantis upstreaming is happening in parallel with public hardware availability and a QEMU tt-atlantis machine model.
- Published doc snippet: "The Tenstorrent Atlantis is an SoC and development board from Tenstorrent in partnership with CoreLab Technology. It contains 8 RISC-V RVA23 compliant Tenstorrent Ascalon cores with RISC-V AIA, RISC-V IOMMU, and a range of devices and IO connectivity." Recent (6.18) Linux/riscv 64-bit defconfig kernels run the QEMU tt-atlantis machine.
v2: 2026-04-24. Drops the IOMMU and PMP refactor patches (they get split out). Single-patch repost of the platform skeleton + PMA/Ascalon scaffolding.
v3: 2026-04-24 (a few hours later). "Fix silly 32-bit build issue."

(b) dbtr: Fixes and heterogeneous trigger types — 18-patch monster, 2026-03-13, Message-Id [email protected]. Motivated explicitly by "implementing and testing heterogeneous trigger types as found in the Tenstorrent Ascalon CPU."

Patches 1-11: bug-fix block. Range checks on every dbtr ecall handler, sbiret.value on update failure, endian conversion in the install handler, "do not support chain bit" (per spec), error-handling for enable/disable/uninstall, avoiding crash in sbi_debug_read_triggers, succeeding ops with no triggers in mask, and fixing read-trigger to not read HW trigger when not mapped.
Patch 12: refactor — move HW trigger probing into a function.
Patches 13-15: rework install/update error handling, decouple dbtr trigger index from hardware trigger number, move trigger feature support test into a function.
Patches 16-17: the heterogeneous part — different HW triggers support different functions, so the existing 1:1 dbtr-trig → HW-trigger mapping is relaxed; HW triggers are allocated independently from what can satisfy the requested type. Heterogeneous access type matching for mcontrol triggers.
Patch 18: "Work around specification bug in range checks" — held last because it depends on a pending SBI spec update; Nick offered to move it forward if the issue is confirmed.
Companion kvm-unit-tests series posted same week: riscv: sbi: dbtr: fix enable trigger return code check and riscv: dbtr: Add initial API corner case / error handling tests — Nick is also building the test harness for dbtr.

(c) Make PMP encoding usable for non-hart PMPs — 7 patches, 2026-04-30, Message-Id [email protected]. The work behind the IOMMU patch from (a).

Rationale (from the cover): "The Tenstorrent RISC-V IOMMU implements PMPs with MMRs in the same format as specified in the RISC-V ISA for the hart CSRs. This series splits out the PMP encoding functions so it can be shared by both users."
Pulls files apart: introduces pmp_t type, splits PMP encoding from CSR access, moves encoding to a new lib/sbi/sbi_pmp.c, adds CSR read/write accessors, adds pmp_is_enabled(), and renames the hart variants with a hart_ prefix into lib/sbi/sbi_hart_pmp.c. Touches platform/generic/eswin/eic770x.c (-/+) along the way.
Notes that the IOMMU patch from the original Atlantis series will be reposted "after the base Atlantis platform and this series is merged."

This is a clear Tenstorrent upstreaming pipeline: get the Atlantis platform skeleton in → land the PMP refactor → repost the IOMMU. The dbtr work is the parallel feature-track for Ascalon's debug triggers.

1.2 Evgeny Voevodin — Smrnmi (Resumable NMI) infrastructure

27 messages. Took ownership of the OpenSBI Smrnmi support after a competing SiFive series stalled (see §2.1). Three revisions.

v1, 2026-03-10 — [PATCH 0/7] Add RISC-V Smrnmi extension support, Message-Id [email protected]. Based on top of Nick Piggin's Atlantis platform v1.

Provides infrastructure for Resumable NMI (RNMI) and Resumable NMI Exception (RNME) handling: dedicated MNEPC/MNSTATUS/MNCAUSE CSRs, implementation-defined NMI vector locations via NMIVEC/NMEVEC.
Patches 1-5: shared infrastructure — tmp1 scratch slot (RNMI handlers use MNSCRATCH instead of MSCRATCH and need separate scratch space), Smrnmi extension macros & enum bit, RNMI/RNME handlers in firmware/fw_base.S, platform callback smrnmi_handlers_init(), detect-and-enable Smrnmi early before trap-based feature detection.
Patches 6-7: Tenstorrent platform glue — Ascalon callback hookup and Atlantis stub handler.
Testing: "Verified on virtual Whisper platform." (Whisper is a Tenstorrent simulator.)

v2, 2026-05-01 — [PATCH v2 0/5] Add RISC-V Smrnmi extension support, Message-Id [email protected]. Major rework based on Anup's review.

Dropped patches 6/7 and 7/7 (Tenstorrent platform support). Per cover: "They will go through the Atlantis platform series instead." So Smrnmi-on-Atlantis depends on the Atlantis platform series landing first.
Dropped the dedicated _rnme_handler assembly entry, ops->rnme_handler callback, and sbi_rnme_handler() C function. RNME is now reused through the existing _trap_handler since RNME is taken as a regular M-mode trap with NMIE=0; ops->smrnmi_handlers_init() passes _trap_handler in place of _rnme_handler.
Renamed _rnmi_handler → _trap_rnmi_handler and the C handler to sbi_trap_rnmi_handler().
Kept ops->rnmi_handler as the temporary RNMI dispatch mechanism (per v1 discussion); extending sbi_irqchip to support NMIs is left for a separate follow-up.
Critical interaction with another series: between v1 and v2, upstream introduced commit ecdb6c90 ("firmware: Initialize stack guard via Zkr"). The Zkr seed-CSR access can trap if Zkr is unimplemented. On Smrnmi platforms NMIE=0 by default after reset, which routes that trap to NMEVEC instead of MTVEC. With no NMEVEC handler installed yet, the early-boot Zkr probe in _start would crash. New patch 4/5 refactors the inline seed loop in fw_base.S into a callable __stack_chk_guard_init and invokes it from init_coldboot() after sbi_hart_init() has installed Smrnmi handlers and set NMIE=1.

v3, 2026-05-07 — [PATCH v3 0/6] Add RNMI handler infrastructure for Smrnmi extension, Message-Id [email protected]. Rebased on 2257e9957103 ("lib: sbi_bitmap_test: add tests for bitmap_empty()").

Per Anup's v2 review, splits former patch 4 ("Create a spot ...") into two:
- Patch 4: only moves sbi_platform_extensions_init() to the beginning of hart_detect_features().
- Patch 5: moves Zkr stack-guard initialization out of fw_base.S into init_coldboot() in C, and drops the asm __stack_chk_guard_init() helper — __stack_chk_guard is initialized directly from init_coldboot().
Testing now also on a HW emulator in addition to Whisper.
Patch 2 ("Add Smrnmi extension macros for registers and bits") picked up Reviewed-by: Anup Patel. This patch defines MNSTATUS_NMIE/MNPV/MNPP and CSRs CSR_MNSCRATCH=0x740, CSR_MNEPC=0x741, CSR_MNCAUSE=0x742, CSR_MNSTATUS=0x744, plus enum bit SBI_HART_EXT_SMRNMI.

The series is in advanced review; only the Zkr split is left to settle.

1.3 Anirudh Srinivasan — payload alignment fix

A single patch on 2026-05-08, Message-Id [email protected]: platform: Fix payload alignment when FW_TEXT_START isn't 2M/4M aligned.

Root cause: FW_PAYLOAD requires the payload at a 2M (64-bit) or 4M (32-bit) aligned address. The current makefile uses FW_PAYLOAD_OFFSET which only works if FW_TEXT_START is already aligned. For FW_TEXT_START=0x80000, the payload ends up at 0x280000, not 2M aligned.
Fix: switch from FW_PAYLOAD_OFFSET to FW_PAYLOAD_ALIGN in platform/generic/objects.mk and platform/template/objects.mk. Comments in the template are flipped accordingly.
Standalone single-patch submission. No review thread observed in the window.

2. Cross-cutting feature initiatives

2.1 Smrnmi: two competing series, then convergence

Smrnmi is the RISC-V "Resumable Non-Maskable Interrupts" extension — it adds MNEPC/MNCAUSE/MNSTATUS, sets up an NMIE bit so NMIs can be delivered without permanently destroying machine context, and routes traps to NMEVEC when NMIE=0.

SiFive's series came first. 2026-01-29, Nylon Chen ([email protected]), [PATCH 0/3] [PATCH v3] lib: sbi: Add RISC-V Smrnmi extension support, Message-Id [email protected]. Co-developed-by Zong Li (SiFive), Suggested-by Nick Hu / Samuel Holland (SiFive), Signed-off-by Yong-Xuan Wang (SiFive).

v3 split a single patch into three per Anup's earlier feedback: detection, enable handler, common NMI trap handler in fw_base.S.
Adds sbi_rnmi_vector_init() to allocate per-HART RNMI context, platform op set_rnmi_trap_vector() for vector programming, suspend/resume support for RNMI CSRs.
This SiFive series did not land. Tenstorrent's Voevodin took the lead in March, picked up the SiFive groundwork, and pushed it through review (see §1.2).

Implication: RISC-V Smrnmi support in OpenSBI is being driven by Tenstorrent now, with SiFive as the original instigator. The CSR encodings, MNSTATUS bit definitions, and enum bit are common between both efforts.

2.2 Hardware isolation (HWISO) framework + QEMU virt WorldGuard RFC

Raymond Mao ([email protected] / [email protected], RISCstar Solutions Corporation) is building a generic abstraction for hardware-domain isolation in OpenSBI.

RFC: sbi: add hardware isolation abstraction framework — initially posted 2026-03-17 (referenced as [1]), reposted 2026-05-04, Message-Id [email protected]. Two patches.

Patch 1: introduces struct sbi_hwiso_ops with name + boot init + per-domain init/exit + domain enter/cleanup. Stores per-domain mechanism contexts in struct sbi_domain via hwiso_ctxs / hwiso_ctx_count.
Patch 2 (sbi: route domain lifecycle transitions through hwiso hooks) wires the abstraction into the domain context-switch path so multiple isolation mechanisms can compose without coupling the domain core to any platform implementation. New file lib/sbi/sbi_hwiso.c (~175 LOC).

RFC: Add QEMU virt WorldGuard support on top of HWISO — 2026-05-01, Message-Id [email protected]. Three patches, ~1410 LOC.

WorldGuard is a RISC-V isolation extension that lets harts execute under a "World ID" (WID) and gates checker MMIO access by WID.
Patch 1: adds CSR_SLWID=0x190, CSR_MLWID, CSR_MWIDDELEG and smwg / sswg hart extension flags so platform code can probe support.
Patch 2: documents HWISO/WorldGuard DT bindings and adds a QEMU virt overlay example (120-line qemu-virt-hwiso-overlay.dts) for domain WID/WID-list assignment and checker permissions.
Patch 3: qemu_virt_wgchecker.c (~1050 LOC) — parses checker topology and protected-resource permissions from DT, programs wgChecker MMIO state at boot, parses per-hart default WorldGuard execution state, parses per-domain WorldGuard metadata, reprograms MLWID, MWIDDELEG, SLWID on domain transitions.
The HWISO framework is the abstraction; WorldGuard is the first concrete user. Future users include MPAM-style QoS, possibly RISC-V Ssqosid/CBQRI on the kernel side.

2.3 dbtr (debug-triggers): npiggin's 18-patch flood

Already covered in §1.1(b). Worth re-emphasizing: this is the largest single fix-and-extend block on the dbtr (SBI Debug Trigger) extension since it was introduced. Half the series is bug fixes (range checks, endianness, error returns), the other half is the genuine architectural change to support heterogeneous HW triggers as found on Ascalon.

2.4 FP / Vector context: Dave Patel's eager-switching saga

Dave Patel ([email protected], RISCstar) drove a four-month series that went v1 → v2 → v3 → v4.

v1: 2026-03-21, [PATCH 0/4] Add eager FP and RISC-V vector context switching support. Goal: per-domain FP/V context save/restore so domain switches don't corrupt FP/V state.
v2: 2026-03-26, dropped to 3 patches; cover notes "the context switch itself in OpenSBI is not being hooked up" yet (still gathering consensus on shape).
v3: 2026-03-27, repost.
v4: 2026-03-31 / 2026-04-x, three-patch shape stable.
Touches switch_to_next_domain_context() adjacent to the existing SBI_HART_EXT_SSQOSID srmcfg-swap (incidental cohabitation). Adds fp_ctx/vec_ctx to struct sbi_domain, sbi_fp_domain_init/exit(), sbi_vector_domain_init/exit(), and proper FS/VS handling in mstatus around the domain switch (only flip FS/VS to Initial if Off; restore original after).
Anup pushed back through several revisions on the FS/VS handling and on whether the context switch should be hooked up at all in OpenSBI vs. expected from the supervisor.

2.5 Anup Patel's irqchip overhaul (multi-series)

Anup Patel (now [email protected] — note he migrated from rivosinc.com / brainfault.org during this period; both addresses appear) is reshaping the OpenSBI irqchip framework in a series of related drops.

[PATCH 0/8] Extend irqchip framework for M-mode interrupts — 2026-02-07, Message-Id [email protected].

Goal: support multiple controllers each targeting a subset of harts, hierarchical controllers (APLIC + IMSIC), and per-controller HW interrupt handler registration, without over-consuming memory.
Patches: rename irq_handle() to process_hwirqs(), fix irqchip_plic_update_context_map(), add IDC-to-hartindex map in aplic_data, add unique 32-bit IDs per irqchip device, allow irqchip device targetting subset of harts, allow registering interrupt handlers.
Touches PLIC, APLIC, IMSIC, plus Ariane, OpenPiton, K210 (later removed), Nuclei UX600, template platforms.
v2 reposted 2026-02-26.

[PATCH 0/3] APLIC hwirq implementation for irqchip — 2026-02-12. Adds APLIC hwirq operation hooks plus a NOT-FOR-UPSTREAM QEMU virt test for APLIC wired IRQs. Companion testing infra.

[PATCH 0/4] irqchip/rpmi: Expose APLIC/IMSIC interfaces for platform use — 2026-03-26.

[PATCH 0/6] Extend irqchip framework for MSIs and line sensing — 2026-04-23, Message-Id [email protected]. Continuation of the M-mode work.

Allow interrupt clients to specify line sensing type. Support MSI controller (IMSIC) as an irqchip device.
Patches: check full hwirq range when registering, keep handler list sorted, allow line-sensing spec, allow marking hwirqs as reserved, allow setting hwirq affinity, register MSI handlers.

These four series interlock and form the spine of OpenSBI's M-mode interrupt handling for AIA-equipped platforms. Branch tracker: irqchip_imp_v1 and irqchip_imp2_v1 at github.com/avpatel/opensbi.

2.6 Timer events

Anup Patel: [PATCH 0/3] Timer events for OpenSBI, 2026-04-15, Message-Id [email protected]. Reposted v2 as 4 patches in May.

Extends sbi_timer so platform drivers can use timer events for timeouts and periodic checks.
Adds sbi_scratch_hartindex() macro, per-HART timer state, support for timer events in lib/sbi/sbi_timer.c (~221 LOC delta).
Branch: sbi_timer_imp_v1 at avpatel/opensbi.

2.7 MIPS p8700 / Mobileye eyeq7h / MIPS Boston

The largest single platform series. Vladimir Kondratiev (Mobileye) with Benoît Monin (Bootlin) co-author.

v1: January, [PATCH 00/22] Introduce MIPS p8700 based "eyeq7h" and "boston".
v2: February, 20 patches.
v3: 2026-02-23, Message-Id [email protected], 23 patches. Tested on real eyeq7h hardware.
Refactors the existing MIPS p8700 platform code into a "cpu" abstraction, then adds two platforms on top: Mobileye eyeq7h (automotive) and MIPS boston (FPGA). Cluster power-up via OLB, accelerator cluster detection and reset deassertion, faster core boot, cache geometry detection, hi-res timer synchronization across clusters, ECC enable on L1 cache, MIPS-specific CSRs.
~1044 LOC added, ~306 LOC removed. Touches lib/sbi/sbi_domain.c, lib/sbi/sbi_hart_pmp.c, platform/generic/Kconfig, platform/generic/configs/defconfig, and many platform/generic/mips/* and platform/generic/include/mips/* files (board.h, mips-cm.h, p8700.h).

2.8 RPMI / MPXY updates

David E. Garcia Porras ([email protected]): [PATCH 0/2] MPXY MSI availability and RPMI notification updates, 2026-04-09, Message-Id [email protected].

Patch 1: replace msi_avail = false hardcode in MPXY channel setup with a runtime imsic_get_data() per-hart check; static inline stub when CONFIG_IRQCHIP_IMSIC is off.
Patch 2: add RPMI notification header macros, rpmi_event_notification_state enum, missing req_state/current_state fields on enable-notification req/resp, plus notification event ID enums and data structures for RPMI Performance service group events (power change, limit change, level change).

David Garcia also has [PATCH 4/4] include: mailbox: rpmi_msgprot: Add RPMI performance domain flag defines (March), and a 2-patch MM-service-group MPXY client driver for RPMI in February.

2.9 Hart state management & system suspend

Andes (Ben Zong-You Xie, [email protected]): [PATCH 0/5] Add hart state management and system suspend support for AE350. Originally December 2025, applied by Anup on 2026-02-10.

Factors ATCSMU code into a dedicated FDT-based HSM driver, adds CSR save/restore for AE350 deep sleep and CPU hotplug, adds cache enable/disable utils, adds an Andes Last Level Cache controller driver, and adds a suspend driver for ATCSMU.
Already merged.

2.10 SSE (Supervisor Software Events) fixes

Zhanpeng Zhang (Bytedance) ([email protected]): [PATCH 0/2] lib: sbi: sse: fix interrupted context corruption, 2026-04-30, Message-Id [email protected].

Two genuine bugs in the SSE entry/completion path:
- KVM context corruption: SSE inject builds a synthetic S-mode context for the registered S-mode handler. After completion, OpenSBI restores the interrupted context, but the current code reconstructs hstatus SPV/SPVP from handler-visible state — insufficient on virtualization-enabled systems because hstatus carries more H-mode state. MPV must be captured before OpenSBI rewrites trap state for handler entry, or the KVM resume context is corrupted.
- SSTATUS leakage: synthetic handler SIE/SPIE/SPP can leak into the SSE-interrupted context. With PMU-SSE active (e.g. perf top), this triggers high-frequency exposure leading to "environment call from U-mode" panics.
Fix: store private resume state in sbi_sse_event (not in ABI-visible attributes). Patch 1 saves/restores hstatus and interrupted virtualization state; patch 2 saves/restores SIE/SPIE/SPP.
Author notes a companion Linux side will preserve kernel stvec in do_sse() to help protect the virtualization context.

2.11 Domain plumbing fixes

A steady drumbeat of small fixes to lib/sbi/sbi_domain*.

Marcos Oduardo ([email protected]): include: sbi: fix illegal shift in sbi_domain.h: sbi_domain_memregion_is_subset, 2026-02-22, then re-fixed by Anup 2026-03-09.
Takumi Hara ([email protected]): lib: sbi_domain: reject overflowing address range in check_addr_range(), 2026-03-19, multiple revisions through 2026-03-27 (Vivian Wang and Anup reviewed; iteration on overflow semantics).
Dave Patel: [PATCH 1/4] lib: sbi: domain: ensure boot_hartid is assigned, 2026-03-20.
Peter Lin ([email protected]): lib: utils: fdt_domain: add support for root domain region inheritance and lib: fdt_domain: Default boot-hart to coldboot HART for multi-domain boot, 2026-03-27.

2.12 Cache / PMP / ABI corner cases

Anup: [PATCH v2 0/2] lib: sbi: Flush cache entries after writing PMP CSRs, February. Fixes a coherence hole between PMP CSR programming and pending data in the cache.
Charles Jenkins (devnull+thecharlesjenkins.gmail.com): event-injection fix discussion in March (base-commit: 8d1c21b38752301fc6c727eece45c15c663649b0, change-id: 20260302-event_inject_fix-...) on saving a6/a7 in the inject context.
Chen Pei ([email protected]): riscv: smp: Align secondary_start_sbi to 4 bytes, v2 in April. The secondary_start_sbi address is passed via sbi_hsm_hart_start and written to STVEC; the privilege spec requires STVEC.BASE to be 4-byte aligned, but secondary_start_sbi was not. Anup acknowledged the historical oddity.

2.13 Removals

Anup Patel: [PATCH] platform: Remove kendryte/k210 platform, 2026-04-08, Message-Id [email protected].
- K210 has no MMU support in S-mode; only NOMMU kernels running in M-mode work. "As of now, there is no clear use-case of supporting OpenSBI for kendryte/k210 platform." Removes 336 lines including k210.dts, platform.c, platform.h, Kconfig, defconfig.

2.14 Misc fixes & smaller features (Jan-May)

January: lib: sbi: KASan implementation for OpenSBI, lib: sbi: UBSan implementation for OpenSBI (early-year safety instrumentation work).
January: lib: sbi: Fix behavior on platform without HART protection.
January: lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64.
January: lib: sbi_pmu: Fix multiple FW counter start operations with custom PMU device.
January: lib: sbi_pmu: Track SBI_PMU_FW_PLATFORM started counter.
January: lib: utils/serial: Add support for Altera JTAG UART.
February: firmware: generate __stack_chk_guard at compile time (later superseded by firmware: Initialize stack guard via Zkr, ecdb6c90, which interacted poorly with Smrnmi — see §1.2 v2 changelog).
February: lib: utils: Add MPXY client driver for RPMI MM service group.
February: [PATCH] platform: support starriver 9530.
February: [PATCH RFC] paravirt place holder for ecall and [PATCH RFC] VIRQ (Virtual IRQ) layer to support paravirtual interrupt delivery from [email protected] — early prototyping for paravirtual interrupt delivery, three sub-patches: prototype VIRQ layer, sample DTS overlay, VIRQ ecall extension.
February: [PATCH 0/7] Fixes for load/store misaligned and access faults — large series adding mstatus and instruction encoding helpers, sbi_regs_prev_xlen, GET/SET FP RDS macros, FS-dirty in vsstatus when V=1, do not override emulator callback for vector load/store, rework load/store emulator instruction decoding. Plus a NOT-FOR-UPSTREAM test program.
February: [PATCH] lib: sbi: Use SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI with unknown ....
March: [PATCH] firmware: fw_base: make stack guard setup conditional on Zkr. Already superseded by Voevodin's Smrnmi rework.
March: [PATCH 0/5] Add RISC-V Smrnmi extension support and [PATCH 0/6] Add RNMI handler infrastructure for Smrnmi extension (Voevodin's revisions, already covered).
March: [kvm-unit-tests PATCH 1/2] riscv: sbi: dbtr: fix enable trigger return code check and riscv: dbtr: Add initial API corner case / error handling tests (npiggin, companion to dbtr fixes).
April: [PATCH 0/2] Add reboot support for SpacemiT K1 platforms.
April: [PATCH] platform: Fix payload alignment when FW_TEXT_START isn't 2M/4M aligned (Tenstorrent, Anirudh — covered in §1.3).
April: [PATCH] lib: sbi: Fix hw a/d updating defaults.
May: [PATCH 1/1] include: sbi_scratch: fix typo sbi_scratch -> HART id (small).

3. Maintenance and release events

2026-01-08: Anup announces OpenSBI v1.8.1. Intermediate release with two fixes: typo in comments of sbi_hartindex_to_hartid(), and a fix for the hart-protection abstraction on platforms without PMP. Driven by Thomas Perrot (Bootlin) reporting init_coldboot: hart isolation configure failed (error -3) on QEMU 10.1.3 with rva22s64/rva23s64 profiles. Root cause: QEMU disables PMP by default; rva22s64/rva23s64 needed pmp=true explicitly. v1.8.1 fixes the OpenSBI side so it doesn't fail when PMP is missing.
Anup's email migration: throughout the window, Anup's address shifts between [email protected] (personal/historical), [email protected] (employer current), and historical [email protected] references. Both anup at brainfault.org (76 messages, mostly review and process) and anup.patel at oss.qualcomm.com (8 messages, mostly his own series) appear active.
Anup as maintainer: 76 messages, consistent reviewer on essentially every series. Style: short, technical, pointed reviews; explicit "Applied this series to the riscv/opensbi repo" when merging; specific patch-split requests when reshaping. Most of the multi-revision series in this digest were reshaped on Anup's feedback.

4. Cast of characters (frequent and notable)

Author / address	Affiliation	Activity
Anup Patel <[email protected] / [email protected]>	Qualcomm (was Ventana, was Rivos)	de-facto maintainer; irqchip overhaul, timer events, k210 removal
Vladimir Kondratiev [email protected]	Mobileye	MIPS p8700 / eyeq7h / boston refactor
Nicholas Piggin [email protected]	Tenstorrent	Atlantis platform, dbtr fixes, PMP refactor
Dave Patel [email protected]	RISCstar	FP/Vector eager context switching
Raymond Mao <[email protected] / [email protected]>	RISCstar	HWISO framework + WorldGuard
Evgeny Voevodin [email protected]	Tenstorrent	Smrnmi infrastructure
Anup Patel	Qualcomm	irqchip M-mode/MSI/line-sensing extensions
Ganbo Wang (ganboing)	?	misc fixes
Samuel Holland [email protected]	SiFive	reviews on FP/V, Smrnmi origins
Nylon Chen / Zong Li / Yong-Xuan Wang	SiFive	original Smrnmi v3 (later picked up by Tenstorrent)
Nick Hu [email protected]	SiFive	Smrnmi suggester
David E. Garcia Porras [email protected]	Ahead Computing	MPXY/RPMI updates, RPMI Performance event defs
Marcos Oduardo [email protected]	?	sbi_domain shift fix
Takumi Hara [email protected]	?	check_addr_range overflow
Peter Lin [email protected]	SiFive	fdt_domain inheritance, multi-domain boot-hart default
Himanshu Chauhan [email protected]	Qualcomm	VIRQ paravirt-IRQ RFC
Ben Zong-You Xie [email protected]	Andes	AE350 HSM + system suspend (merged)
Zhanpeng Zhang [email protected]	Bytedance	SSE KVM context + sstatus leakage fixes
Anirudh Srinivasan [email protected]	Tenstorrent	payload alignment fix
Nylon Chen [email protected]	SiFive	Smrnmi v3 (origin of the current series)
Joel Stanley	? (likely IBM/Linaro/equivalent)	scattered review
Andrew Jones <andrew.jones@?>	?	scattered review
Aurelien	?	scattered review
Charles Jenkins <devnull+thecharlesjenkins.gmail.com>	?	event-inject fix
Daniel Henrique Barboza [email protected]	Qualcomm	reviews

5. Themes and tensions for a deep-dive episode

A handful of cross-cutting threads worth pulling on:

Tenstorrent is upstreaming Atlantis. The big arc: Atlantis platform skeleton (npiggin) → PMP refactor for non-hart PMPs (npiggin) → Atlantis IOMMU repost (npiggin) → Smrnmi infrastructure (Voevodin) → Smrnmi-on-Atlantis (held back, queued behind the Atlantis platform series). Three Tenstorrent contributors converging on a single product.
Two parallel Smrnmi efforts. SiFive proposed Smrnmi support in January with full review iteration through v3, but that series did not land. Tenstorrent picked up the work in March and pushed it through, with the v3 iteration in May now sitting in advanced review with Reviewed-by tags appearing on individual patches. Same hardware extension, different teams driving — a useful lens on how upstream priorities and bandwidth gate which series cross the finish line.
Hardware isolation is becoming a framework, not a one-off. RISCstar's HWISO + WorldGuard RFC is structurally interesting because it acknowledges that domain isolation will need multiple composable mechanisms — WorldGuard, MPAM-style QoS, possibly Tenstorrent IOMMU and Smrnmi, possibly RISC-V Ssqosid/CBQRI on the kernel side. The abstraction explicitly registers callbacks and stores per-domain mechanism context in struct sbi_domain.
Anup's irqchip plan is multi-quarter. Three back-to-back series (M-mode interrupts, APLIC hwirq, MSIs + line sensing) shape OpenSBI's interrupt subsystem to handle modern AIA platforms with multiple controllers, hierarchical PLIC/APLIC/IMSIC stacks, MSI-style delivery, and per-IRQ affinity / reservation. The irqchip_imp_v1 and irqchip_imp2_v1 branches at avpatel/opensbi are the staging area.
Domain plumbing is the silent rough edge. A long tail of small fixes on lib/sbi/sbi_domain* — overflowing address ranges, illegal shifts, missing boot_hartid, root-domain region inheritance, FP/V context, hwiso hooks — keeps showing up. These are correctness fixes layered on top of an abstraction that's still settling, especially as multi-domain boot becomes more common.
Stack guard / Zkr / Smrnmi interaction. Two well-meaning improvements collided: firmware: Initialize stack guard via Zkr (compile-time → runtime via Zkr SEED CSR) and Smrnmi (NMIE=0 by default after reset on Smrnmi platforms, routing early traps to NMEVEC). The early-boot Zkr probe in _start would crash on Smrnmi platforms before any NMEVEC handler is installed. Voevodin's v2 series captured this and the v3 split shows Anup's preferred resolution: move Zkr stack-guard init from asm to C, sequence after Smrnmi enable. A nice example of how subtle the dependency ordering can be at firmware-init time.
MIPS at the OpenSBI table. Mobileye and MIPS are landing serious platform support for the first time in this window — eyeq7h tested on real hardware. Different culture and naming conventions than the RISC-V regulars; coexistence is already smoothing out (lib: sbi: print hartid in hex lands first, then the cluster/PMP/CM details).

6. Where to dig

If a NotebookLM episode wants to follow up on something specific:

Atlantis platform: search "20260310005000.3837512" (v1) and "20260424062520.238403" (v3).
Smrnmi v3 (current): search "1778176768.git.evvoevod" or the cover Message-Id [email protected].
dbtr 18-patch: search "20260313051948.4017134".
PMP refactor: search "20260430045528.420437".
HWISO + WorldGuard RFC: search "20260501183346.1596027" (WorldGuard) and "20260504173948.1663823" (HWISO repost).
MIPS p8700 v3: search "20260223-for-upstream-eyeq7h-v3-0".
SSE KVM/sstatus fix: search "20260430102313.95249".
Andes HSM/suspend (merged): search "20251229071914.1451587" (original Andes posting that Anup merged in Feb).

pdp7/opensbi-2026-jan-may-digest.md

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