Quick tutorial to get RZ-EasyFPGA from AliExpress going with Quartus

HelloWorld Example in Quartus.md

Using

• FPGA Development Board: RZ-EasyFPGA A2.2 from AliExpress, featuring the Altera Cyclone IV.
• OS: Ubuntu 18.04 LTS (bionic)

Quartus Installation

1. Get the Quartus Lite installer, ModelSim installer (optional), and the Cyclone IV development Package from the Altera website.
   • Get it here: https://www.altera.com/products/design-software/fpga-design/quartus-prime/download.html
   • You gotta click on Lite Edition > (Select version and OS) > Individual files and download: Quartus Prime (includes Nios II EDS) and Cyclone IV device support. Files are about 500MB - 2000MB.
2. Install Quartus. Root not required
   • Command:

   $ chmod +x QuartusLiteSetup-18.0.0.614-linux.run
   $ ./QuartusLiteSetup-18.0.0.614-linux.run
   

   • Place in ~/.intelFPGA_lite/18.0 (Note the dot before 'intel').
3. Try running Quartus and verify that it launches. Command: ~/.intelFPGA_lite/18.0/quartus/bin$ ./quartus
   • If you get an error like libpng12.so.0: cannot open shared object file: No such file or directory then go to http://mirrors.edge.kernel.org/ubuntu/pool/main/libp/libpng/ and download/install latest for ubuntu amd64. Example:

   $ wget -q -O /tmp/libpng12.deb http://mirrors.kernel.org/ubuntu/pool/main/libp/libpng/libpng12-0_1.2.54-1ubuntu1_amd64.deb
   $ sudo dpkg -i /tmp/libpng12.deb
   $ rm /tmp/libpng12.deb
   

Hello World Example

1. Open Quartus.
2. Create a new Project
   • File → New → New Quartus Prime Project
   • General Settings:
     • Working directory should be '<path_to_your_dev_folder>/helloWorld'.
     • Set name and top-level-design entity to 'HelloWorld'.
     • Create an Empty Project
     • For Design Files, add that Cyclone IV file you downloaded, cyclone-17.0.0.595.qdz (or similar).
   • Family, Device and Board Settings
     • Family: Cyclone IV E
     • Device: All
     • Target Device: Specific device selected in 'Available devices' list.
     • Name Filter: EP4CE6E22C8
     • Select the EP4CE6E22C8, not the 'EP4CE6E22C8L'.
   • EDA Tools Settings
     • None for now but it would be nice to get ModelSim-Altera working for Simulation.
3. You should now have a blank HelloWorld project staring at you.
4. Add a main source file. Select File > New > Verilog HDL File. Name it 'HelloWorld.v' and save it.
5. Add the following code to HelloWorld.v:

   module HelloWorld (
     input clk,
     output led1, led2, led3, led4
   );
   
   reg [25:0] dig;
   
   // Custom order of LEDs to distinguish from default program
   assign {led1, led4, led3, led2} = dig[25:22];
   
   always @(posedge clk) dig <= dig+1;
   
   endmodule
   

6. Hit the "Start Compilation" button (blue play button) and sanity check that the project compiles.
7. Open Assignment Editor. Create a text file somewhere called 'assignments.txt'. Populate it with this:

To, Assignment Name, Value
clk, Location, PIN_23
led1, Location, PIN_87
led2, Location, PIN_86
led3, Location, PIN_85
led4, Location, PIN_84

8. Click 'Assignments > Import Assignments' and load up your text file to overwrite the assignment editor. (I couldn't figure out how to do this through the Quartus editor). Your pin assignments should populate automatically.
9. Compile the project again.
10. Click on 'Programmer' to open the programmer window. Configure the programmer.
    • Hardware Setup: USB_blaster [3-2]
    • Mode: JTAG
    • File: (Select HelloWorld.sof, which should be the only option).
    • Make sure "Program/Configure" is checked.
11. Make sure your development board is connected to power source, connected via USB-Blaster to PC, and turned on.
12. Flash the circuit by clicking 'Start'.
13. The LEDs on the board should start doing a little jig, different from the standard clock sequence.

Troubleshooting

When flashing to the board, you click Start and nothing happens. Start by running jtagconfig. peach@peach01:~/.intelFPGA_lite/18.0/quartus/bin$ ./jtagconfig

Unable to lock chain - Insufficient port permissions

1. Run solution here (https://stackoverflow.com/questions/18704913/unable-to-lock-chain-insufficient-port-permissions).
2. Then, restart the JTAG daemon.

   sudo killall -9 jtagd
   

3. Restart the PC.

Unable to read device chain - JTAG chain broken

In case you see this error message, your USB Blaster works, but you can't to connect to the JTAG chain. A possible cause can be a missing 32 Bit version of libudev. Download libudev1:i368 and create a symbolic link.

$ sudo apt-get install libudev1:i386
$ sudo ln -sf /lib/x86_64-linux-gnu/libudev.so.1 /lib/x86_64-linux-gnu/libudev.so.0

Another source also suggests you have the board powered on and USB Blaster connected to the board before hooking it up to the computer. The expected output is

~/.intelFPGA_lite/18.0/quartus/bin$ ./jtagconfig
1) USB-Blaster [3-2]
  020F10DD   10CL006(Y|Z)/10CL010(Y|Z)/..

The RZ-EasyFPGA A2.2 is a great value at an inexpensive price.
Very good prototyping capability wit the standard interface connectors and the headers.
My design comments:
1- The RESET line is using a global clock input.
2- The device has another global reset input pin but that one is tied to an LED output
3- The other 4 global clock inputs are for the 4 push button inputs. At least CLK2 looks available.
4- These inputs are also tied to the 4 toggle switches which have redundant pull-up resistors.
5- The Verilog code examples provide designs for all of the hardware except the SDRAM.

Hello!
5- The Verilog code examples provide designs for all of the hardware except the SDRAM.

Please, where is code examples links?

Great tutorial, when i flash the example just set on all the leds but it doesnt blink, do i need to set another configuration?

@VladimirKhludenkov

Please, where is code examples links?

The code example files are here

There is documentation as well. The forum is in Russian.

This boards appears to have a flash chip ob-board (the M25P16). Is there any way to upload the output files to this so that it maintains the programming after poweroff?

@MauroFoti Isn’t that what the second port “AS” is for? JTAG port downloaded programs don’t survive a power cycle, but the AS downloaded ones do.

Isn’t that what the second port “AS” is for? JTAG port downloaded programs don’t survive a power cycle, but the AS downloaded ones do.

To flash your FPGA, so the "program" does survive a powercycle, you have to create a JIC file with QuartusII.
Select the right chip EPCQ16, the SOF file you have synthesized and of cause your target FPGA EP4CE6.
Go to the programmer window, remove your SOF and add the jic, upload it to the FPGA and now it will survive a powercycle.

Edit: this is all done via the JTAG header, not the AS.

Hmm. @GiR-Zippo That's not the way my Quartus and FPGA board works.

Maybe they changed some things over the 3 years. But that's the way I programmed my RZ-EasyFPGA V2.2 and the small MICC variant today.
The small MICC board doesn't even have an AS header, just the EP4CE6, a flash chip and the JTAG header.

Edit: https://www.intel.com/content/www/us/en/docs/programmable/683707/current/generating-a-jic-file.html
That's what I did. :)
Oh and you have to select the right FPGA for the EPCQ, else QuartusII will just throw an error during the flash process.

You can see from the photo in my original post that there definitely is an AS connection on my board. YMMV if you're using a different board.

My dev board has the JTAG ans AS port too and it should be the same board as yours (RZ-EasyFPGA A2.2).
But never used the AS for permanently store the "program" in the flash, just used the JTAG for this...

Interesting! I've never used your approach to flashing the program permanently. I just move the connector from JTAG to AS and do the same procedure as for JTAG.