-
-
Save pexcn/aee1fa9303439ef4413e66c6a41ea616 to your computer and use it in GitHub Desktop.
Xiaomi AX1800 Device Tree
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| /dts-v1/; | |
| / { | |
| MP_256; | |
| model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP02-C1"; | |
| compatible = "qcom,ipq6018-cp02", "qcom,ipq6018"; | |
| qcom,msm-id = <0x192 0x00>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x00 0x40000000 0x00 0x10000000>; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| nss@40000000 { | |
| no-map; | |
| reg = <0x00 0x40000000 0x00 0x800000>; | |
| }; | |
| uboot@4A100000 { | |
| no-map; | |
| reg = <0x00 0x4a100000 0x00 0x400000>; | |
| }; | |
| sbl@4A500000 { | |
| no-map; | |
| reg = <0x00 0x4a500000 0x00 0x100000>; | |
| }; | |
| tz@4A600000 { | |
| no-map; | |
| reg = <0x00 0x4a600000 0x00 0x400000>; | |
| }; | |
| smem@4AA00000 { | |
| no-map; | |
| reg = <0x00 0x4aa00000 0x00 0x100000>; | |
| linux,phandle = <0x11>; | |
| phandle = <0x11>; | |
| }; | |
| wcnss@4ab00000 { | |
| no-map; | |
| reg = <0x00 0x4ab00000 0x00 0x2800000>; | |
| linux,phandle = <0x16>; | |
| phandle = <0x16>; | |
| }; | |
| q6_etr_dump@0x4D300000 { | |
| no-map; | |
| reg = <0x00 0x4d300000 0x00 0x100000>; | |
| linux,phandle = <0x17>; | |
| phandle = <0x17>; | |
| }; | |
| rsvd1@4D400000 { | |
| no-map; | |
| reg = <0x00 0x4d400000 0x00 0x100000>; | |
| }; | |
| rsvd2@4D500000 { | |
| no-map; | |
| reg = <0x00 0x4d500000 0x00 0x100000>; | |
| }; | |
| }; | |
| soc { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| compatible = "simple-bus"; | |
| interrupt-controller@b000000 { | |
| compatible = "qcom,msm-qgic2"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x03>; | |
| reg = <0xb000000 0x1000 0xb002000 0x1000>; | |
| linux,phandle = <0x01>; | |
| phandle = <0x01>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>; | |
| clock-frequency = <0x16e3600>; | |
| always-on; | |
| }; | |
| gcc@1800000 { | |
| compatible = "qcom,gcc-ipq6018"; | |
| reg = <0x1800000 0x80000>; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| linux,phandle = <0x02>; | |
| phandle = <0x02>; | |
| }; | |
| qcom,apss_clk@b111000 { | |
| compatible = "qcom,apss-ipq6018"; | |
| reg = <0xb111000 0x6000>; | |
| #clock-cells = <0x01>; | |
| #reset-cells = <0x01>; | |
| linux,phandle = <0x4c>; | |
| phandle = <0x4c>; | |
| }; | |
| arm,smmu@1E00000 { | |
| compatible = "arm,smmu-v2"; | |
| reg = <0x1e00000 0x40000>; | |
| #iommu-cells = <0x01>; | |
| #global-interrupts = <0x01>; | |
| qcom,skip-init; | |
| interrupts = <0x00 0x29 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x49 0x04 0x00 0xf0 0x04 0x00 0xf1 0x04 0x00 0xf2 0x04 0x00 0xf5 0x04 0x00 0xf6 0x04 0x00 0xf7 0x04 0x00 0xf8 0x04 0x00 0xf9 0x04 0x00 0xfa 0x04 0x00 0xfb 0x04 0x00 0xfc 0x04 0x00 0xfd 0x04 0x00 0xfe 0x04 0x00 0xff 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x3a 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x4c 0x04 0x00 0x4d 0x04 0x00 0x50 0x04 0x00 0x5e 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04>; | |
| status = "disabled"; | |
| }; | |
| serial@78b3000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0x78b3000 0x200>; | |
| interrupts = <0x00 0x134 0x04>; | |
| clocks = <0x02 0x54 0x02 0x43>; | |
| clock-names = "core", "iface"; | |
| status = "ok"; | |
| pinctrl-0 = <0x03>; | |
| pinctrl-names = "default"; | |
| dmas = <0x04 0x08 0x04 0x09>; | |
| dma-names = "tx", "rx"; | |
| }; | |
| serial@78af000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0x78af000 0x200>; | |
| interrupts = <0x00 0x6b 0x04>; | |
| clocks = <0x02 0x50 0x02 0x43>; | |
| clock-names = "core", "iface"; | |
| status = "disabled"; | |
| }; | |
| serial@78b0000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0x78b0000 0x200>; | |
| interrupts = <0x00 0x6c 0x04>; | |
| clocks = <0x02 0x51 0x02 0x43>; | |
| clock-names = "core", "iface"; | |
| status = "disabled"; | |
| }; | |
| serial@78b1000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0x78b1000 0x200>; | |
| interrupts = <0x00 0x132 0x04>; | |
| clocks = <0x02 0x52 0x02 0x43>; | |
| clock-names = "core", "iface"; | |
| status = "ok"; | |
| pinctrl-0 = <0x05>; | |
| pinctrl-names = "default"; | |
| }; | |
| qrng@e1000 { | |
| compatible = "qcom,prng-ipq807x"; | |
| reg = <0xe3000 0x1000>; | |
| clocks = <0x02 0x88>; | |
| clock-names = "core"; | |
| status = "ok"; | |
| }; | |
| dma@704000 { | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0x704000 0x20000>; | |
| interrupts = <0x00 0xcf 0x00>; | |
| clocks = <0x02 0x56>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x01>; | |
| qcom,controlled-remotely = <0x01>; | |
| qcom,config-pipe-trust-reg = <0x00>; | |
| linux,phandle = <0x06>; | |
| phandle = <0x06>; | |
| }; | |
| crypto@73a000 { | |
| compatible = "qcom,crypto-v5.1"; | |
| reg = <0x73a000 0x6000>; | |
| clocks = <0x02 0x56 0x02 0x57 0x02 0x58>; | |
| clock-names = "iface", "bus", "core"; | |
| dmas = <0x06 0x02 0x06 0x03>; | |
| dma-names = "rx", "tx"; | |
| }; | |
| qcom_mdss_qpic@7980000 { | |
| compatible = "qcom,mdss_qpic"; | |
| reg = <0x7980000 0x24000>; | |
| interrupts = <0x00 0x97 0x00>; | |
| clocks = <0x02 0x8a 0x02 0x89>; | |
| clock-names = "core", "aon"; | |
| dmas = <0x07 0x06>; | |
| dma-names = "chan"; | |
| status = "disabled"; | |
| }; | |
| qcom_mdss_qpic_panel { | |
| compatible = "qcom,mdss-qpic-panel"; | |
| label = "qpic lcd panel"; | |
| qcom,mdss-pan-res = <0x320 0x1e0>; | |
| qcom,mdss-pan-bpp = <0x12>; | |
| qcom,refresh_rate = <0x3c>; | |
| status = "disabled"; | |
| }; | |
| ssphy@78000 { | |
| compatible = "qcom,usb-ssphy-qmp"; | |
| reg = <0x78000 0x45c 0x193f244 0x04 0x8af8800 0x100 0x7e000 0x18>; | |
| reg-names = "qmp_phy_base", "vls_clamp_reg", "qscratch_base", "ahb2phy_base"; | |
| qcom,qmp-phy-init-seq = <0xac 0x14 0x1a 0x00 0x34 0x08 0x08 0x00 0x174 0x30 0x30 0x00 0x3c 0x06 0x06 0x00 0xb4 0x00 0x00 0x00 0xb8 0x08 0x08 0x00 0x194 0x06 0x06 0x3e8 0x19c 0x01 0x01 0x00 0x178 0x00 0x00 0x00 0xd0 0x68 0x68 0x00 0xdc 0xab 0xab 0x00 0xe0 0xaa 0xaa 0x00 0xe4 0x02 0x02 0x00 0x78 0x09 0x09 0x00 0x84 0x16 0x16 0x00 0x90 0x28 0x28 0x00 0x108 0xa0 0xa0 0x00 0x10c 0x00 0x00 0x00 0x184 0x0a 0x0a 0x00 0x4c 0xaa 0xaa 0x00 0x50 0x29 0x29 0x00 0x54 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0x18c 0x00 0x00 0x00 0xcc 0x00 0x00 0x00 0x128 0x00 0x00 0x00 0x0c 0x0a 0x0a 0x00 0x10 0x01 0x01 0x00 0x1c 0x7d 0x7d 0x00 0x20 0x01 0x01 0x00 0x14 0x00 0x00 0x00 0x18 0x00 0x00 0x00 0x24 0x0a 0x0a 0x00 0x28 0x05 0x05 0x00 0x48 0x0f 0x0f 0x00 0x70 0x0f 0x0f 0x00 0x100 0x80 0x80 0x00 0x440 0x0b 0x0b 0x00 0x4d8 0x02 0x02 0x00 0x4dc 0x6c 0x6c 0x00 0x4e0 0xbb 0xb8 0x00 0x508 0x77 0x77 0x00 0x50c 0x80 0x80 0x00 0x514 0x03 0x03 0x00 0x51c 0x16 0x16 0x00 0x448 0x75 0x75 0x00 0x454 0x00 0x00 0x00 0x40c 0x0a 0x0a 0x00 0x41c 0x06 0x06 0x00 0x510 0x00 0x00 0x00 0x268 0x45 0x45 0x00 0x2ac 0x12 0x12 0x00 0x294 0x06 0x06 0x00 0x254 0x00 0x00 0x00 0x8c8 0x83 0x83 0x00 0x8c4 0x02 0x02 0x00 0x8cc 0x09 0x09 0x00 0x8d0 0xa2 0xa2 0x00 0x8d4 0x85 0x85 0x00 0x880 0xd1 0xd1 0x00 0x884 0x1f 0x1f 0x00 0x888 0x47 0x47 0x00 0x80c 0x9f 0x9f 0x00 0x824 0x17 0x17 0x00 0x828 0x0f 0x0f 0x00 0x8b8 0x75 0x75 0x00 0x8bc 0x13 0x13 0x00 0x8b0 0x86 0x86 0x00 0x8a0 0x04 0x04 0x00 0x88c 0x44 0x44 0x00 0x870 0xe7 0xe7 0x00 0x874 0x03 0x03 0x00 0x878 0x40 0x40 0x00 0x87c 0x00 0x00 0x00 0x9d8 0x88 0x88 0x00 0xffffffff 0xffffffff 0x00 0x00>; | |
| qcom,qmp-phy-reg-offset = <0x988 0x98c 0x990 0x994 0x974 0x8d8 0x8dc 0x804 0x800 0x808>; | |
| clocks = <0x02 0x9d 0x02 0xa1>; | |
| clock-names = "aux_clk", "pipe_clk"; | |
| resets = <0x02 0x27 0x02 0x28>; | |
| reset-names = "usb3_phy_reset", "usb3phy_phy_reset"; | |
| status = "ok"; | |
| linux,phandle = <0x0a>; | |
| phandle = <0x0a>; | |
| }; | |
| qusb@79000 { | |
| compatible = "qcom,qusb2phy"; | |
| reg = <0x79000 0x180 0x8af8800 0x400 0x1841030 0x04 0x8a0c12c 0x04>; | |
| reg-names = "qusb_phy_base", "qscratch_base", "ref_clk_addr", "usb3_guctl_addr"; | |
| qcom,qusb-phy-init-seq = <0x14 0x00 0xf8 0x80 0xb3 0x84 0x83 0x88 0xc0 0x8c 0x30 0x08 0x79 0x0c 0x21 0x10 0x00 0x90 0x00 0x18 0x14 0x9c 0x80 0x04 0x9f 0x1c>; | |
| phy_type = "utmi"; | |
| resets = <0x02 0x2b>; | |
| reset-names = "usb2_phy_reset"; | |
| status = "ok"; | |
| linux,phandle = <0x09>; | |
| phandle = <0x09>; | |
| }; | |
| qusb@59000 { | |
| compatible = "qcom,qusb2phy"; | |
| reg = <0x59000 0x180 0x70f8800 0x400 0x1841030 0x04 0x700c12c 0x04>; | |
| reg-names = "qusb_phy_base", "qscratch_base", "ref_clk_addr", "usb3_guctl_addr"; | |
| qcom,qusb-phy-init-seq = <0x14 0x00 0xf8 0x80 0xb3 0x84 0x83 0x88 0xc0 0x8c 0x30 0x08 0x79 0x0c 0x21 0x10 0x00 0x90 0x00 0x18 0x14 0x9c 0x80 0x04 0x9f 0x1c>; | |
| phy_type = "utmi"; | |
| resets = <0x02 0x2c>; | |
| reset-names = "usb2_phy_reset"; | |
| status = "disabled"; | |
| linux,phandle = <0x0b>; | |
| phandle = <0x0b>; | |
| }; | |
| dbm@0x8AF8000 { | |
| compatible = "qcom,usb-dbm-1p5"; | |
| reg = <0x8af8000 0x300>; | |
| qcom,reset-ep-after-lpm-resume; | |
| linux,phandle = <0x08>; | |
| phandle = <0x08>; | |
| }; | |
| usb3@8A00000 { | |
| compatible = "qcom,ipq6018-dwc3"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| reg = <0x8af8800 0x100 0x8a00000 0xcd00>; | |
| reg-names = "qscratch_base", "dwc3_base"; | |
| clocks = <0x02 0xb9 0x02 0xba 0x02 0x9e 0x02 0xa2 0x02 0x9f 0x02 0xa0 0x02 0x9d 0x02 0xa1>; | |
| clock-names = "snoc_bus_timeout2", "sys_noc_axi", "master", "sleep", "mock_utmi", "cfg_ahb_clk", "aux_clk", "pipe_clk"; | |
| assigned-clocks = <0x02 0xba 0x02 0x9e 0x02 0x9f>; | |
| assigned-clock-rates = <0x7f27450 0x7f27450 0x16e3600>; | |
| qca,host = <0x01>; | |
| qcom,usb-dbm = <0x08>; | |
| status = "ok"; | |
| dwc3@8A00000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x8a00000 0xcd00>; | |
| interrupts = <0x00 0x8c 0x00>; | |
| usb-phy = <0x09 0x0a>; | |
| tx-fifo-resize; | |
| snps,usb3-u1u2-disable; | |
| snps,nominal-elastic-buffer; | |
| snps,is-utmi-l1-suspend; | |
| snps,hird-threshold = [00]; | |
| snps,dis_u2_susphy_quirk; | |
| snps,dis_u3_susphy_quirk; | |
| snps,quirk-ref-clock-adjustment = <0xa87f0>; | |
| snps,quirk-ref-clock-period = <0x29>; | |
| dr_mode = "host"; | |
| }; | |
| }; | |
| qcom,usbbam@8B04000 { | |
| compatible = "qcom,usb-bam-msm"; | |
| reg = <0x8b04000 0x17000>; | |
| interrupt-parent = <0x01>; | |
| interrupts = <0x00 0x87 0x00>; | |
| qcom,bam-type = <0x00>; | |
| qcom,usb-bam-fifo-baseaddr = <0x4a100000>; | |
| qcom,usb-bam-num-pipes = <0x04>; | |
| qcom,ignore-core-reset-ack; | |
| qcom,disable-clk-gating; | |
| qcom,usb-bam-override-threshold = <0x4001>; | |
| qcom,usb-bam-max-mbps-highspeed = <0x190>; | |
| qcom,usb-bam-max-mbps-superspeed = <0xe10>; | |
| qcom,reset-bam-on-connect; | |
| qcom,pipe0 { | |
| label = "ssusb-qdss-in-0"; | |
| qcom,usb-bam-mem-type = <0x02>; | |
| qcom,dir = <0x01>; | |
| qcom,pipe-num = <0x00>; | |
| qcom,peer-bam = <0x00>; | |
| qcom,peer-bam-physical-address = <0x6064000>; | |
| qcom,src-bam-pipe-index = <0x00>; | |
| qcom,dst-bam-pipe-index = <0x00>; | |
| qcom,data-fifo-offset = <0x00>; | |
| qcom,data-fifo-size = <0xe00>; | |
| qcom,descriptor-fifo-offset = <0xe00>; | |
| qcom,descriptor-fifo-size = <0x200>; | |
| }; | |
| }; | |
| extcon_usb { | |
| compatible = "linux,extcon-usb-gpio"; | |
| status = "disabled"; | |
| }; | |
| usb2@7000000 { | |
| compatible = "qcom,ipq6018-dwc3"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges; | |
| reg = <0x70f8800 0x100 0x7000000 0xcd00>; | |
| reg-names = "qscratch_base", "dwc3_base"; | |
| clocks = <0x02 0xa3 0x02 0xa6 0x02 0xa4 0x02 0xa5>; | |
| clock-names = "master", "sleep", "mock_utmi", "cfg_ahb_clk"; | |
| assigned-clocks = <0x02 0xa3 0x02 0xa4>; | |
| assigned-clock-rates = <0x7f27450 0x16e3600>; | |
| qca,host = <0x01>; | |
| status = "disabled"; | |
| dwc3@7000000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0x7000000 0xcd00>; | |
| interrupts = <0x00 0x63 0x00>; | |
| usb-phy = <0x0b>; | |
| tx-fifo-resize; | |
| snps,usb3-u1u2-disable; | |
| snps,nominal-elastic-buffer; | |
| snps,is-utmi-l1-suspend; | |
| snps,hird-threshold = [00]; | |
| snps,dis_u2_susphy_quirk; | |
| snps,dis_u3_susphy_quirk; | |
| snps,quirk-ref-clock-adjustment = <0xa87f0>; | |
| snps,quirk-ref-clock-period = <0x29>; | |
| dr_mode = "host"; | |
| }; | |
| }; | |
| phy@84000 { | |
| compatible = "qca,pcie-qmp-phy-gen3"; | |
| reg = <0x84000 0x1000>; | |
| phy-type = "gen3"; | |
| qcom,qmp-pcie-phy-init-seq = <0x840 0x03 0x1c 0x7d 0x20 0x01 0x24 0x0a 0x28 0x05 0x2c 0x08 0x30 0x04 0x3c 0x18 0x40 0x90 0x44 0x02 0x48 0x07 0x50 0x0f 0x54 0xd4 0x58 0x14 0x60 0xaa 0x64 0x29 0x74 0x0f 0xffffffff 0x01 0x80 0x09 0x84 0x09 0x88 0x16 0x8c 0x16 0x90 0x28 0x94 0x28 0xa4 0x01 0xa8 0x08 0xb0 0x20 0xc4 0x42 0xcc 0x68 0xd0 0x53 0xd8 0xab 0xdc 0xaa 0xe0 0x02 0xe4 0x55 0xe8 0x55 0xec 0x05 0x100 0xa0 0x108 0xa0 0x124 0x24 0x128 0x02 0x12c 0xb4 0x130 0x03 0x16c 0x32 0x170 0x01 0x184 0x00 0x18c 0x06 0x194 0x05 0x1b4 0x08 0x23c 0x02 0x284 0x06 0x29c 0x12 0x408 0x0c 0x414 0x02 0x434 0x7f 0x444 0x70 0x4ec 0x61 0x4f0 0x04 0x4f4 0x1e 0x4f8 0xc0 0x4fc 0x00 0x510 0x73 0x514 0x80 0x518 0x1c 0x51c 0x03 0x524 0x14 0x570 0xf0 0x574 0x01 0x578 0x2f 0x57c 0xd3 0x580 0x40 0x584 0x01 0x588 0x02 0x58c 0xc8 0x590 0x09 0x594 0xb1 0x598 0x00 0x59c 0x02 0x5a0 0xc8 0x5a4 0x09 0x5a8 0xb1 0x5b4 0x04 0x898 0x01 0x8dc 0x0d 0x96c 0x10 0x988 0xaa 0x9a4 0x01 0x9d8 0x01 0x9ec 0x01 0xc0c 0x0d 0xc14 0x07 0xc1c 0xc1 0xc40 0x01 0xc48 0x01 0xc90 0x00 0xca0 0x11 0xcbc 0x00 0xce0 0x58 0x800 0x00 0x844 0x03>; | |
| #phy-cells = <0x00>; | |
| clocks = <0x02 0x87>; | |
| clock-names = "pipe_clk"; | |
| resets = <0x02 0x45 0x02 0x46>; | |
| reset-names = "phy", "phy_phy"; | |
| status = "ok"; | |
| linux,phandle = <0x0c>; | |
| phandle = <0x0c>; | |
| }; | |
| pci@20000000 { | |
| compatible = "qcom,pcie-ipq6018"; | |
| reg = <0x20000000 0xf1d 0x20000f20 0xa8 0x20001000 0x1000 0x80000 0x2000 0x20100000 0x1000>; | |
| reg-names = "dbi", "elbi", "dm_iatu", "parf", "config"; | |
| device_type = "pci"; | |
| linux,pci-domain = <0x00>; | |
| bus-range = <0x00 0xff>; | |
| num-lanes = <0x01>; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| phys = <0x0c>; | |
| phy-names = "pciephy"; | |
| ranges = <0x81000000 0x00 0x20200000 0x20200000 0x00 0x100000 0x82000000 0x00 0x20300000 0x20300000 0x00 0x10000000>; | |
| interrupts = <0x00 0x34 0x00>; | |
| interrupt-names = "msi"; | |
| #interrupt-cells = <0x01>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x4b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x4e 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x4f 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x53 0x04>; | |
| clocks = <0x02 0xbb 0x02 0x85 0x02 0x86 0x02 0x83 0x02 0x84 0x02 0xc6 0x02 0xc7>; | |
| clock-names = "sys_noc", "axi_m", "axi_s", "ahb", "aux", "axi_bridge", "rchng"; | |
| resets = <0x02 0x60 0x02 0x61 0x02 0x62 0x02 0x63 0x02 0x64 0x02 0x65 0x02 0x66 0x02 0x67>; | |
| reset-names = "pipe", "sleep", "sticky", "axi_m", "axi_s", "ahb", "axi_m_sticky", "axi_s_sticky"; | |
| perst-gpio = <0x0d 0x3c 0x01>; | |
| status = "ok"; | |
| }; | |
| qcom,diag@0 { | |
| compatible = "qcom,diag"; | |
| status = "ok"; | |
| }; | |
| dma@7884000 { | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0x7884000 0x2b000>; | |
| interrupts = <0x00 0xee 0x00>; | |
| clocks = <0x02 0x43>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x00>; | |
| linux,phandle = <0x04>; | |
| phandle = <0x04>; | |
| }; | |
| i2c@78b6000 { | |
| compatible = "qcom,i2c-qup-v2.2.1"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x78b6000 0x600>; | |
| interrupts = <0x00 0x60 0x04>; | |
| clocks = <0x02 0x43 0x02 0x46>; | |
| clock-names = "iface", "core"; | |
| clock-frequency = <0x61a80>; | |
| dmas = <0x04 0x0f 0x04 0x0e>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| i2c@78b7000 { | |
| compatible = "qcom,i2c-qup-v2.2.1"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x78b7000 0x600>; | |
| interrupts = <0x00 0x61 0x04>; | |
| clocks = <0x02 0x43 0x02 0x48>; | |
| clock-names = "iface", "core"; | |
| clock-frequency = <0x61a80>; | |
| dmas = <0x04 0x11 0x04 0x10>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| spi@78b5000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x78b5000 0x600>; | |
| interrupts = <0x00 0x5f 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| clocks = <0x02 0x45 0x02 0x43>; | |
| clock-names = "core", "iface"; | |
| dmas = <0x04 0x0c 0x04 0x0d>; | |
| dma-names = "tx", "rx"; | |
| status = "disabled"; | |
| pinctrl-0 = <0x0e>; | |
| pinctrl-names = "default"; | |
| cs-select = <0x00>; | |
| m25p80@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x00>; | |
| compatible = "n25q128a11"; | |
| linux,modalias = "m25p80", "n25q128a11"; | |
| spi-max-frequency = <0x2faf080>; | |
| use-default-sizes; | |
| }; | |
| }; | |
| spi@78b6000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x78b6000 0x600>; | |
| interrupts = <0x00 0x60 0x00>; | |
| spi-max-frequency = <0x2faf080>; | |
| clocks = <0x02 0x47 0x02 0x43>; | |
| clock-names = "core", "iface"; | |
| dmas = <0x04 0x0e 0x04 0x0f>; | |
| dma-names = "tx", "rx"; | |
| status = "disabled"; | |
| pinctrl-0 = <0x0f>; | |
| pinctrl-names = "default"; | |
| cs-select = <0x00>; | |
| quartz-reset-gpio = <0x0d 0x4a 0x01>; | |
| spi@1 { | |
| compatible = "qca,spidev"; | |
| reg = <0x00>; | |
| spi-max-frequency = <0x16e3600>; | |
| }; | |
| }; | |
| pwm { | |
| compatible = "qca,ipq6018-pwm"; | |
| reg = <0x1941010 0x20>; | |
| clocks = <0x02 0xc1>; | |
| clock-names = "core"; | |
| src-freq = <0x5f5e100>; | |
| pwm-base-index = <0x00>; | |
| used-pwm-indices = <0x01 0x01 0x01 0x01>; | |
| status = "disabled"; | |
| }; | |
| dcc@b3000 { | |
| compatible = "qca,dcc"; | |
| status = "ok"; | |
| reg = <0xb3000 0x1000 0xb4000 0x800 0x4a2000 0x08>; | |
| reg-names = "dcc-base", "dcc-ram-base", "gcnt_lo_hi"; | |
| clocks = <0x02 0xc4>; | |
| clock-names = "dcc_clk"; | |
| no_xpu_support; | |
| qca,save-reg; | |
| }; | |
| syscon@1905000 { | |
| compatible = "syscon"; | |
| reg = <0x1905000 0x8000>; | |
| linux,phandle = <0x10>; | |
| phandle = <0x10>; | |
| }; | |
| hwlock@1905000 { | |
| compatible = "qcom,tcsr-mutex"; | |
| syscon = <0x10 0x00 0x80>; | |
| #hwlock-cells = <0x01>; | |
| linux,phandle = <0x12>; | |
| phandle = <0x12>; | |
| }; | |
| qcom,smem@4AA00000 { | |
| compatible = "qcom,smem"; | |
| memory-region = <0x11>; | |
| hwlocks = <0x12 0x00>; | |
| }; | |
| qcom,glink-smem-native-xprt-modem@4AA00000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg = <0x4aa00000 0x100000 0xb111008 0x04>; | |
| reg-names = "smem", "irq-reg-base"; | |
| qcom,irq-mask = <0x100>; | |
| interrupts = <0x00 0x141 0x01>; | |
| label = "mpss"; | |
| qcom,subsys-id = <0x01>; | |
| smem-entry = <0x1de 0x1df 0x1e0>; | |
| smem-entry-names = "ch", "tx_fifo", "rx_fifo"; | |
| }; | |
| qcom,glink-smem-native-xprt-adsp@4AA00000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg = <0x4aa00000 0x100000 0xb111008 0x04>; | |
| reg-names = "smem", "irq-reg-base"; | |
| qcom,irq-mask = <0x800000>; | |
| interrupts = <0x00 0x18 0x01>; | |
| label = "adsp"; | |
| qcom,subsys-id = <0x02>; | |
| smem-entry = <0x1de 0x1df 0x1e0>; | |
| smem-entry-names = "ch", "tx_fifo", "rx_fifo"; | |
| status = "disabled"; | |
| }; | |
| qcom,glink-rpm-native-xprt@60000 { | |
| compatible = "qcom,glink-rpm-native-xprt"; | |
| reg = <0x60000 0x6000 0xb111008 0x04>; | |
| reg-names = "msgram", "irq-reg-base"; | |
| qcom,irq-mask = <0x01>; | |
| interrupts = <0x00 0xa8 0x01>; | |
| label = "rpm"; | |
| qcom,subsys-id = <0x06>; | |
| status = "ok"; | |
| }; | |
| qcom,rpm-glink { | |
| compatible = "qcom,rpm-glink"; | |
| qcom,glink-edge = "rpm"; | |
| rpm-channel-name = "rpm_requests"; | |
| qcom,rpm-channel-type = <0x0f>; | |
| status = "ok"; | |
| rpm-regulator-smpa1 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x01>; | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| status = "disabled"; | |
| regulator-s1 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_s1"; | |
| qcom,set = <0x03>; | |
| regulator-min-microvolt = <0xcf850>; | |
| regulator-max-microvolt = <0xf116c>; | |
| qcom,always-send-voltage; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-smpa2 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x02>; | |
| qcom,regulator-type = <0x01>; | |
| status = "ok"; | |
| regulator-s2 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_s2"; | |
| regulator-min-microvolt = <0x8f6ec>; | |
| regulator-max-microvolt = <0x10c8e0>; | |
| qcom,always-send-voltage; | |
| qcom,set = <0x03>; | |
| status = "ok"; | |
| linux,phandle = <0x48>; | |
| phandle = <0x48>; | |
| }; | |
| }; | |
| rpm-regulator-smpa3 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x03>; | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| status = "disabled"; | |
| regulator-s3 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_s3"; | |
| regulator-min-microvolt = <0x9c400>; | |
| regulator-max-microvolt = <0xbe6e0>; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-smpa4 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x04>; | |
| qcom,regulator-type = <0x01>; | |
| qcom,hpm-min-load = <0x186a0>; | |
| status = "disabled"; | |
| regulator-s5 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_s4"; | |
| qcom,set = <0x01>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa2 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x02>; | |
| qcom,regulator-type = <0x00>; | |
| status = "ok"; | |
| regulator-l2 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_l2"; | |
| regulator-min-microvolt = <0x10d880>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| qcom,always-send-voltage; | |
| qcom,set = <0x03>; | |
| status = "ok"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa3 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x03>; | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| status = "disabled"; | |
| regulator-l3 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_l3"; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa4 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x04>; | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| status = "disabled"; | |
| regulator-l4 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_l4"; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| rpm-regulator-ldoa5 { | |
| compatible = "qcom,rpm-glink-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x05>; | |
| qcom,regulator-type = <0x00>; | |
| qcom,hpm-min-load = <0x2710>; | |
| status = "disabled"; | |
| regulator-l5 { | |
| compatible = "qcom,rpm-glink-regulator"; | |
| regulator-name = "ipq6018_l5"; | |
| qcom,set = <0x03>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| }; | |
| qcom,ipc_router { | |
| compatible = "qcom,ipc_router"; | |
| qcom,node-id = <0x01>; | |
| }; | |
| qcom,ipc_router_modem_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,xprt-remote = "mpss"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,xprt-version = <0x01>; | |
| qcom,fragmented-data; | |
| }; | |
| qcom,ipc_router_adsp_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,xprt-remote = "adsp"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-linkid = <0x01>; | |
| qcom,xprt-version = <0x01>; | |
| qcom,fragmented-data; | |
| status = "disabled"; | |
| }; | |
| syscon@b111000 { | |
| compatible = "syscon"; | |
| reg = <0xb111000 0x1000>; | |
| linux,phandle = <0x13>; | |
| phandle = <0x13>; | |
| }; | |
| smp2p-wcss { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <0x1b3 0x1ac>; | |
| interrupt-parent = <0x01>; | |
| interrupts = <0x00 0x142 0x01>; | |
| qcom,ipc = <0x13 0x08 0x09>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x01>; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| qcom,smp2p-feature-ssr-ack; | |
| #qcom,smem-state-cells = <0x01>; | |
| linux,phandle = <0x15>; | |
| phandle = <0x15>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| linux,phandle = <0x14>; | |
| phandle = <0x14>; | |
| }; | |
| }; | |
| smp2p-adsp { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <0x1bb 0x1ad>; | |
| status = "disabled"; | |
| interrupt-parent = <0x01>; | |
| interrupts = <0x00 0x1a 0x01>; | |
| qcom,ipc = <0x13 0x08 0x15>; | |
| qcom,local-pid = <0x00>; | |
| qcom,remote-pid = <0x02>; | |
| master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| qcom,smp2p-feature-ssr-ack; | |
| #qcom,smem-state-cells = <0x01>; | |
| linux,phandle = <0x1b>; | |
| phandle = <0x1b>; | |
| }; | |
| slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| linux,phandle = <0x1a>; | |
| phandle = <0x1a>; | |
| }; | |
| }; | |
| q6v5_wcss@CD00000 { | |
| compatible = "qca,q6v5-wcss-rproc-ipq60xx"; | |
| firmware = "IPQ6018/q6_fw.mdt"; | |
| reg = <0xcd00000 0x4040 0x194f000 0x10 0x1952000 0x10 0x4ab000 0x20 0x1818000 0x110 0x1859000 0x10 0x1945000 0x10>; | |
| reg-names = "wcss-base", "tcsr-q6-base", "tcsr-base", "mpm-base", "gcc-wcss-bcr-base", "gcc-wcss-misc-base", "tcsr-global"; | |
| clocks = <0x02 0xce 0x02 0xcf 0x02 0xd0 0x02 0xd1 0x02 0xcb 0x02 0xcc 0x02 0xcd 0x02 0xd2 0x02 0xd4>; | |
| clock-names = "wcss_axi_m_clk", "sys_noc_wcss_ahb_clk", "q6_axim_clk", "q6ss_atbm_clk", "q6ss_pclkdbg_clk", "q6_tsctr_1to2_clk", "wcss_core_tbu_clk", "wcss_q6_tbu_clk", "gcc_q6_ahb_clk"; | |
| qca,auto-restart; | |
| qca,extended-intc; | |
| qca,sec-reset-cmd = <0x18>; | |
| qca,secure; | |
| interrupts-extended = <0x01 0x00 0x145 0x01 0x14 0x00 0x00 0x14 0x01 0x00 0x14 0x03 0x00>; | |
| interrupt-names = "wdog", "qcom,gpio-err-fatal", "qcom,gpio-err-ready", "qcom,gpio-stop-ack"; | |
| qcom,smem-states = <0x15 0x00 0x15 0x01>; | |
| qcom,smem-state-names = "shutdown", "stop"; | |
| memory-region = <0x16 0x17>; | |
| linux,phandle = <0x19>; | |
| phandle = <0x19>; | |
| }; | |
| q6v5_m3 { | |
| compatible = "qca,q6v5-m3-rproc"; | |
| firmware = "IPQ6018/m3_fw.mdt"; | |
| qca,auto-restart; | |
| qcom,restart-group = <0x18 0x19>; | |
| linux,phandle = <0x18>; | |
| phandle = <0x18>; | |
| }; | |
| q6v6_adsp@AB00000 { | |
| status = "disabled"; | |
| compatible = "qca,q6v6-adsp-rproc"; | |
| firmware = "IPQ6018/adsp.mdt"; | |
| reg = <0xab00000 0x4040 0x181f000 0x04 0xa000000 0x48000 0x1954010 0x20>; | |
| reg-names = "adsp-base", "gcc-adsp-bcr-base", "adsp-cc-base", "tcsr-base"; | |
| qca,extended-intc; | |
| qca,sec-reset-cmd = <0x18>; | |
| qca,secure; | |
| interrupts-extended = <0x01 0x00 0x1e 0x01 0x1a 0x00 0x00 0x1a 0x01 0x00 0x1a 0x03 0x00>; | |
| interrupt-names = "wdog", "qcom,gpio-err-fatal", "qcom,gpio-err-ready", "qcom,gpio-stop-ack"; | |
| qcom,smem-states = <0x1b 0x00 0x1b 0x01>; | |
| qcom,smem-state-names = "shutdown", "stop"; | |
| clocks = <0x02 0xf5 0x02 0xf6 0x02 0xe4 0x02 0xe5 0x02 0xe6 0x02 0xe7 0x02 0xe8 0x02 0xe9 0x02 0xea 0x02 0xeb 0x02 0xef>; | |
| clock-names = "mem_noc_lpass_clk", "snoc_lpass_cfg_clk", "lpass_core_axim_clk", "lpass_snoc_cfg_clk", "lpass_q6_axim_clk", "lpass_q6_atbm_at_clk", "lpass_q6_pclkdbg_clk", "lpass_q6ss_tsctr_1to2_clk", "lpass_q6ss_trig_clk", "lpass_tbu_clk", "pcnoc_lpass_clk"; | |
| }; | |
| qcom,glink-ssr-modem { | |
| compatible = "qcom,glink_ssr"; | |
| label = "q6v5-wcss"; | |
| qcom,edge = "mpss"; | |
| qca,no-notify-edges; | |
| qcom,xprt = "smem"; | |
| }; | |
| qcom,glink-ssr-adsp { | |
| compatible = "qcom,glink_ssr"; | |
| label = "q6v6-adsp"; | |
| qcom,edge = "adsp"; | |
| qcom,notify-edges = <0x1c>; | |
| qcom,xprt = "smem"; | |
| status = "disabled"; | |
| }; | |
| qcom,glink-ssr-rpm { | |
| compatible = "qcom,glink_ssr"; | |
| label = "rpm"; | |
| qcom,edge = "rpm"; | |
| qcom,no-notify-edges; | |
| qcom,xprt = "smem"; | |
| linux,phandle = <0x1c>; | |
| phandle = <0x1c>; | |
| }; | |
| dma@7984000 { | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0x7984000 0x1a000>; | |
| interrupts = <0x00 0x92 0x00>; | |
| clocks = <0x02 0x89>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <0x01>; | |
| qcom,ee = <0x00>; | |
| status = "ok"; | |
| linux,phandle = <0x07>; | |
| phandle = <0x07>; | |
| }; | |
| qcom,sps { | |
| compatible = "qcom,msm_sps_4k"; | |
| qcom,pipe-attr-ee; | |
| }; | |
| qpic-nand@79b0000 { | |
| compatible = "qcom,ebi2-nandc-bam-v1.5.0"; | |
| reg = <0x79b0000 0x10000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| clocks = <0x02 0x8a 0x02 0x89>; | |
| clock-names = "core", "aon"; | |
| dmas = <0x07 0x00 0x07 0x01 0x07 0x02>; | |
| dma-names = "tx", "rx", "cmd"; | |
| status = "ok"; | |
| pinctrl-0 = <0x1d>; | |
| pinctrl-names = "default"; | |
| nandcs@0 { | |
| compatible = "qcom,nandcs"; | |
| reg = <0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| nand-ecc-strength = <0x04>; | |
| nand-ecc-step-size = <0x200>; | |
| nand-bus-width = <0x08>; | |
| }; | |
| }; | |
| sdcc1ice@7808000 { | |
| compatible = "qcom,ice"; | |
| reg = <0x7808000 0x2000>; | |
| interrupts = <0x00 0x138 0x00>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x00 0x00 0x4e 0x200 0x3e8 0x00>; | |
| qcom,bus-vector-names = "MIN", "MAX"; | |
| qcom,instance-type = "sdcc"; | |
| linux,phandle = <0x1e>; | |
| phandle = <0x1e>; | |
| }; | |
| sdhci@7804000 { | |
| compatible = "qcom,sdhci-msm-v5"; | |
| reg = <0x7804000 0x1000 0x7805000 0x1000>; | |
| reg-names = "hc_mem", "cmdq_mem"; | |
| interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>; | |
| interrupt-names = "hc_irq", "pwr_irq"; | |
| qcom,bus-width = <0x08>; | |
| sdhc-msm-crypto = <0x1e>; | |
| qcom,max_clk = <0xb71b000>; | |
| qcom,dedicated-io = <0x01>; | |
| qcom,vdd-voltage-level = <0x2c4020 0x2c4020>; | |
| qcom,vdd-current-level = <0xc8 0x8b290>; | |
| qcom,vdd-io-lpm-sup; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>; | |
| qcom,vdd-io-current-level = <0xc8 0x4f588>; | |
| qcom,vdd-io-always-on; | |
| qcom,cpu-dma-latency-us = <0x2bd>; | |
| qcom,msm-bus,name = "sdhc1"; | |
| qcom,msm-bus,num-cases = <0x09>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x00 0x00 0x4e 0x200 0x416 0xc80 0x4e 0x200 0xcc3e 0x27100 0x4e 0x200 0xff50 0x30d40 0x4e 0x200 0x1fe9e 0x61a80 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x3fd3e 0xc3500 0x4e 0x200 0x146cc2 0x3e8000>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0x17d78400 0xffffffff>; | |
| clocks = <0x02 0x8b 0x02 0x8c 0x02 0xc3>; | |
| clock-names = "iface_clk", "core_clk", "ice_core_clk"; | |
| qcom,ice-clk-rates = <0x9896800 0x12646790>; | |
| qcom,large-address-bus; | |
| qcom,disable-aggressive-pm; | |
| qcom,clk-rates = <0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xb71b000>; | |
| qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; | |
| qcom,nonremovable; | |
| status = "disabled"; | |
| }; | |
| sdhci_sd@7804000 { | |
| compatible = "qcom,sdhci-msm-v5"; | |
| reg = <0x7804000 0x1000>; | |
| reg-names = "hc_mem"; | |
| interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>; | |
| interrupt-names = "hc_irq", "pwr_irq"; | |
| qcom,max_clk = <0xb71b000>; | |
| qcom,bus-width = <0x04>; | |
| qcom,dedicated-io = <0x01>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| qcom,vdd-current-level = <0x3a98 0x61a80>; | |
| qcom,vdd-io-lpm-sup; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>; | |
| qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
| qcom,vdd-io-always-on; | |
| qcom,cpu-dma-latency-us = <0x2bd>; | |
| qcom,msm-bus,name = "sdhc2"; | |
| qcom,msm-bus,num-cases = <0x08>; | |
| qcom,msm-bus,num-paths = <0x01>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x00 0x00 0x51 0x200 0x416 0xc80 0x51 0x200 0xcc3e 0x27100 0x51 0x200 0xff50 0x30d40 0x51 0x200 0x1fe9e 0x61a80 0x51 0x200 0x3fd3e 0xc3500 0x51 0x200 0x3fd3e 0xc3500 0x51 0x200 0x146cc2 0x3e8000>; | |
| qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| clocks = <0x02 0x8b 0x02 0x8c>; | |
| clock-names = "iface_clk", "core_clk"; | |
| qcom,large-address-bus; | |
| qcom,disable-aggressive-pm; | |
| qcom,clk-rates = <0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xb71b000>; | |
| qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; | |
| status = "disabled"; | |
| }; | |
| edma@3ab00000 { | |
| compatible = "qcom,edma"; | |
| reg = <0x3ab00000 0xabe00>; | |
| reg-names = "edma-reg-base"; | |
| qcom,txdesc-ring-start = <0x17>; | |
| qcom,txdesc-rings = <0x01>; | |
| qcom,txcmpl-ring-start = <0x17>; | |
| qcom,txcmpl-rings = <0x01>; | |
| qcom,rxfill-ring-start = <0x07>; | |
| qcom,rxfill-rings = <0x01>; | |
| qcom,rxdesc-ring-start = <0x0f>; | |
| qcom,rxdesc-rings = <0x01>; | |
| interrupts = <0x00 0x17a 0x04 0x00 0x162 0x04 0x00 0x15a 0x04 0x00 0x17b 0x04>; | |
| resets = <0x02 0x6d>; | |
| reset-names = "edma_rst"; | |
| }; | |
| nss-common { | |
| compatible = "qcom,nss-common"; | |
| reg = <0x1868010 0x1000 0x40000000 0x1000>; | |
| reg-names = "nss-misc-reset", "nss-misc-reset-flag"; | |
| }; | |
| nss@40000000 { | |
| compatible = "qcom,nss"; | |
| interrupts = <0x00 0x192 0x01 0x00 0x191 0x01 0x00 0x190 0x01 0x00 0x18f 0x01 0x00 0x18e 0x01 0x00 0x18d 0x01 0x00 0x18c 0x01 0x00 0x18b 0x01 0x00 0x18a 0x01>; | |
| reg = <0x39000000 0x1000 0xb111000 0x1000>; | |
| reg-names = "nphys", "qgic-phys"; | |
| clocks = <0x02 0x64 0x02 0x72 0x02 0x61 0x02 0x5f 0x02 0x78 0x02 0xae 0x02 0x79 0x02 0xf4 0x02 0x5e 0x02 0x5d 0x02 0x74 0x02 0x73 0x02 0x7a 0x02 0x82 0x02 0x80 0x02 0x81 0x02 0xaf 0x02 0xf0 0x02 0xf2>; | |
| clock-names = "nss-noc-clk", "nss-ptp-ref-clk", "nss-csr-clk", "nss-cfg-clk", "nss-nssnoc-qosgen-ref-clk", "nss-nssnoc-snoc-clk", "nss-nssnoc-timeout-ref-clk", "nss-mem-noc-ubi32-clk", "nss-ce-axi-clk", "nss-ce-apb-clk", "nss-nssnoc-ce-axi-clk", "nss-nssnoc-ce-apb-clk", "nss-nssnoc-ahb-clk", "nss-core-clk", "nss-ahb-clk", "nss-axi-clk", "nss-nc-axi-clk", "nss-utcm-clk", "nss-snoc-nssnoc-clk"; | |
| qcom,id = <0x00>; | |
| qcom,num-queue = <0x04>; | |
| qcom,num-irq = <0x09>; | |
| qcom,num-pri = <0x04>; | |
| qcom,load-addr = <0x40000000>; | |
| qcom,low-frequency = "\v(r"; | |
| qcom,mid-frequency = <0x2ca1c800>; | |
| qcom,max-frequency = <0x59439000>; | |
| qcom,bridge-enabled; | |
| qcom,ipv4-enabled; | |
| qcom,ipv4-reasm-enabled; | |
| qcom,ipv6-enabled; | |
| qcom,ipv6-reasm-enabled; | |
| qcom,wlanredirect-enabled; | |
| qcom,tun6rd-enabled; | |
| qcom,l2tpv2-enabled; | |
| qcom,gre-enabled; | |
| qcom,gre-redir-enabled; | |
| qcom,gre-redir-mark-enabled; | |
| qcom,map-t-enabled; | |
| qcom,portid-enabled; | |
| qcom,ppe-enabled; | |
| qcom,pppoe-enabled; | |
| qcom,pptp-enabled; | |
| qcom,tunipip6-enabled; | |
| qcom,shaping-enabled; | |
| qcom,wlan-dataplane-offload-enabled; | |
| qcom,vlan-enabled; | |
| qcom,capwap-enabled; | |
| qcom,dtls-enabled; | |
| qcom,crypto-enabled; | |
| qcom,ipsec-enabled; | |
| qcom,qvpn-enabled; | |
| qcom,pvxlan-enabled; | |
| qcom,clmap-enabled; | |
| }; | |
| qcom,nss_crypto { | |
| compatible = "qcom,nss-crypto"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| qcom,max-contexts = <0x40>; | |
| qcom,max-context-size = <0x20>; | |
| ranges; | |
| status = "ok"; | |
| eip197_node { | |
| compatible = "qcom,eip197"; | |
| reg-names = "crypto_pbase"; | |
| reg = <0x39800000 0x7ffff>; | |
| clocks = <0x02 0x60 0x02 0x75 0x02 0x5c>; | |
| clock-names = "crypto_clk", "crypto_nocclk", "crypto_ppeclk"; | |
| clock-frequency = <0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x11e1a300>; | |
| qcom,dma-mask = <0xff>; | |
| qcom,transform-enabled; | |
| qcom,aes128-cbc; | |
| qcom,aes192-cbc; | |
| qcom,aes256-cbc; | |
| qcom,aes128-ctr; | |
| qcom,aes192-ctr; | |
| qcom,aes256-ctr; | |
| qcom,aes128-ecb; | |
| qcom,aes192-ecb; | |
| qcom,aes256-ecb; | |
| qcom,3des-cbc; | |
| qcom,md5-hash; | |
| qcom,sha160-hash; | |
| qcom,sha224-hash; | |
| qcom,sha256-hash; | |
| qcom,sha384-hash; | |
| qcom,sha512-hash; | |
| qcom,md5-hmac; | |
| qcom,sha160-hmac; | |
| qcom,sha256-hmac; | |
| qcom,sha384-hmac; | |
| qcom,sha512-hmac; | |
| qcom,aes128-gcm-gmac; | |
| qcom,aes192-gcm-gmac; | |
| qcom,aes256-gcm-gmac; | |
| qcom,aes128-cbc-md5-hmac; | |
| qcom,aes128-cbc-sha160-hmac; | |
| qcom,aes192-cbc-md5-hmac; | |
| qcom,aes192-cbc-sha160-hmac; | |
| qcom,aes256-cbc-md5-hmac; | |
| qcom,aes256-cbc-sha160-hmac; | |
| qcom,aes128-ctr-sha160-hmac; | |
| qcom,aes192-ctr-sha160-hmac; | |
| qcom,aes256-ctr-sha160-hmac; | |
| qcom,aes128-ctr-md5-hmac; | |
| qcom,aes192-ctr-md5-hmac; | |
| qcom,aes256-ctr-md5-hmac; | |
| qcom,3des-cbc-md5-hmac; | |
| qcom,3des-cbc-sha160-hmac; | |
| qcom,aes128-cbc-sha256-hmac; | |
| qcom,aes192-cbc-sha256-hmac; | |
| qcom,aes256-cbc-sha256-hmac; | |
| qcom,aes128-ctr-sha256-hmac; | |
| qcom,aes192-ctr-sha256-hmac; | |
| qcom,aes256-ctr-sha256-hmac; | |
| qcom,3des-cbc-sha256-hmac; | |
| qcom,aes128-cbc-sha384-hmac; | |
| qcom,aes192-cbc-sha384-hmac; | |
| qcom,aes256-cbc-sha384-hmac; | |
| qcom,aes128-ctr-sha384-hmac; | |
| qcom,aes192-ctr-sha384-hmac; | |
| qcom,aes256-ctr-sha384-hmac; | |
| qcom,aes128-cbc-sha512-hmac; | |
| qcom,aes192-cbc-sha512-hmac; | |
| qcom,aes256-cbc-sha512-hmac; | |
| qcom,aes128-ctr-sha512-hmac; | |
| qcom,aes192-ctr-sha512-hmac; | |
| qcom,aes256-ctr-sha512-hmac; | |
| engine0 { | |
| reg_offset = <0x80000>; | |
| qcom,ifpp-enabled; | |
| qcom,ipue-enabled; | |
| qcom,ofpp-enabled; | |
| qcom,opue-enabled; | |
| }; | |
| }; | |
| }; | |
| clock-controller@b188000 { | |
| compatible = "qcom,arm-cortex-acc"; | |
| reg = <0xb188000 0x1000>; | |
| linux,phandle = <0x4a>; | |
| phandle = <0x4a>; | |
| }; | |
| clock-controller@b198000 { | |
| compatible = "qcom,arm-cortex-acc"; | |
| reg = <0xb198000 0x1000>; | |
| linux,phandle = <0x4f>; | |
| phandle = <0x4f>; | |
| }; | |
| clock-controller@b1a8000 { | |
| compatible = "qcom,arm-cortex-acc"; | |
| reg = <0xb1a8000 0x1000>; | |
| linux,phandle = <0x50>; | |
| phandle = <0x50>; | |
| }; | |
| clock-controller@b1b8000 { | |
| compatible = "qcom,arm-cortex-acc"; | |
| reg = <0xb1b8000 0x1000>; | |
| linux,phandle = <0x51>; | |
| phandle = <0x51>; | |
| }; | |
| pinctrl@1000000 { | |
| compatible = "qcom,ipq6018-pinctrl"; | |
| reg = <0x1000000 0x300000>; | |
| interrupts = <0x00 0xd0 0x00>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| linux,phandle = <0x0d>; | |
| phandle = <0x0d>; | |
| uart_pins { | |
| linux,phandle = <0x05>; | |
| phandle = <0x05>; | |
| mux { | |
| pins = "gpio44", "gpio45"; | |
| function = "blsp2_uart"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| spi_0_pins { | |
| linux,phandle = <0x0e>; | |
| phandle = <0x0e>; | |
| mux { | |
| pins = "gpio38", "gpio39", "gpio40", "gpio41"; | |
| function = "blsp0_spi"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| spi_1_pins { | |
| linux,phandle = <0x0f>; | |
| phandle = <0x0f>; | |
| mux { | |
| pins = "gpio69", "gpio71", "gpio72"; | |
| function = "blsp1_spi"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| spi_cs { | |
| pins = "gpio70"; | |
| function = "blsp1_spi"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| quartz_interrupt { | |
| pins = "gpio73"; | |
| function = "gpio"; | |
| input; | |
| bias-disable; | |
| }; | |
| quartz_reset { | |
| pins = "gpio74"; | |
| function = "gpio"; | |
| output-low; | |
| bias-disable; | |
| }; | |
| }; | |
| qpic_pins { | |
| linux,phandle = <0x1d>; | |
| phandle = <0x1d>; | |
| data_0 { | |
| pins = "gpio15"; | |
| function = "qpic_pad0"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_1 { | |
| pins = "gpio12"; | |
| function = "qpic_pad1"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_2 { | |
| pins = "gpio13"; | |
| function = "qpic_pad2"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_3 { | |
| pins = "gpio14"; | |
| function = "qpic_pad3"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_4 { | |
| pins = "gpio5"; | |
| function = "qpic_pad4"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_5 { | |
| pins = "gpio6"; | |
| function = "qpic_pad5"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_6 { | |
| pins = "gpio7"; | |
| function = "qpic_pad6"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| data_7 { | |
| pins = "gpio8"; | |
| function = "qpic_pad7"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| qpic_pad { | |
| pins = "gpio1", "gpio3", "gpio4", "gpio10", "gpio11", "gpio17"; | |
| function = "qpic_pad"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| button_pins { | |
| wps_button { | |
| pins = "gpio9"; | |
| function = "gpio"; | |
| drive-strength = <0x08>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| mdio_pinmux { | |
| linux,phandle = <0x20>; | |
| phandle = <0x20>; | |
| mux_0 { | |
| pins = "gpio64"; | |
| function = "mdc"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| mux_1 { | |
| pins = "gpio65"; | |
| function = "mdio"; | |
| drive-strength = <0x08>; | |
| bias-pull-up; | |
| }; | |
| mux_2 { | |
| pins = "gpio77"; | |
| function = "gpio"; | |
| bias-pull-up; | |
| }; | |
| }; | |
| hsuart_pins { | |
| linux,phandle = <0x03>; | |
| phandle = <0x03>; | |
| mux { | |
| pins = "gpio55", "gpio56", "gpio57", "gpio58"; | |
| function = "blsp4_uart"; | |
| drive-strength = <0x08>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| watchdog@b017000 { | |
| compatible = "qcom,kpss-wdt-ipq6018"; | |
| reg = <0xb017000 0x1000>; | |
| reg-names = "kpss_wdt"; | |
| interrupt-names = "bark_irq"; | |
| interrupts = <0x00 0x03 0x00>; | |
| clocks = <0x1f>; | |
| timeout-sec = <0x1e>; | |
| wdt-max-timeout = <0x20>; | |
| }; | |
| mdio@90000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio"; | |
| reg = <0x90000 0x64>; | |
| status = "ok"; | |
| pinctrl-0 = <0x20>; | |
| pinctrl-names = "default"; | |
| phy-reset-gpio = <0x0d 0x4d 0x00>; | |
| linux,phandle = <0x49>; | |
| phandle = <0x49>; | |
| ethernet-phy@0 { | |
| reg = <0x10>; | |
| }; | |
| ethernet-phy@1 { | |
| reg = <0x14>; | |
| }; | |
| }; | |
| ess-switch@3a000000 { | |
| compatible = "qcom,ess-switch-ipq60xx"; | |
| reg = <0x3a000000 0x1000000>; | |
| switch_access_mode = "local bus"; | |
| clocks = <0x02 0xb7 0x02 0xb8 0x02 0x8d 0x02 0x98 0x02 0x99 0x02 0x9c 0x02 0x7b 0x02 0x7c 0x02 0x7d 0x02 0x7e 0x02 0x7f 0x02 0x70 0x02 0x6f 0x02 0x77 0x02 0x76 0x02 0x63 0x02 0x62 0x02 0x71 0x02 0x5b 0x02 0x64 0x02 0xae 0x02 0x60 0x02 0x72 0x02 0x65 0x02 0x66 0x02 0x67 0x02 0x68 0x02 0x69 0x02 0x6a 0x02 0x6b 0x02 0x6c 0x02 0x6d 0x02 0x6e 0x02 0x8e 0x02 0x8f 0x02 0x90 0x02 0x91 0x02 0x92 0x02 0x93 0x02 0x94 0x02 0x95 0x02 0x96 0x02 0x97 0x02 0x9a 0x02 0x9b 0x02 0x0c 0x02 0x0d 0x02 0xf2>; | |
| clock-names = "cmn_ahb_clk", "cmn_sys_clk", "uniphy0_ahb_clk", "uniphy0_sys_clk", "uniphy1_ahb_clk", "uniphy1_sys_clk", "port1_mac_clk", "port2_mac_clk", "port3_mac_clk", "port4_mac_clk", "port5_mac_clk", "nss_ppe_clk", "nss_ppe_cfg_clk", "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk", "nss_edma_clk", "nss_edma_cfg_clk", "nss_ppe_ipe_clk", "gcc_mdio_ahb_clk", "gcc_nss_noc_clk", "gcc_nssnoc_snoc_clk", "gcc_nss_crypto_clk", "gcc_nss_ptp_ref_clk", "nss_port1_rx_clk", "nss_port1_tx_clk", "nss_port2_rx_clk", "nss_port2_tx_clk", "nss_port3_rx_clk", "nss_port3_tx_clk", "nss_port4_rx_clk", "nss_port4_tx_clk", "nss_port5_rx_clk", "nss_port5_tx_clk", "uniphy0_port1_rx_clk", "uniphy0_port1_tx_clk", "uniphy0_port2_rx_clk", "uniphy0_port2_tx_clk", "uniphy0_port3_rx_clk", "uniphy0_port3_tx_clk", "uniphy0_port4_rx_clk", "uniphy0_port4_tx_clk", "uniphy0_port5_rx_clk", "uniphy0_port5_tx_clk", "uniphy1_port5_rx_clk", "uniphy1_port5_tx_clk", "nss_port5_rx_clk_src", "nss_port5_tx_clk_src", "gcc_snoc_nssnoc_clk"; | |
| resets = <0x02 0x68 0x02 0x69 0x02 0x6a 0x02 0x6b 0x02 0x6c 0x02 0x70 0x02 0x71 0x02 0x72 0x02 0x73 0x02 0x74 0x02 0x75 0x02 0x76 0x02 0x77 0x02 0x78 0x02 0x79 0x02 0x7a 0x02 0x7b>; | |
| reset-names = "ppe_rst", "uniphy0_soft_rst", "uniphy0_xpcs_rst", "uniphy1_soft_rst", "uniphy1_xpcs_rst", "nss_port1_rst", "nss_port2_rst", "nss_port3_rst", "nss_port4_rst", "nss_port5_rst", "uniphy0_port1_dis", "uniphy0_port2_dis", "uniphy0_port3_dis", "uniphy0_port4_dis", "uniphy0_port5_dis", "uniphy0_port_4_5_rst", "uniphy0_port_4_rst"; | |
| switch_cpu_bmp = <0x01>; | |
| switch_lan_bmp = <0x10>; | |
| switch_wan_bmp = <0x20>; | |
| switch_inner_bmp = <0xc0>; | |
| switch_mac_mode = <0x0f>; | |
| switch_mac_mode1 = <0x0f>; | |
| switch_mac_mode2 = <0xff>; | |
| bm_tick_mode = <0x00>; | |
| tm_tick_mode = <0x00>; | |
| port_scheduler_resource { | |
| port@0 { | |
| port_id = <0x00>; | |
| ucast_queue = <0x00 0x8f>; | |
| mcast_queue = <0x100 0x10f>; | |
| l0sp = <0x00 0x23>; | |
| l0cdrr = <0x00 0x2f>; | |
| l0edrr = <0x00 0x2f>; | |
| l1cdrr = <0x00 0x07>; | |
| l1edrr = <0x00 0x07>; | |
| }; | |
| port@1 { | |
| port_id = <0x01>; | |
| ucast_queue = <0x90 0x9f>; | |
| mcast_queue = <0x110 0x113>; | |
| l0sp = <0x24 0x27>; | |
| l0cdrr = <0x30 0x3f>; | |
| l0edrr = <0x30 0x3f>; | |
| l1cdrr = <0x08 0x0b>; | |
| l1edrr = <0x08 0x0b>; | |
| }; | |
| port@2 { | |
| port_id = <0x02>; | |
| ucast_queue = <0xa0 0xaf>; | |
| mcast_queue = <0x114 0x117>; | |
| l0sp = <0x28 0x2b>; | |
| l0cdrr = <0x40 0x4f>; | |
| l0edrr = <0x40 0x4f>; | |
| l1cdrr = <0x0c 0x0f>; | |
| l1edrr = <0x0c 0x0f>; | |
| }; | |
| port@3 { | |
| port_id = <0x03>; | |
| ucast_queue = <0xb0 0xbf>; | |
| mcast_queue = <0x118 0x11b>; | |
| l0sp = <0x2c 0x2f>; | |
| l0cdrr = <0x50 0x5f>; | |
| l0edrr = <0x50 0x5f>; | |
| l1cdrr = <0x10 0x13>; | |
| l1edrr = <0x10 0x13>; | |
| }; | |
| port@4 { | |
| port_id = <0x04>; | |
| ucast_queue = <0xc0 0xcf>; | |
| mcast_queue = <0x11c 0x11f>; | |
| l0sp = <0x30 0x33>; | |
| l0cdrr = <0x60 0x6f>; | |
| l0edrr = <0x60 0x6f>; | |
| l1cdrr = <0x14 0x17>; | |
| l1edrr = <0x14 0x17>; | |
| }; | |
| port@5 { | |
| port_id = <0x05>; | |
| ucast_queue = <0xd0 0xdf>; | |
| mcast_queue = <0x120 0x123>; | |
| l0sp = <0x34 0x37>; | |
| l0cdrr = <0x70 0x7f>; | |
| l0edrr = <0x70 0x7f>; | |
| l1cdrr = <0x18 0x1b>; | |
| l1edrr = <0x18 0x1b>; | |
| }; | |
| port@6 { | |
| port_id = <0x06>; | |
| ucast_queue = <0xe0 0xef>; | |
| mcast_queue = <0x124 0x127>; | |
| l0sp = <0x38 0x3b>; | |
| l0cdrr = <0x80 0x8f>; | |
| l0edrr = <0x80 0x8f>; | |
| l1cdrr = <0x1c 0x1f>; | |
| l1edrr = <0x1c 0x1f>; | |
| }; | |
| port@7 { | |
| port_id = <0x07>; | |
| ucast_queue = <0xf0 0xff>; | |
| mcast_queue = <0x128 0x12b>; | |
| l0sp = <0x3c 0x3f>; | |
| l0cdrr = <0x90 0x9f>; | |
| l0edrr = <0x90 0x9f>; | |
| l1cdrr = <0x20 0x23>; | |
| l1edrr = <0x20 0x23>; | |
| }; | |
| }; | |
| port_scheduler_config { | |
| port@0 { | |
| port_id = <0x00>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x00 0x01>; | |
| cfg = <0x00 0x00 0x00 0x00>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0x00 0x04 0x08>; | |
| mcast_queue = <0x100 0x104>; | |
| cfg = <0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| group@1 { | |
| ucast_queue = <0x01 0x05 0x09>; | |
| mcast_queue = <0x101 0x105>; | |
| cfg = <0x00 0x01 0x01 0x01 0x01>; | |
| }; | |
| group@2 { | |
| ucast_queue = <0x02 0x06 0x0a>; | |
| mcast_queue = <0x102 0x106>; | |
| cfg = <0x00 0x02 0x02 0x02 0x02>; | |
| }; | |
| group@3 { | |
| ucast_queue = <0x03 0x07 0x0b>; | |
| mcast_queue = <0x103 0x107>; | |
| cfg = <0x00 0x03 0x03 0x03 0x03>; | |
| }; | |
| }; | |
| }; | |
| port@1 { | |
| port_id = <0x01>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x24>; | |
| cfg = <0x00 0x08 0x00 0x08>; | |
| }; | |
| group@1 { | |
| sp = <0x25>; | |
| cfg = <0x01 0x09 0x01 0x09>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0x90>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x110>; | |
| mcast_loop_pri = <0x04>; | |
| cfg = <0x24 0x00 0x30 0x00 0x30>; | |
| }; | |
| }; | |
| }; | |
| port@2 { | |
| port_id = <0x02>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x28>; | |
| cfg = <0x00 0x0c 0x00 0x0c>; | |
| }; | |
| group@1 { | |
| sp = <0x29>; | |
| cfg = <0x01 0x0d 0x01 0x0d>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0xa0>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x114>; | |
| mcast_loop_pri = <0x04>; | |
| cfg = <0x28 0x00 0x40 0x00 0x40>; | |
| }; | |
| }; | |
| }; | |
| port@3 { | |
| port_id = <0x03>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x2c>; | |
| cfg = <0x00 0x10 0x00 0x10>; | |
| }; | |
| group@1 { | |
| sp = <0x2d>; | |
| cfg = <0x01 0x11 0x01 0x11>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0xb0>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x118>; | |
| mcast_loop_pri = <0x04>; | |
| cfg = <0x2c 0x00 0x50 0x00 0x50>; | |
| }; | |
| }; | |
| }; | |
| port@4 { | |
| port_id = <0x04>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x30>; | |
| cfg = <0x00 0x14 0x00 0x14>; | |
| }; | |
| group@1 { | |
| sp = <0x31>; | |
| cfg = <0x01 0x15 0x01 0x15>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0xc0>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x11c>; | |
| mcast_loop_pri = <0x04>; | |
| cfg = <0x30 0x00 0x60 0x00 0x60>; | |
| }; | |
| }; | |
| }; | |
| port@5 { | |
| port_id = <0x05>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x34>; | |
| cfg = <0x00 0x18 0x00 0x18>; | |
| }; | |
| group@1 { | |
| sp = <0x35>; | |
| cfg = <0x01 0x19 0x01 0x19>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0xd0>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x120>; | |
| mcast_loop_pri = <0x04>; | |
| cfg = <0x34 0x00 0x70 0x00 0x70>; | |
| }; | |
| }; | |
| }; | |
| port@6 { | |
| port_id = <0x06>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x38>; | |
| cfg = <0x00 0x1c 0x00 0x1c>; | |
| }; | |
| group@1 { | |
| sp = <0x39>; | |
| cfg = <0x01 0x1d 0x01 0x1d>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0xe0>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x124>; | |
| mcast_loop_pri = <0x04>; | |
| cfg = <0x38 0x00 0x80 0x00 0x80>; | |
| }; | |
| }; | |
| }; | |
| port@7 { | |
| port_id = <0x07>; | |
| l1scheduler { | |
| group@0 { | |
| sp = <0x3c>; | |
| cfg = <0x00 0x20 0x00 0x20>; | |
| }; | |
| group@1 { | |
| sp = <0x3d>; | |
| cfg = <0x01 0x21 0x01 0x21>; | |
| }; | |
| }; | |
| l0scheduler { | |
| group@0 { | |
| ucast_queue = <0xf0>; | |
| ucast_loop_pri = <0x10>; | |
| mcast_queue = <0x128>; | |
| cfg = <0x3c 0x00 0x90 0x00 0x90>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,port_phyinfo { | |
| port@4 { | |
| port_id = <0x04>; | |
| phy_address = <0x10>; | |
| port_mac_sel = "QGMAC_PORT"; | |
| }; | |
| port@5 { | |
| port_id = <0x05>; | |
| phy_address = <0x14>; | |
| port_mac_sel = "QGMAC_PORT"; | |
| }; | |
| }; | |
| }; | |
| ess-uniphy@7a00000 { | |
| compatible = "qcom,ess-uniphy"; | |
| reg = <0x7a00000 0x30000>; | |
| uniphy_access_mode = "local bus"; | |
| }; | |
| wifi@c000000 { | |
| compatible = "qcom,cnss-qca6018"; | |
| reg = <0xc000000 0x1000000>; | |
| qcom,hw-mode-id = <0x01>; | |
| qcom,tgt-mem-mode = <0x02>; | |
| qcom,bdf-addr = <0x4abc0000 0x4abc0000 0x4abc0000>; | |
| qcom,caldb-addr = <0x4b500000 0x4b500000 0x4b500000>; | |
| interrupts = <0x00 0x140 0x01 0x00 0x13f 0x01 0x00 0x13e 0x01 0x00 0x13d 0x01 0x00 0x13c 0x01 0x00 0x13b 0x01 0x00 0x13a 0x01 0x00 0x137 0x01 0x00 0x136 0x01 0x00 0x19b 0x01 0x00 0x19a 0x01 0x00 0x28 0x01 0x00 0x27 0x01 0x00 0x12e 0x01 0x00 0x12d 0x01 0x00 0x25 0x01 0x00 0x24 0x01 0x00 0x128 0x01 0x00 0x127 0x01 0x00 0x126 0x01 0x00 0x125 0x01 0x00 0x124 0x01 0x00 0x123 0x01 0x00 0x122 0x01 0x00 0x121 0x01 0x00 0x120 0x01 0x00 0xef 0x01 0x00 0xec 0x01 0x00 0xeb 0x01 0x00 0xea 0x01 0x00 0xe9 0x01 0x00 0xe8 0x01 0x00 0xe7 0x01 0x00 0xe6 0x01 0x00 0xe5 0x01 0x00 0xe4 0x01 0x00 0xe0 0x01 0x00 0xdf 0x01 0x00 0xcb 0x01 0x00 0xb7 0x01 0x00 0xb4 0x01 0x00 0xb3 0x01 0x00 0xb2 0x01 0x00 0xb1 0x01 0x00 0xb0 0x01 0x00 0xa3 0x01 0x00 0xa2 0x01 0x00 0xa0 0x01 0x00 0x9f 0x01 0x00 0x9e 0x01 0x00 0x9d 0x01 0x00 0x9c 0x01>; | |
| interrupt-names = "misc-pulse1", "misc-latch", "sw-exception", "watchdog", "ce0", "ce1", "ce2", "ce3", "ce4", "ce5", "ce6", "ce7", "ce8", "ce9", "ce10", "ce11", "host2wbm-desc-feed", "host2reo-re-injection", "host2reo-command", "host2rxdma-monitor-ring3", "host2rxdma-monitor-ring2", "host2rxdma-monitor-ring1", "reo2ost-exception", "wbm2host-rx-release", "reo2host-status", "reo2host-destination-ring4", "reo2host-destination-ring3", "reo2host-destination-ring2", "reo2host-destination-ring1", "rxdma2host-monitor-destination-mac3", "rxdma2host-monitor-destination-mac2", "rxdma2host-monitor-destination-mac1", "ppdu-end-interrupts-mac3", "ppdu-end-interrupts-mac2", "ppdu-end-interrupts-mac1", "rxdma2host-monitor-status-ring-mac3", "rxdma2host-monitor-status-ring-mac2", "rxdma2host-monitor-status-ring-mac1", "host2rxdma-host-buf-ring-mac3", "host2rxdma-host-buf-ring-mac2", "host2rxdma-host-buf-ring-mac1", "rxdma2host-destination-ring-mac3", "rxdma2host-destination-ring-mac2", "rxdma2host-destination-ring-mac1", "host2tcl-input-ring4", "host2tcl-input-ring3", "host2tcl-input-ring2", "host2tcl-input-ring1", "wbm2host-tx-completions-ring3", "wbm2host-tx-completions-ring2", "wbm2host-tx-completions-ring1", "tcl2host-status-ring"; | |
| status = "ok"; | |
| }; | |
| qcom,msm-imem@8600000 { | |
| compatible = "qcom,msm-imem"; | |
| reg = <0x8600000 0x1000>; | |
| ranges = <0x00 0x8600000 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| mem_dump_table@10 { | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| reg = <0x10 0x08>; | |
| }; | |
| }; | |
| qca,scm_restart_reason { | |
| compatible = "qca_ipq6018,scm_restart_reason"; | |
| reg = <0x193d000 0x14>; | |
| }; | |
| slim@a2c0000 { | |
| cell-index = <0x01>; | |
| compatible = "qcom,slim-ngd"; | |
| reg = <0xa2c0000 0x2c000 0xa284000 0x2a000>; | |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; | |
| interrupts = <0x00 0x1f 0x00 0x00 0x20 0x00>; | |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; | |
| qcom,apps-ch-pipes = <0x7c0000>; | |
| qcom,ea-pc = <0x320>; | |
| status = "disabled"; | |
| }; | |
| qca,tzlog { | |
| compatible = "qca,tzlog_ipq6018"; | |
| interrupts = <0x00 0xf4 0x01>; | |
| qca,tzbsp-diag-buf-size = <0x3000>; | |
| qca,hyp-enabled; | |
| hyp-scm-cmd-id = <0x0a>; | |
| }; | |
| qcom,rpm-log@29fc00 { | |
| compatible = "qcom,rpm-log"; | |
| reg = <0x29fc00 0x4000>; | |
| qcom,rpm-addr-phys = <0x200000>; | |
| qcom,offset-version = <0x04>; | |
| qcom,offset-page-buffer-addr = <0x24>; | |
| qcom,offset-log-len = <0x28>; | |
| qcom,offset-log-len-mask = <0x2c>; | |
| qcom,offset-page-indices = <0x38>; | |
| }; | |
| tmc@6048000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6048000 0x1000 0x6064000 0x15000>; | |
| reg-names = "tmc-base", "bam-base"; | |
| interrupts = <0x00 0xa6 0x00>; | |
| interrupt-names = "byte-cntr-irq"; | |
| memory_region = <0x17>; | |
| arm,buffer-size = <0x100000>; | |
| arm,sg-enable; | |
| coresight-ctis = <0x21 0x22>; | |
| coresight-name = "coresight-tmc-etr"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x23>; | |
| linux,phandle = <0x24>; | |
| phandle = <0x24>; | |
| }; | |
| }; | |
| }; | |
| replicator@6046000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b909>; | |
| reg = <0x6046000 0x1000>; | |
| reg-names = "replicator-base"; | |
| coresight-name = "coresight-replicator"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x24>; | |
| linux,phandle = <0x23>; | |
| phandle = <0x23>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x25>; | |
| linux,phandle = <0x26>; | |
| phandle = <0x26>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tmc@6047000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6047000 0x1000>; | |
| reg-names = "tmc-base"; | |
| coresight-ctis = <0x21 0x22>; | |
| coresight-name = "coresight-tmc-etf"; | |
| arm,default-sink; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x26>; | |
| linux,phandle = <0x25>; | |
| phandle = <0x25>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x27>; | |
| linux,phandle = <0x28>; | |
| phandle = <0x28>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6041000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6041000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-in0"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x28>; | |
| linux,phandle = <0x27>; | |
| phandle = <0x27>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x29>; | |
| linux,phandle = <0x2f>; | |
| phandle = <0x2f>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x04>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2a>; | |
| linux,phandle = <0x32>; | |
| phandle = <0x32>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x05>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2b>; | |
| linux,phandle = <0x31>; | |
| phandle = <0x31>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x06>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2c>; | |
| linux,phandle = <0x44>; | |
| phandle = <0x44>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x07>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2d>; | |
| linux,phandle = <0x42>; | |
| phandle = <0x42>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2e>; | |
| linux,phandle = <0x41>; | |
| phandle = <0x41>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6100000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6100000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-center"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x2f>; | |
| linux,phandle = <0x29>; | |
| phandle = <0x29>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x30>; | |
| linux,phandle = <0x43>; | |
| phandle = <0x43>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6130000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6130000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coesight-funnel-mm"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x31>; | |
| linux,phandle = <0x2b>; | |
| phandle = <0x2b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6120000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6120000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-right"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x32>; | |
| linux,phandle = <0x2a>; | |
| phandle = <0x2a>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x33>; | |
| linux,phandle = <0x34>; | |
| phandle = <0x34>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@61a1000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x61a1000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-apss0"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x34>; | |
| linux,phandle = <0x33>; | |
| phandle = <0x33>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x35>; | |
| linux,phandle = <0x3a>; | |
| phandle = <0x3a>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x01>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x36>; | |
| linux,phandle = <0x3c>; | |
| phandle = <0x3c>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x02>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x37>; | |
| linux,phandle = <0x3e>; | |
| phandle = <0x3e>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x03>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x38>; | |
| linux,phandle = <0x40>; | |
| phandle = <0x40>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@619c000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x619c000 0x1000>; | |
| coresight-name = "coresight-etm0"; | |
| cpu = <0x39>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x3a>; | |
| linux,phandle = <0x35>; | |
| phandle = <0x35>; | |
| }; | |
| }; | |
| }; | |
| etm@619d000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x619d000 0x1000>; | |
| coresight-name = "coresight-etm1"; | |
| cpu = <0x3b>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x3c>; | |
| linux,phandle = <0x36>; | |
| phandle = <0x36>; | |
| }; | |
| }; | |
| }; | |
| etm@619e000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x619e000 0x1000>; | |
| coresight-name = "coresight-etm2"; | |
| cpu = <0x3d>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x3e>; | |
| linux,phandle = <0x37>; | |
| phandle = <0x37>; | |
| }; | |
| }; | |
| }; | |
| etm@619f000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x619f000 0x1000>; | |
| coresight-name = "coresight-etm3"; | |
| cpu = <0x3f>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x40>; | |
| linux,phandle = <0x38>; | |
| phandle = <0x38>; | |
| }; | |
| }; | |
| }; | |
| rpm_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-rpm-etm0"; | |
| qcom,inst-id = <0x04>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x41>; | |
| linux,phandle = <0x2e>; | |
| phandle = <0x2e>; | |
| }; | |
| }; | |
| }; | |
| stm@6002000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b962>; | |
| reg = <0x6002000 0x1000 0x9280000 0x180000>; | |
| reg-names = "stm-base", "stm-data-base"; | |
| coresight-name = "coresight-stm"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x42>; | |
| linux,phandle = <0x2d>; | |
| phandle = <0x2d>; | |
| }; | |
| }; | |
| }; | |
| cti@6010000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6010000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti0"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x21>; | |
| phandle = <0x21>; | |
| }; | |
| cti@6011000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6011000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti1"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6012000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6012000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti2"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6013000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6013000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti3"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6014000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6014000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti4"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6015000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6015000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti5"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6016000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6016000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti6"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6017000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6017000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti7"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6018000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6018000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti8"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x22>; | |
| phandle = <0x22>; | |
| }; | |
| cti@6019000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6019000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti9"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@601a000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601a000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti10"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@601b000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601b000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti11"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@601c000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601c000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti12"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@601d000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601d000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti13"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@601e000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601e000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti14"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@601f000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601f000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti15"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6198000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6198000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu0"; | |
| cpu = <0x39>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@6199000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6199000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu1"; | |
| cpu = <0x3b>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@619a000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x619a000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu2"; | |
| cpu = <0x3d>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@619b000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x619b000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu3"; | |
| cpu = <0x3f>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| cti@610c000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x610c000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-rpm-cpu0"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| csr@6001000 { | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x6001000 0x1000>; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| qcom,blk-size = <0x01>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| dbgui@6108000 { | |
| compatible = "qcom,coresight-dbgui"; | |
| reg = <0x6108000 0x1000>; | |
| reg-names = "dbgui-base"; | |
| coresight-name = "coresight-dbgui"; | |
| qcom,dbgui-addr-offset = <0x30>; | |
| qcom,dbgui-data-offset = <0x130>; | |
| qcom,dbgui-size = <0x40>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x43>; | |
| linux,phandle = <0x30>; | |
| phandle = <0x30>; | |
| }; | |
| }; | |
| }; | |
| tpda@6004000 { | |
| compatible = "qcom,coresight-tpda"; | |
| reg = <0x6004000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda"; | |
| qcom,tpda-atid = <0x40>; | |
| qcom,cmb-elem-size = <0x00 0x20>; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x44>; | |
| linux,phandle = <0x2c>; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x00>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x45>; | |
| linux,phandle = <0x46>; | |
| phandle = <0x46>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@6110000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x6110000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-dcc"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x46>; | |
| linux,phandle = <0x45>; | |
| phandle = <0x45>; | |
| }; | |
| }; | |
| }; | |
| hwevent@6101000 { | |
| compatible = "qcom,coresight-hwevent"; | |
| reg = <0x6101000 0x148 0x6101fb0 0x04 0x6121000 0x148 0x6121fb0 0x04 0x6131000 0x148 0x6131fb0 0x04 0x6130fb0 0x04 0x6130000 0x148 0x6041fb0 0x04 0x6041000 0x148>; | |
| reg-names = "center-wrapper-mux", "center-wrapper-lockaccess", "right-wrapper-mux", "right-wrapper-lockaccess", "mm-wrapper-mux", "mm-wrapper-lockaccess", "mm-fun-lockaccess", "mm-fun", "in-fun-lockaccess", "in-fun"; | |
| coresight-name = "coresight-hwevent"; | |
| clocks = <0x02 0xbf 0x02 0xbe>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| }; | |
| apm@b111000 { | |
| compatible = "qcom,ipq807x-apm"; | |
| reg = <0xb111000 0x1000>; | |
| reg-names = "pm-apcc-glb"; | |
| qcom,apm-post-halt-delay = <0x02>; | |
| qcom,apm-halt-clk-delay = <0x11>; | |
| qcom,apm-resume-clk-delay = <0x10>; | |
| qcom,apm-sel-switch-delay = <0x01>; | |
| linux,phandle = <0x47>; | |
| phandle = <0x47>; | |
| }; | |
| cpr4-ctrl@b018000 { | |
| compatible = "qcom,cpr4-ipq6018-apss-regulator"; | |
| reg = <0xb018000 0x4000 0xa4000 0x1000 0x193d008 0x04>; | |
| reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg"; | |
| interrupts = <0x00 0x0f 0x01>; | |
| interrupt-names = "cpr"; | |
| qcom,cpr-ctrl-name = "apc"; | |
| qcom,cpr-sensor-time = <0x3e8>; | |
| qcom,cpr-loop-time = <0x4c4b40>; | |
| qcom,cpr-idle-cycles = <0x0f>; | |
| qcom,cpr-step-quot-init-min = <0x00>; | |
| qcom,cpr-step-quot-init-max = <0x0f>; | |
| qcom,cpr-count-mode = <0x00>; | |
| qcom,cpr-count-repeat = <0x01>; | |
| qcom,cpr-down-error-step-limit = <0x01>; | |
| qcom,cpr-up-error-step-limit = <0x01>; | |
| qcom,apm-ctrl = <0x47>; | |
| qcom,apm-threshold-voltage = <0xcf850>; | |
| vdd-supply = <0x48>; | |
| qcom,voltage-step = <0x30d4>; | |
| thread@0 { | |
| qcom,cpr-thread-id = <0x00>; | |
| qcom,cpr-consecutive-up = <0x02>; | |
| qcom,cpr-consecutive-down = <0x02>; | |
| qcom,cpr-up-threshold = <0x02>; | |
| qcom,cpr-down-threshold = <0x02>; | |
| regulator { | |
| regulator-name = "apc_corner"; | |
| regulator-min-microvolt = <0x01>; | |
| regulator-max-microvolt = <0x06>; | |
| qcom,cpr-fuse-corners = <0x04>; | |
| qcom,cpr-fuse-combos = <0x08>; | |
| qcom,cpr-corners = <0x06>; | |
| qcom,cpr-speed-bins = <0x01>; | |
| qcom,cpr-speed-bin-corners = <0x06>; | |
| qcom,cpr-corner-fmax-map = <0x01 0x03 0x05 0x06>; | |
| qcom,allow-voltage-interpolation; | |
| qcom,allow-quotient-interpolation; | |
| qcom,cpr-voltage-ceiling = <0xb1008 0xc042c 0xd2924 0xe1d48 0xf116c 0x103664>; | |
| qcom,cpr-voltage-floor = <0x8f6ec 0x9eb10 0xadf34 0xb71b0 0xc042c 0xcf850>; | |
| qcom,corner-frequencies = <0x337f9800 0x3ef14800 0x4ead9a00 0x55d4a800 0x5fd82200 0x6b49d200>; | |
| qcom,cpr-ro-sel = <0x00 0x00 0x00 0x00 0x07 0x07 0x07 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,cpr-open-loop-voltage-fuse-adjustment = <0x00 0x00 0x00 0x00 0x00 0x00 0x3a98 0x00 0x00 0x00 0x3a98 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = <0x00 0x00 0x00 0x00 0x32c8 0x00 0x32c8 0x32c8 0x32c8 0x00 0x32c8 0x32c8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| qcom,cpr-ro-scaling-factor = <0x7d0 0x6ea 0x76c 0x686 0x78a 0x6ea 0x776 0x708 0x74e 0x6c2 0x7d0 0x730 0x708 0x7ee 0x6a4 0x762 0x7d0 0x6ea 0x76c 0x686 0x78a 0x6ea 0x776 0x708 0x74e 0x6c2 0x7d0 0x730 0x708 0x7ee 0x6a4 0x762 0x7d0 0x6ea 0x76c 0x686 0x78a 0x6ea 0x776 0x708 0x74e 0x6c2 0x7d0 0x730 0x708 0x7ee 0x6a4 0x762 0x7d0 0x6ea 0x76c 0x686 0x78a 0x6ea 0x776 0x708 0x74e 0x6c2 0x7d0 0x730 0x708 0x7ee 0x6a4 0x762>; | |
| linux,phandle = <0x4e>; | |
| phandle = <0x4e>; | |
| }; | |
| }; | |
| }; | |
| thermal-sensor@4a8000 { | |
| compatible = "qcom,ipq6018-tsens"; | |
| reg = <0x4a8000 0x2000>; | |
| interrupts = <0x00 0xb8 0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| tsens-up-low-int-clr-deassert-quirk; | |
| status = "ok"; | |
| linux,phandle = <0x52>; | |
| phandle = <0x52>; | |
| }; | |
| dp1 { | |
| device_type = "network"; | |
| compatible = "qcom,nss-dp"; | |
| qcom,id = <0x04>; | |
| reg = <0x3a001600 0x200>; | |
| qcom,mactype = <0x00>; | |
| local-mac-address = [00 00 00 00 00 00]; | |
| qcom,link-poll = <0x01>; | |
| qcom,phy-mdio-addr = <0x10>; | |
| phy-mode = "sgmii"; | |
| }; | |
| dp2 { | |
| device_type = "network"; | |
| compatible = "qcom,nss-dp"; | |
| qcom,id = <0x05>; | |
| reg = <0x3a001800 0x200>; | |
| qcom,mactype = <0x00>; | |
| local-mac-address = [00 00 00 00 00 00]; | |
| qcom,link-poll = <0x01>; | |
| qcom,phy-mdio-addr = <0x14>; | |
| phy-mode = "sgmii"; | |
| }; | |
| nss-macsec0 { | |
| compatible = "qcom,nss-macsec"; | |
| phy_addr = <0x10>; | |
| phy_access_mode = <0x00>; | |
| mdiobus = <0x49>; | |
| }; | |
| nss-macsec1 { | |
| compatible = "qcom,nss-macsec"; | |
| phy_addr = <0x14>; | |
| phy_access_mode = <0x00>; | |
| mdiobus = <0x49>; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a7-pmu"; | |
| interrupts = <0x01 0x07 0xf04>; | |
| }; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| status = "ok"; | |
| }; | |
| cpus { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x00>; | |
| enable-method = "psci"; | |
| qcom,acc = <0x4a>; | |
| next-level-cache = <0x4b>; | |
| clocks = <0x4c 0x03>; | |
| clock-names = "cpu"; | |
| operating-points-v2 = <0x4d>; | |
| voltage-tolerance = <0x01>; | |
| cpu0-supply = <0x4e>; | |
| enable-cpu-regulator; | |
| linux,phandle = <0x39>; | |
| phandle = <0x39>; | |
| l2-cache { | |
| compatible = "cache"; | |
| cache-level = <0x02>; | |
| linux,phandle = <0x4b>; | |
| phandle = <0x4b>; | |
| }; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| enable-method = "psci"; | |
| qcom,acc = <0x4f>; | |
| reg = <0x01>; | |
| next-level-cache = <0x4b>; | |
| clocks = <0x4c 0x03>; | |
| clock-names = "cpu"; | |
| operating-points-v2 = <0x4d>; | |
| voltage-tolerance = <0x01>; | |
| cpu-supply = <0x4e>; | |
| linux,phandle = <0x3b>; | |
| phandle = <0x3b>; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| enable-method = "psci"; | |
| qcom,acc = <0x50>; | |
| reg = <0x02>; | |
| next-level-cache = <0x4b>; | |
| clocks = <0x4c 0x03>; | |
| clock-names = "cpu"; | |
| operating-points-v2 = <0x4d>; | |
| voltage-tolerance = <0x01>; | |
| cpu-supply = <0x4e>; | |
| linux,phandle = <0x3d>; | |
| phandle = <0x3d>; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| enable-method = "psci"; | |
| qcom,acc = <0x51>; | |
| reg = <0x03>; | |
| next-level-cache = <0x4b>; | |
| clocks = <0x4c 0x03>; | |
| clock-names = "cpu"; | |
| operating-points-v2 = <0x4d>; | |
| voltage-tolerance = <0x01>; | |
| cpu-supply = <0x4e>; | |
| linux,phandle = <0x3f>; | |
| phandle = <0x3f>; | |
| }; | |
| opp_table0 { | |
| compatible = "operating-points-v2"; | |
| opp-shared; | |
| linux,phandle = <0x4d>; | |
| phandle = <0x4d>; | |
| opp00 { | |
| opp-hz = <0x00 0x00>; | |
| opp-microvolt = <0x00>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| opp01 { | |
| opp-hz = <0x00 0x337f9800>; | |
| opp-microvolt = <0x01>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| opp02 { | |
| opp-hz = <0x00 0x3ef14800>; | |
| opp-microvolt = <0x02>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| opp03 { | |
| opp-hz = <0x00 0x4ead9a00>; | |
| opp-microvolt = <0x03>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| opp04 { | |
| opp-hz = <0x00 0x55d4a800>; | |
| opp-microvolt = <0x04>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| opp05 { | |
| opp-hz = <0x00 0x5fd82200>; | |
| opp-microvolt = <0x05>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| opp06 { | |
| opp-hz = <0x00 0x6b49d200>; | |
| opp-microvolt = <0x06>; | |
| clock-latency-ns = <0x30d40>; | |
| }; | |
| }; | |
| }; | |
| qseecom { | |
| compatible = "ipq6018-qseecom"; | |
| status = "disabled"; | |
| }; | |
| firmware { | |
| scm { | |
| compatible = "qcom,scm-ipq6018"; | |
| }; | |
| qfprom { | |
| compatible = "qcom,qfprom-sec"; | |
| img-addr = <0x4a100000>; | |
| img-size = <0x500000>; | |
| scm-cmd-id = <0x1f>; | |
| }; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <0x01 0x07 0xf04>; | |
| }; | |
| clocks { | |
| sleep_clk { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x7d00>; | |
| #clock-cells = <0x00>; | |
| linux,phandle = <0x1f>; | |
| phandle = <0x1f>; | |
| }; | |
| xo { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x16e3600>; | |
| #clock-cells = <0x00>; | |
| }; | |
| bias_pll_cc_clk { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x11e1a300>; | |
| #clock-cells = <0x00>; | |
| }; | |
| bias_pll_nss_noc_clk { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x18d34920>; | |
| #clock-cells = <0x00>; | |
| }; | |
| usb3phy_0_cc_pipe_clk { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x7735940>; | |
| #clock-cells = <0x00>; | |
| }; | |
| }; | |
| ion_dummy { | |
| compatible = "ipq60xx-ion-dummy"; | |
| status = "disabled"; | |
| }; | |
| thermal-zones { | |
| tsens_tz_sensor4 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x04>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| tsens_tz_sensor5 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x05>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| tsens_tz_sensor7 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x07>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| tsens_tz_sensor8 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x08>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| tsens_tz_sensor13 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x0d>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| tsens_tz_sensor14 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x0e>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| tsens_tz_sensor15 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x52 0x0f>; | |
| trips { | |
| cpu-critical-hi { | |
| temperature = <0x7d>; | |
| hysteresis = <0x02>; | |
| type = "critical_high"; | |
| }; | |
| cpu-config-hi { | |
| temperature = <0x69>; | |
| hysteresis = <0x02>; | |
| type = "configurable_hi"; | |
| }; | |
| cpu-config-lo { | |
| temperature = <0x5f>; | |
| hysteresis = <0x02>; | |
| type = "configurable_lo"; | |
| }; | |
| cpu-critical-low { | |
| temperature = <0x00>; | |
| hysteresis = <0x02>; | |
| type = "critical_low"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| aliases { | |
| serial0 = "/soc/serial@78b1000"; | |
| serial1 = "/soc/serial@78b3000"; | |
| sdhc1 = "/soc/sdhci@7804000"; | |
| ethernet0 = "/soc/dp1"; | |
| ethernet1 = "/soc/dp2"; | |
| }; | |
| chosen { | |
| bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; | |
| bootargs-append = " swiotlb=1 coherent_pool=2M"; | |
| }; | |
| }; |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment