bug.ll

; Function Attrs: noinline norecurse nounwind readnone
define i32 @u32_ge_u32_or(i32, i32) unnamed_addr #1 {
start:
  %2 = icmp ult i32 %0, %1
  %3 = or i32 %1, %0
  %_0.0 = select i1 %2, i32 0, i32 %3
  ret i32 %_0.0
}

attributes #1 = { noinline norecurse nounwind readnone }

log

# After Machine Loop Invariant Code Motion:
# Machine code for function u32_ge_u32_or: IsSSA, TracksLiveness
Function Live Ins: %R12 in %vreg0, %R13 in %vreg1, %R14 in %vreg2, %R15 in %vreg3

BB#0: derived from LLVM BB %start
    Live Ins: %R12 %R13 %R14 %R15
	%vreg3<def> = COPY %R15; GR16:%vreg3
	%vreg2<def> = COPY %R14; GR16:%vreg2
	%vreg1<def> = COPY %R13; GR16:%vreg1
	%vreg0<def> = COPY %R12; GR16:%vreg0
	CMP16rr %vreg1, %vreg3, %SR<imp-def>; GR16:%vreg1,%vreg3
	%vreg4<def> = COPY %SR; GR16:%vreg4
	%vreg5<def> = MOV16ri 1; GR16:%vreg5
	%vreg6<def,tied1> = BIC16rr %vreg5<tied0>, %vreg4, %SR<imp-def,dead>; GR16:%vreg6,%vreg5,%vreg4
	CMP16rr %vreg0, %vreg2, %SR<imp-def>; GR16:%vreg0,%vreg2
	%vreg7<def> = COPY %SR; GR16:%vreg7
	%vreg8<def,tied1> = BIC16rr %vreg5<tied0>, %vreg7, %SR<imp-def,dead>; GR16:%vreg8,%vreg5,%vreg7
	CMP16rr %vreg1, %vreg3, %SR<imp-def,dead>; GR16:%vreg1,%vreg3
	JCC <BB#2>, 0, %SR<imp-use>
    Successors according to CFG: BB#1(?%) BB#2(?%)

BB#1: derived from LLVM BB %start
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2(?%)

BB#2: derived from LLVM BB %start
    Predecessors according to CFG: BB#0 BB#1
	%vreg9<def> = PHI %vreg6, <BB#1>, %vreg8, <BB#0>; GR16:%vreg9,%vreg6,%vreg8
	%vreg10<def,tied1> = OR16rr %vreg3<tied0>, %vreg1, %SR<imp-def,dead>; GR16:%vreg10,%vreg3,%vreg1
	%vreg11<def,tied1> = OR16rr %vreg2<tied0>, %vreg0, %SR<imp-def,dead>; GR16:%vreg11,%vreg2,%vreg0
	%vreg12<def> = MOV16ri 0; GR16:%vreg12
	CMP16ri %vreg9, 0, %SR<imp-def,dead>; GR16:%vreg9
	JCC <BB#4>, 1, %SR<imp-use>
    Successors according to CFG: BB#3(?%) BB#4(?%)

BB#3: derived from LLVM BB %start
    Predecessors according to CFG: BB#2
    Successors according to CFG: BB#4(?%)

BB#4: derived from LLVM BB %start
    Predecessors according to CFG: BB#2 BB#3
	%vreg13<def> = PHI %vreg11, <BB#3>, %vreg12, <BB#2>; GR16:%vreg13,%vreg11,%vreg12
	CMP16ri %vreg9, 0, %SR<imp-def,dead>; GR16:%vreg9
	JCC <BB#6>, 1, %SR<imp-use>
    Successors according to CFG: BB#5(?%) BB#6(?%)

BB#5: derived from LLVM BB %start
    Predecessors according to CFG: BB#4
    Successors according to CFG: BB#6(?%)

BB#6: derived from LLVM BB %start
    Predecessors according to CFG: BB#4 BB#5
	%vreg14<def> = PHI %vreg10, <BB#5>, %vreg12, <BB#4>; GR16:%vreg14,%vreg10,%vreg12
	%R12<def> = COPY %vreg13; GR16:%vreg13
	%R13<def> = COPY %vreg14; GR16:%vreg14
	RET %R12<imp-use>, %R13<imp-use>

# End machine code for function u32_ge_u32_or.

# After Machine Common Subexpression Elimination:
# Machine code for function u32_ge_u32_or: IsSSA, TracksLiveness
Function Live Ins: %R12 in %vreg0, %R13 in %vreg1, %R14 in %vreg2, %R15 in %vreg3

BB#0: derived from LLVM BB %start
    Live Ins: %R12 %R13 %R14 %R15
	%vreg3<def> = COPY %R15; GR16:%vreg3
	%vreg2<def> = COPY %R14; GR16:%vreg2
	%vreg1<def> = COPY %R13; GR16:%vreg1
	%vreg0<def> = COPY %R12; GR16:%vreg0
	CMP16rr %vreg1, %vreg3, %SR<imp-def>; GR16:%vreg1,%vreg3
	%vreg4<def> = COPY %SR; GR16:%vreg4
	%vreg5<def> = MOV16ri 1; GR16:%vreg5
	%vreg6<def,tied1> = BIC16rr %vreg5<tied0>, %vreg4, %SR<imp-def,dead>; GR16:%vreg6,%vreg5,%vreg4
	CMP16rr %vreg0, %vreg2, %SR<imp-def>; GR16:%vreg0,%vreg2
	%vreg7<def> = COPY %SR; GR16:%vreg7
	%vreg8<def,tied1> = BIC16rr %vreg5<tied0>, %vreg7, %SR<imp-def,dead>; GR16:%vreg8,%vreg5,%vreg7
	JCC <BB#2>, 0, %SR<imp-use>
    Successors according to CFG: BB#1(?%) BB#2(?%)

BB#1: derived from LLVM BB %start
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2(?%)

BB#2: derived from LLVM BB %start
    Predecessors according to CFG: BB#0 BB#1
	%vreg9<def> = PHI %vreg6, <BB#1>, %vreg8, <BB#0>; GR16:%vreg9,%vreg6,%vreg8
	%vreg10<def,tied1> = OR16rr %vreg3<tied0>, %vreg1, %SR<imp-def,dead>; GR16:%vreg10,%vreg3,%vreg1
	%vreg11<def,tied1> = OR16rr %vreg2<tied0>, %vreg0, %SR<imp-def,dead>; GR16:%vreg11,%vreg2,%vreg0
	%vreg12<def> = MOV16ri 0; GR16:%vreg12
	CMP16ri %vreg9, 0, %SR<imp-def,dead>; GR16:%vreg9
	JCC <BB#4>, 1, %SR<imp-use>
    Successors according to CFG: BB#3(?%) BB#4(?%)

BB#3: derived from LLVM BB %start
    Predecessors according to CFG: BB#2
    Successors according to CFG: BB#4(?%)

BB#4: derived from LLVM BB %start
    Predecessors according to CFG: BB#2 BB#3
	%vreg13<def> = PHI %vreg11, <BB#3>, %vreg12, <BB#2>; GR16:%vreg13,%vreg11,%vreg12
	JCC <BB#6>, 1, %SR<imp-use>
    Successors according to CFG: BB#5(?%) BB#6(?%)

BB#5: derived from LLVM BB %start
    Predecessors according to CFG: BB#4
    Successors according to CFG: BB#6(?%)

BB#6: derived from LLVM BB %start
    Predecessors according to CFG: BB#4 BB#5
	%vreg14<def> = PHI %vreg10, <BB#5>, %vreg12, <BB#4>; GR16:%vreg14,%vreg10,%vreg12
	%R12<def> = COPY %vreg13; GR16:%vreg13
	%R13<def> = COPY %vreg14; GR16:%vreg14
	RET %R12<imp-use>, %R13<imp-use>

# End machine code for function u32_ge_u32_or.