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[pklaus@hades ~]$ sudo lspci -vv |
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00:00.0 Host bridge: Intel Corporation 8th Gen Core 4-core Processor Host Bridge/DRAM Registers [Coffee Lake H] (rev 07) |
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DeviceName: SATA |
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Subsystem: Intel Corporation 8th Gen Core 4-core Processor Host Bridge/DRAM Registers [Coffee Lake H] |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- |
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Latency: 0 |
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Capabilities: [e0] Vendor Specific Information: Len=10 <?> |
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Kernel driver in use: skl_uncore |
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00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x16) (rev 07) (prog-if 00 [Normal decode]) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 26 |
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Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 |
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I/O behind bridge: None |
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Memory behind bridge: 81800000-81cfffff [size=5M] |
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Prefetchable memory behind bridge: None |
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Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- |
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BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
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PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
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Capabilities: [88] Subsystem: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x16) |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- |
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Address: fee00278 Data: 0000 |
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Capabilities: [a0] Express (v2) Root Port (Slot+), MSI 00 |
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DevCap: MaxPayload 256 bytes, PhantFunc 0 |
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ExtTag- RBE+ |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
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MaxPayload 256 bytes, MaxReadReq 128 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- |
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LnkCap: Port #2, Speed 5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <256ns, L1 <8us |
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ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 5GT/s (ok), Width x4 (downgraded) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt+ |
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SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
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Slot #1, PowerLimit 75.000W; Interlock- NoCompl+ |
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SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
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Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
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SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
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Changed: MRL- PresDet- LinkState- |
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RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- |
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RootCap: CRSVisible- |
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RootSta: PME ReqID 0000, PMEStatus- PMEPending- |
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DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via WAKE# ARIFwd- |
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AtomicOpsCap: Routing- 32bit+ 64bit+ 128bitCAS+ |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Via WAKE# ARIFwd- |
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AtomicOpsCtl: ReqEn- EgressBlck- |
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LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [100 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [140 v1] Root Complex Link |
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Desc: PortNumber=02 ComponentID=01 EltType=Config |
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Link0: Desc: TargetPort=00 TargetComponent=01 AssocRCRB- LinkType=MemMapped LinkValid+ |
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Addr: 00000000fed19000 |
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Capabilities: [d94 v1] Secondary PCI Express <?> |
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Kernel driver in use: pcieport |
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00:01.1 PCI bridge: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x8) (rev 07) (prog-if 00 [Normal decode]) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 27 |
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Bus: primary=00, secondary=05, subordinate=7a, sec-latency=0 |
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I/O behind bridge: 00004000-00007fff [size=16K] |
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Memory behind bridge: 81f00000-900fffff [size=226M] |
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Prefetchable memory behind bridge: 00000000b1300000-00000000bf2fffff [size=224M] |
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Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- |
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BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
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PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
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Capabilities: [88] Subsystem: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x8) |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- |
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Address: fee00298 Data: 0000 |
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Capabilities: [a0] Express (v2) Root Port (Slot+), MSI 00 |
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DevCap: MaxPayload 256 bytes, PhantFunc 0 |
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ExtTag- RBE+ |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
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MaxPayload 128 bytes, MaxReadReq 128 bytes |
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DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- |
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LnkCap: Port #3, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <256ns, L1 <8us |
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ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt+ |
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SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
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Slot #2, PowerLimit 75.000W; Interlock- NoCompl+ |
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SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
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Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
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SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
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Changed: MRL- PresDet+ LinkState- |
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RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- |
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RootCap: CRSVisible- |
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RootSta: PME ReqID 0000, PMEStatus- PMEPending- |
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DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via WAKE# ARIFwd- |
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AtomicOpsCap: Routing- 32bit+ 64bit+ 128bitCAS+ |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Via WAKE# ARIFwd- |
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AtomicOpsCtl: ReqEn- EgressBlck- |
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LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ |
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EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- |
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Capabilities: [100 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [140 v1] Root Complex Link |
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Desc: PortNumber=03 ComponentID=01 EltType=Config |
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Link0: Desc: TargetPort=00 TargetComponent=01 AssocRCRB- LinkType=MemMapped LinkValid+ |
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Addr: 00000000fed19000 |
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Capabilities: [d94 v1] Secondary PCI Express <?> |
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Kernel driver in use: pcieport |
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00:01.2 PCI bridge: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x4) (rev 07) (prog-if 00 [Normal decode]) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 28 |
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Bus: primary=00, secondary=7b, subordinate=f0, sec-latency=0 |
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I/O behind bridge: 00008000-0000bfff [size=16K] |
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Memory behind bridge: 90100000-9e2fffff [size=226M] |
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Prefetchable memory behind bridge: 00000000bf300000-00000000cd2fffff [size=224M] |
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Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- |
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BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
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PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
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Capabilities: [88] Subsystem: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x4) |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- |
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Address: fee002b8 Data: 0000 |
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Capabilities: [a0] Express (v2) Root Port (Slot+), MSI 00 |
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DevCap: MaxPayload 256 bytes, PhantFunc 0 |
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ExtTag- RBE+ |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
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MaxPayload 128 bytes, MaxReadReq 128 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- |
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LnkCap: Port #4, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <256ns, L1 <8us |
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ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt+ |
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SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
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Slot #3, PowerLimit 75.000W; Interlock- NoCompl+ |
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SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
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Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
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SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
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Changed: MRL- PresDet+ LinkState- |
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RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- |
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RootCap: CRSVisible- |
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RootSta: PME ReqID 7e00, PMEStatus+ PMEPending- |
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DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via WAKE# ARIFwd- |
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AtomicOpsCap: Routing- 32bit+ 64bit+ 128bitCAS+ |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Via WAKE# ARIFwd- |
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AtomicOpsCtl: ReqEn- EgressBlck- |
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LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ |
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EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- |
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Capabilities: [100 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [140 v1] Root Complex Link |
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Desc: PortNumber=04 ComponentID=01 EltType=Config |
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Link0: Desc: TargetPort=00 TargetComponent=01 AssocRCRB- LinkType=MemMapped LinkValid+ |
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Addr: 00000000fed19000 |
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Capabilities: [d94 v1] Secondary PCI Express <?> |
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Kernel driver in use: pcieport |
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00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 630 (Mobile) (prog-if 00 [VGA controller]) |
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Subsystem: Apple Inc. UHD Graphics 630 (Mobile) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 67 |
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Region 0: Memory at 80000000 (64-bit, non-prefetchable) [size=16M] |
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Region 2: Memory at a0000000 (64-bit, prefetchable) [size=256M] |
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Region 4: I/O ports at 3000 [size=64] |
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[virtual] Expansion ROM at 000c0000 [disabled] [size=128K] |
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Capabilities: [40] Vendor Specific Information: Len=0c <?> |
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Capabilities: [70] Express (v2) Root Complex Integrated Endpoint, MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0 |
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ExtTag- RBE+ |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
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MaxPayload 128 bytes, MaxReadReq 128 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- |
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DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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Capabilities: [ac] MSI: Enable+ Count=1/1 Maskable- 64bit- |
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Address: fee00018 Data: 0000 |
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Capabilities: [d0] Power Management version 2 |
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Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) |
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [100 v1] Process Address Space ID (PASID) |
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PASIDCap: Exec- Priv-, Max PASID Width: 14 |
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PASIDCtl: Enable- Exec- Priv- |
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Capabilities: [200 v1] Address Translation Service (ATS) |
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ATSCap: Invalidate Queue Depth: 00 |
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ATSCtl: Enable-, Smallest Translation Unit: 00 |
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Capabilities: [300 v1] Page Request Interface (PRI) |
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PRICtl: Enable- Reset- |
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PRISta: RF- UPRGI- Stopped+ |
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Page Request Capacity: 00008000, Page Request Allocation: 00000000 |
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Kernel driver in use: i915 |
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Kernel modules: i915 |
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00:12.0 Signal processing controller: Intel Corporation Cannon Lake PCH Thermal Controller (rev 10) |
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Subsystem: Intel Corporation Cannon Lake PCH Thermal Controller |
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Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Interrupt: pin A routed to IRQ -2147483648 |
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Region 0: Memory at 81e16000 (64-bit, non-prefetchable) [size=4K] |
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Capabilities: [50] Power Management version 3 |
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Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- |
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Address: 00000000 Data: 0000 |
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Kernel driver in use: intel_pch_thermal |
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Kernel modules: intel_pch_thermal |
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00:14.0 USB controller: Intel Corporation Cannon Lake PCH USB 3.1 xHCI Host Controller (rev 10) (prog-if 30 [XHCI]) |
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Subsystem: Intel Corporation Cannon Lake PCH USB 3.1 xHCI Host Controller |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0 |
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Interrupt: pin A routed to IRQ 42 |
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Region 0: Memory at 81e00000 (64-bit, non-prefetchable) [size=64K] |
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Capabilities: [70] Power Management version 2 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [80] MSI: Enable+ Count=1/8 Maskable- 64bit+ |
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Address: 00000000fee00478 Data: 0000 |
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Capabilities: [90] Vendor Specific Information: Len=14 <?> |
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Kernel driver in use: xhci_hcd |
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Kernel modules: xhci_pci |
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00:14.2 RAM memory: Intel Corporation Cannon Lake PCH Shared SRAM (rev 10) |
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Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Region 0: Memory at 81e14000 (64-bit, non-prefetchable) [disabled] [size=8K] |
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Region 2: Memory at 81e17000 (64-bit, non-prefetchable) [disabled] [size=4K] |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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00:16.0 Communication controller: Intel Corporation Cannon Lake PCH HECI Controller (rev 10) |
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Subsystem: Intel Corporation Cannon Lake PCH HECI Controller |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0 |
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Interrupt: pin A routed to IRQ 45 |
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Region 0: Memory at 81e18000 (64-bit, non-prefetchable) [size=4K] |
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Capabilities: [50] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [8c] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
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Address: 00000000fee004d8 Data: 0000 |
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Capabilities: [a4] Vendor Specific Information: Len=14 <?> |
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Kernel driver in use: mei_me |
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Kernel modules: mei_me |
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00:1b.0 PCI bridge: Intel Corporation Cannon Lake PCH PCI Express Root Port #17 (rev f0) (prog-if 00 [Normal decode]) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 29 |
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Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 |
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I/O behind bridge: None |
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Memory behind bridge: None |
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Prefetchable memory behind bridge: 00000000b0000000-00000000b12fffff [size=19M] |
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Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 256 bytes, PhantFunc 0 |
|
ExtTag- RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
|
MaxPayload 256 bytes, MaxReadReq 128 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #17, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us |
|
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
|
Slot #16, PowerLimit 25.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
|
Changed: MRL- PresDet- LinkState- |
|
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- |
|
RootCap: CRSVisible- |
|
RootSta: PME ReqID 0000, PMEStatus- PMEPending- |
|
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ |
|
AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- |
|
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: ReqEn- EgressBlck- |
|
LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+ |
|
EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- |
|
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- |
|
Address: fee002d8 Data: 0000 |
|
Capabilities: [90] Subsystem: Intel Corporation Cannon Lake PCH PCI Express Root Port |
|
Capabilities: [a0] Power Management version 3 |
|
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [100 v0] Null |
|
Capabilities: [140 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Capabilities: [150 v1] Precision Time Measurement |
|
PTMCap: Requester:- Responder:+ Root:+ |
|
PTMClockGranularity: 4ns |
|
PTMControl: Enabled:+ RootSelected:+ |
|
PTMEffectiveGranularity: Unknown |
|
Capabilities: [200 v1] L1 PM Substates |
|
L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ L1_PM_Substates+ |
|
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ |
|
|
|
L1SubCtl2: |
|
Capabilities: [220 v1] Secondary PCI Express <?> |
|
Capabilities: [250 v1] Downstream Port Containment |
|
DpcCap: INT Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+ |
|
DpcCtl: Trigger:0 Cmpl- INT- ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr- |
|
DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:1f |
|
Source: 0000 |
|
Kernel driver in use: pcieport |
|
|
|
00:1c.0 PCI bridge: Intel Corporation Cannon Lake PCH PCI Express Root Port #1 (rev f0) (prog-if 00 [Normal decode]) |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0, Cache Line Size: 256 bytes |
|
Interrupt: pin A routed to IRQ 30 |
|
Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 |
|
I/O behind bridge: None |
|
Memory behind bridge: 81000000-814fffff [size=5M] |
|
Prefetchable memory behind bridge: None |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 256 bytes, PhantFunc 0 |
|
ExtTag- RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
|
MaxPayload 256 bytes, MaxReadReq 128 bytes |
|
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us |
|
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) |
|
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
|
Slot #0, PowerLimit 10.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
|
Changed: MRL- PresDet+ LinkState+ |
|
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- |
|
RootCap: CRSVisible- |
|
RootSta: PME ReqID 0000, PMEStatus- PMEPending- |
|
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ |
|
AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: ReqEn- EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- |
|
Address: fee002f8 Data: 0000 |
|
Capabilities: [90] Subsystem: Intel Corporation Cannon Lake PCH PCI Express Root Port |
|
Capabilities: [a0] Power Management version 3 |
|
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [100 v0] Null |
|
Capabilities: [140 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Capabilities: [150 v1] Precision Time Measurement |
|
PTMCap: Requester:- Responder:+ Root:+ |
|
PTMClockGranularity: 4ns |
|
PTMControl: Enabled:+ RootSelected:+ |
|
PTMEffectiveGranularity: Unknown |
|
Capabilities: [200 v1] L1 PM Substates |
|
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ |
|
PortCommonModeRestoreTime=40us PortTPowerOnTime=44us |
|
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ |
|
T_CommonMode=40us LTR1.2_Threshold=81920ns |
|
L1SubCtl2: T_PwrOn=44us |
|
Capabilities: [250 v1] Downstream Port Containment |
|
DpcCap: INT Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+ |
|
DpcCtl: Trigger:0 Cmpl- INT- ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr- |
|
DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:1f |
|
Source: 0000 |
|
Kernel driver in use: pcieport |
|
|
|
00:1c.1 PCI bridge: Intel Corporation Cannon Lake PCH PCI Express Root Port #2 (rev f0) (prog-if 00 [Normal decode]) |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0, Cache Line Size: 256 bytes |
|
Interrupt: pin B routed to IRQ 31 |
|
Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 |
|
I/O behind bridge: 00002000-00002fff [size=4K] |
|
Memory behind bridge: 81500000-816fffff [size=2M] |
|
Prefetchable memory behind bridge: 0000004000000000-00000040001fffff [size=2M] |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 256 bytes, PhantFunc 0 |
|
ExtTag- RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- |
|
MaxPayload 256 bytes, MaxReadReq 128 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <16us |
|
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x0 (downgraded) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ |
|
Slot #1, PowerLimit 10.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq+ LinkChg+ |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- |
|
Changed: MRL- PresDet- LinkState- |
|
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- |
|
RootCap: CRSVisible- |
|
RootSta: PME ReqID 0000, PMEStatus- PMEPending- |
|
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ |
|
AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- |
|
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: ReqEn- EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- |
|
Address: fee00318 Data: 0000 |
|
Capabilities: [90] Subsystem: Intel Corporation Cannon Lake PCH PCI Express Root Port |
|
Capabilities: [a0] Power Management version 3 |
|
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [100 v0] Null |
|
Capabilities: [140 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Capabilities: [150 v1] Precision Time Measurement |
|
PTMCap: Requester:- Responder:+ Root:+ |
|
PTMClockGranularity: 4ns |
|
PTMControl: Enabled:+ RootSelected:+ |
|
PTMEffectiveGranularity: Unknown |
|
Capabilities: [250 v1] Downstream Port Containment |
|
DpcCap: INT Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+ |
|
DpcCtl: Trigger:0 Cmpl- INT- ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr- |
|
DpcSta: Trigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:1f |
|
Source: 0000 |
|
Kernel driver in use: pcieport |
|
|
|
00:1e.0 Communication controller: Intel Corporation Device a328 (rev 10) |
|
Subsystem: Intel Corporation Device 7270 |
|
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0, Cache Line Size: 256 bytes |
|
Interrupt: pin A routed to IRQ 20 |
|
Region 0: Memory at 4000300000 (64-bit, non-prefetchable) [size=4K] |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [90] Vendor Specific Information: Len=14 <?> |
|
Kernel driver in use: intel-lpss |
|
Kernel modules: intel_lpss_pci |
|
|
|
00:1f.0 ISA bridge: Intel Corporation Device a30e (rev 10) |
|
Subsystem: Intel Corporation Device 7270 |
|
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
|
|
00:1f.3 Audio device: Intel Corporation Cannon Lake PCH cAVS (rev 10) |
|
Subsystem: Intel Corporation Cannon Lake PCH cAVS |
|
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 64, Cache Line Size: 256 bytes |
|
Interrupt: pin A routed to IRQ 84 |
|
Region 0: Memory at 81e10000 (64-bit, non-prefetchable) [size=16K] |
|
Region 4: Memory at 4000200000 (64-bit, non-prefetchable) [size=1M] |
|
Capabilities: [50] Power Management version 3 |
|
Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [80] Vendor Specific Information: Len=14 <?> |
|
Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee009b8 Data: 0000 |
|
Kernel driver in use: snd_hda_intel |
|
Kernel modules: snd_hda_intel, snd_soc_skl, sof_pci_dev |
|
|
|
00:1f.4 SMBus: Intel Corporation Cannon Lake PCH SMBus Controller (rev 10) |
|
Subsystem: Intel Corporation Cannon Lake PCH SMBus Controller |
|
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
|
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Interrupt: pin A routed to IRQ 16 |
|
Region 0: Memory at 81e1a000 (64-bit, non-prefetchable) [size=256] |
|
Region 4: I/O ports at 3040 [size=32] |
|
Kernel driver in use: i801_smbus |
|
Kernel modules: i2c_i801 |
|
|
|
00:1f.5 Serial bus controller [0c80]: Intel Corporation Cannon Lake PCH SPI Controller (rev 10) |
|
Subsystem: Intel Corporation Cannon Lake PCH SPI Controller |
|
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Region 0: Memory at fe010000 (32-bit, non-prefetchable) [size=4K] |
|
|
|
01:00.0 Ethernet controller: Aquantia Corp. AQC107 NBase-T/IEEE 802.3bz Ethernet Controller [AQtion] (rev 02) |
|
Subsystem: Apple Inc. AQC107 NBase-T/IEEE 802.3bz Ethernet Controller [AQtion] |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0, Cache Line Size: 256 bytes |
|
Interrupt: pin A routed to IRQ 16 |
|
Region 0: Memory at 81c00000 (64-bit, non-prefetchable) [size=64K] |
|
Region 2: Memory at 81c10000 (64-bit, non-prefetchable) [size=4K] |
|
Region 4: Memory at 81800000 (64-bit, non-prefetchable) [size=4M] |
|
Capabilities: [40] Express (v2) Endpoint, MSI 00 |
|
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us |
|
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75.000W |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset- |
|
MaxPayload 256 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend- |
|
LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s unlimited, L1 unlimited |
|
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 5GT/s (downgraded), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported |
|
AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled |
|
AtomicOpsCtl: ReqEn- |
|
LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [90] MSI-X: Enable+ Count=32 Masked- |
|
Vector table: BAR=2 offset=00000000 |
|
PBA: BAR=2 offset=00000200 |
|
Capabilities: [a0] MSI: Enable- Count=1/32 Maskable- 64bit+ |
|
Address: 0000000000000000 Data: 0000 |
|
Capabilities: [100 v2] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [150 v1] Vendor Specific Information: ID=0001 Rev=1 Len=024 <?> |
|
Capabilities: [180 v1] Secondary PCI Express <?> |
|
Kernel driver in use: atlantic |
|
Kernel modules: atlantic |
|
|
|
02:00.0 Mass storage controller: Apple Inc. ANS2 NVMe Controller (rev 01) (prog-if 02) |
|
Subsystem: Apple Inc. ANS2 NVMe Controller |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Region 0: Memory at b0000000 (64-bit, prefetchable) [size=4M] |
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Region 2: Memory at b1000000 (64-bit, prefetchable) [size=512K] |
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Region 4: Memory at b1200000 (64-bit, prefetchable) [size=64K] |
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Capabilities: [40] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ |
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Address: 0000000000000000 Data: 0000 |
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Capabilities: [70] Express (v2) Endpoint, MSI 00 |
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DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
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ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 256 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <64us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
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LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch+ ClockPM+ AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis-, LTR+, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ |
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EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- |
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Capabilities: [100 v2] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [148 v1] Secondary PCI Express <?> |
|
Capabilities: [168 v1] Latency Tolerance Reporting |
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Max snoop latency: 3145728ns |
|
Max no snoop latency: 3145728ns |
|
Capabilities: [170 v1] L1 PM Substates |
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L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ |
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PortCommonModeRestoreTime=0us PortTPowerOnTime=0us |
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L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ |
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T_CommonMode=0us LTR1.2_Threshold=81920ns |
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L1SubCtl2: T_PwrOn=44us |
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Capabilities: [180 v1] Vendor Specific Information: ID=0002 Rev=1 Len=100 <?> |
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Capabilities: [280 v1] Resizable BAR <?> |
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|
|
02:00.1 Non-VGA unclassified device: Apple Inc. T2 Bridge Controller (rev 01) |
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Subsystem: Apple Inc. T2 Bridge Controller |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Region 0: Memory at b0400000 (64-bit, prefetchable) [size=4M] |
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Region 2: Memory at b1080000 (64-bit, prefetchable) [size=512K] |
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Region 4: Memory at b1210000 (64-bit, prefetchable) [size=64K] |
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Capabilities: [40] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ |
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Address: 0000000000000000 Data: 0000 |
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Capabilities: [70] Express (v2) Endpoint, MSI 00 |
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DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
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ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 256 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <64us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
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LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch+ ClockPM+ AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis-, LTR-, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
|
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [100 v2] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [180 v1] Vendor Specific Information: ID=0002 Rev=1 Len=100 <?> |
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Capabilities: [280 v1] Resizable BAR <?> |
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|
|
02:00.2 Non-VGA unclassified device: Apple Inc. T2 Secure Enclave Processor (rev 01) |
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Subsystem: Apple Inc. T2 Secure Enclave Processor |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
|
Region 0: Memory at b0800000 (64-bit, prefetchable) [size=4M] |
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Region 2: Memory at b1100000 (64-bit, prefetchable) [size=512K] |
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Region 4: Memory at b1220000 (64-bit, prefetchable) [size=64K] |
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Capabilities: [40] Power Management version 3 |
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Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ |
|
Address: 0000000000000000 Data: 0000 |
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Capabilities: [70] Express (v2) Endpoint, MSI 00 |
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DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
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ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 256 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <64us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
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LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch+ ClockPM+ AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis-, LTR-, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [100 v2] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [180 v1] Vendor Specific Information: ID=0002 Rev=1 Len=100 <?> |
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Capabilities: [280 v1] Resizable BAR <?> |
|
|
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02:00.3 Multimedia audio controller: Apple Inc. Apple Audio Device (rev 01) |
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Subsystem: Apple Inc. Apple Audio Device |
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Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Region 0: Memory at b0c00000 (64-bit, prefetchable) [disabled] [size=4M] |
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Region 2: Memory at b1180000 (64-bit, prefetchable) [disabled] [size=512K] |
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Region 4: Memory at b1230000 (64-bit, prefetchable) [disabled] [size=64K] |
|
Capabilities: [40] Power Management version 3 |
|
Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ |
|
Address: 0000000000000000 Data: 0000 |
|
Capabilities: [70] Express (v2) Endpoint, MSI 00 |
|
DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
|
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 256 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend- |
|
LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <64us |
|
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
|
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ |
|
ExtSynch+ ClockPM+ AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Not Supported |
|
AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
|
DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis-, LTR-, OBFF Disabled |
|
AtomicOpsCtl: ReqEn- |
|
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [100 v2] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [180 v1] Vendor Specific Information: ID=0002 Rev=1 Len=100 <?> |
|
Capabilities: [280 v1] Resizable BAR <?> |
|
|
|
03:00.0 Network controller: Broadcom Inc. and subsidiaries Device 4464 (rev 03) |
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Subsystem: Apple Inc. Device 07bf |
|
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Interrupt: pin A routed to IRQ 255 |
|
Region 0: Memory at 81400000 (64-bit, non-prefetchable) [disabled] [size=32K] |
|
Region 2: Memory at 81000000 (64-bit, non-prefetchable) [disabled] [size=4M] |
|
Capabilities: [48] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=2 PME- |
|
Capabilities: [58] MSI: Enable- Count=1/16 Maskable- 64bit+ |
|
Address: 0000000000000000 Data: 0000 |
|
Capabilities: [68] Vendor Specific Information: Len=44 <?> |
|
Capabilities: [ac] Express (v2) Endpoint, MSI 00 |
|
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited |
|
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 10.000W |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag- PhantFunc- AuxPwr+ NoSnoop+ |
|
MaxPayload 256 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <2us, L1 <32us |
|
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x1 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Via WAKE# |
|
AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
|
AtomicOpsCtl: ReqEn- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [100 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [13c v1] Device Serial Number 7e-6f-d3-ff-ff-19-38-f9 |
|
Capabilities: [150 v1] Power Budgeting <?> |
|
Capabilities: [160 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending- InProgress- |
|
Capabilities: [1b0 v1] Latency Tolerance Reporting |
|
Max snoop latency: 0ns |
|
Max no snoop latency: 0ns |
|
Capabilities: [220 v1] Resizable BAR <?> |
|
Capabilities: [240 v1] L1 PM Substates |
|
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ |
|
PortCommonModeRestoreTime=0us PortTPowerOnTime=10us |
|
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- |
|
T_CommonMode=0us LTR1.2_Threshold=0ns |
|
L1SubCtl2: T_PwrOn=10us |
|
|
|
05:00.0 PCI bridge: Intel Corporation DSL6540 Thunderbolt 3 Bridge [Alpine Ridge 4C 2015] (rev 06) (prog-if 00 [Normal decode]) |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 32 |
|
Bus: primary=05, secondary=06, subordinate=7a, sec-latency=0 |
|
I/O behind bridge: 00004000-00007fff [size=16K] |
|
Memory behind bridge: 81f00000-900fffff [size=226M] |
|
Prefetchable memory behind bridge: 00000000b1300000-00000000bf2fffff [size=224M] |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00338 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation DSL6540 Thunderbolt 3 Bridge [Alpine Ridge 4C 2015] |
|
Capabilities: [c0] Express (v2) Upstream Port, MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 75.000W |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <2us |
|
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ |
|
EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP+ BadDLLP+ Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending- InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [800 v1] Latency Tolerance Reporting |
|
Max snoop latency: 0ns |
|
Max no snoop latency: 0ns |
|
Capabilities: [a00 v1] L1 PM Substates |
|
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ |
|
PortCommonModeRestoreTime=0us PortTPowerOnTime=10us |
|
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- |
|
T_CommonMode=0us LTR1.2_Threshold=0ns |
|
L1SubCtl2: T_PwrOn=10us |
|
Capabilities: [b00 v1] Precision Time Measurement |
|
PTMCap: Requester:- Responder:- Root:- |
|
PTMClockGranularity: Unimplemented |
|
PTMControl: Enabled:- RootSelected:- |
|
PTMEffectiveGranularity: Unknown |
|
Kernel driver in use: pcieport |
|
|
|
06:00.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 33 |
|
Bus: primary=06, secondary=07, subordinate=07, sec-latency=0 |
|
I/O behind bridge: None |
|
Memory behind bridge: 82000000-820fffff [size=1M] |
|
Prefetchable memory behind bridge: None |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00358 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
|
Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
|
Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
|
Changed: MRL- PresDet+ LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=1 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed+ WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending- InProgress- |
|
VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable- ID=1 ArbSelect=Fixed TC/VC=00 |
|
Status: NegoPending+ InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
06:01.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Physical Slot: 1 |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 34 |
|
Bus: primary=06, secondary=09, subordinate=41, sec-latency=0 |
|
I/O behind bridge: 00004000-00005fff [size=8K] |
|
Memory behind bridge: 82100000-890fffff [size=112M] |
|
Prefetchable memory behind bridge: 00000000b1300000-00000000b82fffff [size=112M] |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D3 NoSoftRst+ PME-Enable+ DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00378 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
|
Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk- |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ |
|
Slot #1, PowerLimit 0.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq+ LinkChg+ |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- |
|
Changed: MRL- PresDet- LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending+ InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
06:02.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 35 |
|
Bus: primary=06, secondary=08, subordinate=08, sec-latency=0 |
|
I/O behind bridge: None |
|
Memory behind bridge: 81f00000-81ffffff [size=1M] |
|
Prefetchable memory behind bridge: None |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00398 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
|
Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
|
Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
|
Changed: MRL- PresDet+ LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending- InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
06:04.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Physical Slot: 2 |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 36 |
|
Bus: primary=06, secondary=42, subordinate=7a, sec-latency=0 |
|
I/O behind bridge: 00006000-00007fff [size=8K] |
|
Memory behind bridge: 89100000-900fffff [size=112M] |
|
Prefetchable memory behind bridge: 00000000b8300000-00000000bf2fffff [size=112M] |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D3 NoSoftRst+ PME-Enable+ DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee003b8 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
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Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0 |
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ExtTag+ RBE+ |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 128 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
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LnkCap: Port #4, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
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ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
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LnkCtl: ASPM Disabled; Disabled- CommClk- |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ |
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Slot #4, PowerLimit 0.000W; Interlock- NoCompl+ |
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SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq+ LinkChg+ |
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Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
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SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- |
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Changed: MRL- PresDet- LinkState- |
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DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
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AtomicOpsCap: Routing- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- |
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AtomicOpsCtl: EgressBlck- |
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [50] Capability ID 0x15 [0000] |
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Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
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Capabilities: [200 v1] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [300 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending+ InProgress- |
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Capabilities: [400 v1] Power Budgeting <?> |
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Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
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Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
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Capabilities: [700 v1] Secondary PCI Express <?> |
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Capabilities: [900 v1] Access Control Services |
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ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
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ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
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Kernel driver in use: pcieport |
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07:00.0 System peripheral: Intel Corporation JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018] (rev 06) |
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Subsystem: Intel Corporation JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018] |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0 |
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Interrupt: pin A routed to IRQ 17 |
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Region 0: Memory at 82000000 (32-bit, non-prefetchable) [size=256K] |
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Region 1: Memory at 82040000 (32-bit, non-prefetchable) [size=4K] |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [88] MSI: Enable- Count=1/1 Maskable- 64bit+ |
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Address: 0000000000000000 Data: 0000 |
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Capabilities: [c0] Express (v2) Endpoint, MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
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ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 128 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp- |
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [a0] MSI-X: Enable+ Count=16 Masked- |
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Vector table: BAR=1 offset=00000000 |
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PBA: BAR=1 offset=00000fa0 |
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Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
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Capabilities: [200 v1] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [300 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [400 v1] Power Budgeting <?> |
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Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
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Capabilities: [600 v1] Latency Tolerance Reporting |
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Max snoop latency: 0ns |
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Max no snoop latency: 0ns |
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Kernel driver in use: thunderbolt |
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Kernel modules: thunderbolt |
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08:00.0 USB controller: Intel Corporation JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] (rev 06) (prog-if 30 [XHCI]) |
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Subsystem: Intel Corporation JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 43 |
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Region 0: Memory at 81f00000 (32-bit, non-prefetchable) [size=64K] |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [88] MSI: Enable+ Count=1/8 Maskable- 64bit+ |
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Address: 00000000fee00498 Data: 0000 |
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Capabilities: [c0] Express (v2) Endpoint, MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
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ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 128 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [100 v1] Device Serial Number cb-45-c8-e8-31-b7-d0-00 |
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Capabilities: [200 v1] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [300 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [400 v1] Power Budgeting <?> |
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Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
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Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
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Capabilities: [700 v1] Secondary PCI Express <?> |
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Capabilities: [800 v1] Latency Tolerance Reporting |
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Max snoop latency: 0ns |
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Max no snoop latency: 0ns |
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Kernel driver in use: xhci_hcd |
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Kernel modules: xhci_pci |
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7b:00.0 PCI bridge: Intel Corporation DSL6540 Thunderbolt 3 Bridge [Alpine Ridge 4C 2015] (rev 06) (prog-if 00 [Normal decode]) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0 |
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Interrupt: pin A routed to IRQ 37 |
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Bus: primary=7b, secondary=7c, subordinate=f0, sec-latency=0 |
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I/O behind bridge: 00008000-0000bfff [size=16K] |
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Memory behind bridge: 90100000-9e2fffff [size=226M] |
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Prefetchable memory behind bridge: 00000000bf300000-00000000cd2fffff [size=224M] |
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Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
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BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
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PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
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Address: 00000000fee003d8 Data: 0000 |
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Capabilities: [ac] Subsystem: Intel Corporation DSL6540 Thunderbolt 3 Bridge [Alpine Ridge 4C 2015] |
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Capabilities: [c0] Express (v2) Upstream Port, MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0 |
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ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 75.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 128 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <2us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
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LnkCtl: ASPM Disabled; Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 8GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported |
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AtomicOpsCap: Routing- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
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AtomicOpsCtl: EgressBlck- |
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LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ |
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EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- |
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Capabilities: [50] Capability ID 0x15 [0000] |
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Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
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Capabilities: [200 v1] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [300 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [400 v1] Power Budgeting <?> |
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Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
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Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
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Capabilities: [700 v1] Secondary PCI Express <?> |
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Capabilities: [800 v1] Latency Tolerance Reporting |
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Max snoop latency: 0ns |
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Max no snoop latency: 0ns |
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Capabilities: [a00 v1] L1 PM Substates |
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L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ |
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PortCommonModeRestoreTime=0us PortTPowerOnTime=10us |
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L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- |
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T_CommonMode=0us LTR1.2_Threshold=0ns |
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L1SubCtl2: T_PwrOn=10us |
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Capabilities: [b00 v1] Precision Time Measurement |
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PTMCap: Requester:- Responder:- Root:- |
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PTMClockGranularity: Unimplemented |
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PTMControl: Enabled:- RootSelected:- |
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PTMEffectiveGranularity: Unknown |
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Kernel driver in use: pcieport |
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7c:00.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0 |
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Interrupt: pin A routed to IRQ 38 |
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Bus: primary=7c, secondary=7d, subordinate=7d, sec-latency=0 |
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I/O behind bridge: None |
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Memory behind bridge: 90200000-902fffff [size=1M] |
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Prefetchable memory behind bridge: None |
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Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
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BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
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PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
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Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
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Address: 00000000fee003f8 Data: 0000 |
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Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
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Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0 |
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ExtTag+ RBE+ |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 128 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
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ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
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LnkCtl: ASPM Disabled; Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt- |
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SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
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Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ |
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SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
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Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
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SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
|
Changed: MRL- PresDet+ LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=1 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed+ WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending- InProgress- |
|
VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable- ID=1 ArbSelect=Fixed TC/VC=00 |
|
Status: NegoPending+ InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
7c:01.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Physical Slot: 1-1 |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 39 |
|
Bus: primary=7c, secondary=7f, subordinate=b7, sec-latency=0 |
|
I/O behind bridge: 00008000-00009fff [size=8K] |
|
Memory behind bridge: 90300000-972fffff [size=112M] |
|
Prefetchable memory behind bridge: 00000000bf300000-00000000c62fffff [size=112M] |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D3 NoSoftRst+ PME-Enable+ DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00418 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
|
Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk- |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ |
|
Slot #1, PowerLimit 0.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq+ LinkChg+ |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- |
|
Changed: MRL- PresDet- LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending+ InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
7c:02.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 40 |
|
Bus: primary=7c, secondary=7e, subordinate=7e, sec-latency=0 |
|
I/O behind bridge: None |
|
Memory behind bridge: 90100000-901fffff [size=1M] |
|
Prefetchable memory behind bridge: None |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00438 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
|
Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- |
|
Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- |
|
Changed: MRL- PresDet+ LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending- InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
7c:04.0 PCI bridge: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] (rev 06) (prog-if 00 [Normal decode]) |
|
Physical Slot: 2-1 |
|
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 41 |
|
Bus: primary=7c, secondary=b8, subordinate=f0, sec-latency=0 |
|
I/O behind bridge: 0000a000-0000bfff [size=8K] |
|
Memory behind bridge: 97300000-9e2fffff [size=112M] |
|
Prefetchable memory behind bridge: 00000000c6300000-00000000cd2fffff [size=112M] |
|
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- |
|
BridgeCtl: Parity- SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- |
|
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D3 NoSoftRst+ PME-Enable+ DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ |
|
Address: 00000000fee00458 Data: 0000 |
|
Capabilities: [ac] Subsystem: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] |
|
Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0 |
|
ExtTag+ RBE+ |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #4, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ |
|
LnkCtl: ASPM Disabled; Disabled- CommClk- |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
|
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
|
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ |
|
Slot #4, PowerLimit 0.000W; Interlock- NoCompl+ |
|
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq+ LinkChg+ |
|
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- |
|
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- |
|
Changed: MRL- PresDet- LinkState- |
|
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported ARIFwd- |
|
AtomicOpsCap: Routing- |
|
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- |
|
AtomicOpsCtl: EgressBlck- |
|
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB |
|
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
|
Compliance De-emphasis: -6dB |
|
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
|
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
|
Capabilities: [50] Capability ID 0x15 [0000] |
|
Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
|
Capabilities: [200 v1] Advanced Error Reporting |
|
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
|
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
|
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
|
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
|
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
|
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
|
HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
|
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
|
Status: InProgress- |
|
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
|
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- |
|
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
|
Status: NegoPending+ InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
|
Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
|
Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [900 v1] Access Control Services |
|
ACSCap: SrcValid+ TransBlk+ ReqRedir- CmpltRedir- UpstreamFwd+ EgressCtrl- DirectTrans- |
|
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- |
|
Kernel driver in use: pcieport |
|
|
|
7d:00.0 System peripheral: Intel Corporation JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018] (rev 06) |
|
Subsystem: Intel Corporation JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018] |
|
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
|
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
|
Latency: 0 |
|
Interrupt: pin A routed to IRQ 18 |
|
Region 0: Memory at 90200000 (32-bit, non-prefetchable) [size=256K] |
|
Region 1: Memory at 90240000 (32-bit, non-prefetchable) [size=4K] |
|
Capabilities: [80] Power Management version 3 |
|
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
|
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- |
|
Capabilities: [88] MSI: Enable- Count=1/1 Maskable- 64bit+ |
|
Address: 0000000000000000 Data: 0000 |
|
Capabilities: [c0] Express (v2) Endpoint, MSI 00 |
|
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
|
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W |
|
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
|
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
|
MaxPayload 128 bytes, MaxReadReq 512 bytes |
|
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
|
LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
|
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp- |
|
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
|
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
|
LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [a0] MSI-X: Enable+ Count=16 Masked- |
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Vector table: BAR=1 offset=00000000 |
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PBA: BAR=1 offset=00000fa0 |
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Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
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Capabilities: [200 v1] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
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Capabilities: [300 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
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Arb: Fixed- WRR32- WRR64- WRR128- |
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Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
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Capabilities: [400 v1] Power Budgeting <?> |
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Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
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Capabilities: [600 v1] Latency Tolerance Reporting |
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Max snoop latency: 0ns |
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Max no snoop latency: 0ns |
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Kernel driver in use: thunderbolt |
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Kernel modules: thunderbolt |
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|
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7e:00.0 USB controller: Intel Corporation JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] (rev 06) (prog-if 30 [XHCI]) |
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Subsystem: Intel Corporation JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] |
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ |
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- |
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Latency: 0, Cache Line Size: 256 bytes |
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Interrupt: pin A routed to IRQ 44 |
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Region 0: Memory at 90100000 (32-bit, non-prefetchable) [size=64K] |
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Capabilities: [80] Power Management version 3 |
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Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) |
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- |
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Capabilities: [88] MSI: Enable+ Count=1/8 Maskable- 64bit+ |
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Address: 00000000fee004b8 Data: 0000 |
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Capabilities: [c0] Express (v2) Endpoint, MSI 00 |
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DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited |
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ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W |
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DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- |
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RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ |
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MaxPayload 128 bytes, MaxReadReq 512 bytes |
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DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- |
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LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L1, Exit Latency L1 <1us |
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ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ |
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ |
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- |
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LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) |
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TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- |
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DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Not Supported |
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AtomicOpsCap: 32bit- 64bit- 128bitCAS- |
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled |
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AtomicOpsCtl: ReqEn- |
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- |
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- |
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Compliance De-emphasis: -6dB |
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LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- |
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EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- |
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Capabilities: [100 v1] Device Serial Number cb-45-c8-b0-ce-b7-d0-00 |
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Capabilities: [200 v1] Advanced Error Reporting |
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- |
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UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- |
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- |
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ |
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AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- |
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MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- |
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HeaderLog: 00000000 00000000 00000000 00000000 |
|
Capabilities: [300 v1] Virtual Channel |
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 |
|
Arb: Fixed- WRR32- WRR64- WRR128- |
|
Ctrl: ArbSelect=Fixed |
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Status: InProgress- |
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- |
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Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- |
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff |
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Status: NegoPending- InProgress- |
|
Capabilities: [400 v1] Power Budgeting <?> |
|
Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=100 <?> |
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Capabilities: [600 v1] Vendor Specific Information: ID=8086 Rev=2 Len=04c <?> |
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Capabilities: [700 v1] Secondary PCI Express <?> |
|
Capabilities: [800 v1] Latency Tolerance Reporting |
|
Max snoop latency: 0ns |
|
Max no snoop latency: 0ns |
|
Kernel driver in use: xhci_hcd |
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Kernel modules: xhci_pci |
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|
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[pklaus@hades ~]$ |