Skip to content

Instantly share code, notes, and snippets.

View prydin's full-sized avatar

Pontus Rydin prydin

View GitHub Profile
@prydin
prydin / noise.py
Created January 9, 2025 15:19
Low noise preamp simulation
import numpy as np
noise_db = -80 # Noise added by each amplifier
gain_db = 60 # Closed loop gain
cycles = 2
resolution = 1000
length = np.pi * 2 * cycles
signal = np.sin(np.arange(0, length, length / resolution))
raw_noise = 10**(noise_db / 20)
@prydin
prydin / part0.v
Last active December 20, 2024 00:16
ESC Part 0
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/17/2024 08:29:18 AM
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
Version 4
SHEET 1 5264 1236
WIRE 272 -80 272 -112
WIRE 1600 -80 1600 -112
WIRE -496 -64 -496 -144
WIRE 208 -32 128 -32
WIRE 1536 -32 1456 -32
WIRE 128 16 128 -32
WIRE 272 32 272 16
WIRE 1600 32 1600 16
@prydin
prydin / thermo_amp.asc
Created October 14, 2024 13:30
Thermocouple amplifier
Version 4
SHEET 1 880 680
WIRE -448 -80 -560 -80
WIRE -416 -80 -448 -80
WIRE -320 -80 -336 -80
WIRE 96 -80 -320 -80
WIRE -560 -48 -560 -80
WIRE -320 -32 -320 -80
WIRE -576 48 -576 32
WIRE -560 80 -560 32
@prydin
prydin / thd_mat.py
Created October 6, 2024 01:46
THD calculation
import math
import numpy as np
import scipy as sci
from numpy.linalg.linalg import solve
from scipy.signal import correlate, fftconvolve
import matplotlib.pyplot as plt
import cmath
def parabolic(f, x):
@prydin
prydin / dac.v
Created April 15, 2024 00:57
Delta/sigma-DAC
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/09/2024 02:08:14 PM
// Design Name:
// Module Name: dac
// Project Name:
// Target Devices:
@prydin
prydin / am.m
Created April 1, 2024 23:46
AM Detection example
# Generate test signal
t = linspace(0,120*pi, 1000)
baseband = cos(t/40)
carrier = cos(t)
modulated = carrier .* baseband
# Downshift and split into I and Q
fq_offset = 1.05 # Carrier and LO are off by 5%
i = cos(t*fq_offset) .* modulated
q = sin(t*fq_offset) .* modulated
@prydin
prydin / radio.py
Created February 15, 2024 23:39
AM demodulation pipeline
# Baseband sample rate
import math
import matplotlib.pyplot as plt
import numpy
from scipy import signal, fft
import numpy as np
# RF sampling rate
rf_rate = 6e6
@prydin
prydin / dds.v
Last active November 15, 2023 14:56
DDS attempt
module dds
#(parameter ACC_LENGTH = 48,
parameter PHASE_LENGTH = 14
) (
input sys_clk,
input spi_clk,
input spi_data,
input freq_cs,
input phaseshift_cs,
input [1:0] mode_in,
@prydin
prydin / vrohelper.py
Created June 14, 2023 19:00
Simplified vRO API
from functools import lru_cache
import requests
import time
class AutomationClient:
"""
Low level Aria Automation/Orchestration client.
"""