kendryte manual

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\begin_body

\begin_layout Title

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K210
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\begin_layout Title

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Technical Specification
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\begin_layout Author
Jia Nan Technology KENDRYTE.COM
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\begin_layout Subsection*
About this manual 
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This document provides the user with an introduction to the Kendryte hardware
 specifications.
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Release notes
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Date
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Version
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Release notes
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2018-08-01
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V0.1.0
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Initial version
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2018-09-13
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V0.1.1
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Fix description of errors in SPI and GPIO
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2018-09-14
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V0.1.2
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2018-09-17
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V0.1.3
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2018-09-18
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V0.1.4
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Add Kendryte system architecture diagram
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2018-09-19
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V0.1.5
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\begin_layout Subsection*
Disclaimer
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The information in this document, including the referenced URL address,
 is subject to change without notice.
 The document is provided "as is" and does not bear any Warranty, including
 any warranties of merchantability, fitness for a particular purpose or
 non-infringement, and any proposal, specification or sample referred to
 elsewhere Any guarantees arrived.
 This document is not responsible for any infringement of any patent rights
 arising out of the use of the information in this document.
 This article This document does not grant any intellectual property licenses,
 whether express or implied, by estoppel or otherwise.
 implied in the text All trademark names, trademarks and registered trademarks
 are the property of their respective owners and are hereby acknowledged.
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Copyright notice 
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Copyright © 2018 Jia Nan Technology.
 all rights reserved.
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\begin_layout Section
Overview 
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\begin_layout Standard
The Kendryte K210 is a system-on-chip (SoC) that integrates machine vision
 and machine hearing.
 Use TSMC ultra low power It consumes 28nm advanced process and has dual-core
 64-bit processor with good power performance, stability and reliability.
 The program strives Zero threshold development, can be deployed in the
 user's products in the shortest time, giving the product artificial intelligenc
e.
\end_layout

\begin_layout Standard
The Kendryte K210 is located in the SoC of the AI and IoT markets and is
 a very convenient MCU.
 Kendryte Chinese means surveying intelligence, while surveying intelligence
 is taken from surveying and searching.
 The main application area of this chip is the Internet of Things, in the
 Internet of Things.
 The field is developed and therefore is a survey; this chip mainly provides
 artificial intelligence solutions, which are explored in the field of artificia
l intelligence, so Exploring wisdom.
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\begin_layout Itemize
Have machine vision capabilities
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\begin_layout Itemize
With machine hearing ability
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\begin_layout Itemize
Better low power vision processing speed and accuracy 
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\begin_layout Itemize
Convolutional artificial neural network hardware accelerator KPU for high
 performance convolutional artificial neural network operations 
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\begin_layout Itemize
TSMC 28nm advanced process, temperature range -40 ° C to 125 ° C, stable
 and reliable 
\end_layout

\begin_layout Itemize
Support firmware encryption, difficult to crack using common methods 
\end_layout

\begin_layout Itemize
Unique programmable IO array for more flexible product design 
\end_layout

\begin_layout Itemize
Low voltage, lower power consumption compared to systems with the same processin
g power 
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\begin_layout Itemize
3.3V/1.8V dual voltage support, no level shifting, cost savings
\end_layout

\begin_layout Subsection
AI solution
\end_layout

\begin_layout Subsubsection
1.1.1 Machine Vision 
\end_layout

\begin_layout Standard
With machine vision capabilities, the Kendryte K210 is a zero-threshold
 machine vision embedded solution.
 It can be used in low power consumption Line convolutional neural network
 calculation.
 The chip can achieve the following machine vision capabilities:
\end_layout

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General target detection based on convolutional neural networks 
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Image classification tasks based on convolutional neural networks 
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Face detection and face recognition 
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Get the size and coordinates of the detected target in real time
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Get the type of target being detected in real time
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\begin_layout Subsubsection
1.1.2 Machine hearing
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The Kendryte K210 has machine hearing capabilities.
 On-chip high-performance microphone array audio processor for real-time
 sound source Orientation and beamforming.
 The chip can achieve the following machine hearing capabilities:
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Sound source orientation
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Sound field imaging
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Beamforming
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Voice wake up
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Speech Recognition
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\begin_layout Subsubsection
1.1.3 Visual/Hearing Hybrid Solution 
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The Kendryte K210 combines machine vision and machine hearing to provide
 even more powerful features.
 On the one hand, it can be passed in the application.
 Sound source localization and sound field imaging assist the machine vision
 to track the target, and the target can be obtained by the general target
 detection.
 Hearing beamforming the orientation.
 On the other hand, the image can be obtained by the camera to obtain the
 direction of the person, so that the microphone array Point to the person
 by beamforming.
 At the same time, the direction of a speaker can be determined according
 to the microphone array, and the camera is rotated to point to the person.
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\begin_layout Subsection
system structure
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\begin_inset Graphics
	filename sysDiag.png

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\begin_layout Standard
Kendryte K210 includes RISC-V 64-bit dual-core CPUs with built-in independent
 FPUs on each core.
 The core functions of the K210 are machine vision and hearing.
 Includes KPU for calculating convolutional artificial neural networks and
 APU for processing microphone array inputs.
 
\end_layout

\begin_layout Standard
Fast Fourier transform accelerator allows for high performance complex FFT
 calculations.
 So for most machine learning algorithms, the K210 has high-performance
 processing power.
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\begin_layout Standard
The K210 embeds the AES and SHA256 algorithm accelerators to provide users
 with basic security features.
 The K210 features high-performance, low-power SRAM and powerful DMA for
 superior data throughput.
 K210 has a wealth of peripheral units: DVP, JTAG, OTP, FPIOA, GPIO, UART,
 SPI, RTC, I2S, I2C, WDT, Timer and PWM can meet a large number of application
 scenarios.
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\begin_layout Section
Pin definition 
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\begin_layout Standard
The K210 uses a well-designed pin layout to ensure that the signal is on
 the BGA outer ring for PCB engineers to fan out and route.
 Electrical performance reduces design difficulty.
 Since the K210 contains multiple IO signals from the power domain and different
 power domains may have different voltages, the following will be used.
 Domain description of the list: 
\end_layout

\begin_layout Subsection
Pin layout
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\begin_layout Standard
The pin definition of the chip is as shown above (top view, the solder ball
 is facing downwards).
 The chip is packaged in BGA144, square, with 12 pins on each side.
 The chip has a width of 8mm, a length of 8mm and a height of 0.953mm.
 
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\begin_layout Subsection
Pin description
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5
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2.3
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\begin_layout Subsection
Power distribution
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10
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2.4
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\begin_layout Subsection
Reset circuit
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11
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2.5
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\begin_layout Subsection
Special pin
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11
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Chapter 3
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\begin_layout Section
Functional description
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12
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3.1
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Central Processing Unit (CPU) 
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This chip is equipped with a RISC-V ISA-based dual-core 64-bit high-performance,
 low-power CPU with the following features:
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Number of cores
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2 core
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Dual-core peer, each core has an independent FPU
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Processor bit width
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64 bit
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64-bit CPU bit width provides a bit-wide basis for high-performance algorithm
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Nominal frequency
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400MHz
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Platform interrupt management
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PLIC
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Support for advanced interrupt management, supporting 64 external interrupt
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Support for CPU built-in timer interrupts and cross-core interrupts
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\color none
Instruction cache
\end_layout

\end_inset
</cell>
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\begin_inset Text

\begin_layout Plain Layout

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32KiB×2
\end_layout

\end_inset
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Core 0 and Core 1 each have a 32 kilobyte instruction cache to improve dual-core
 instruction read performance
\end_layout

\end_inset
</cell>
</row>
<row>
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Data cache
\end_layout

\end_inset
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32KiB×2
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\end_inset
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Core 0 and Core 1 each have 32 kilobytes of data cache for improved dual-core
 data read performance
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="right" valignment="top" bottomline="true" usebox="none">
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\begin_layout Plain Layout

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On-chip SRAM
\end_layout

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8MiB
\end_layout

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A total of 8 megabytes of on-chip SRAM, see the SRAM chapter for details.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Subsubsection
CPU instruction features
\end_layout

\begin_layout Itemize
Powerful dual-core 64-bit open architecture-based processor with rich community
 resources
\end_layout

\begin_layout Itemize
Support for I extensions, ie Base Integer Instruction Set extensions
\end_layout

\begin_layout Itemize
Support M extension, ie integer multiplication and division extension, hardware
 acceleration for high performance integer multiplication and division
\end_layout

\begin_layout Itemize
Support for A extensions, atomic operations extensions, hardware implementations
 of atomic operations required by software and operating systems
\end_layout

\begin_layout Itemize
Support for C extensions, ie compression instruction extensions, for higher
 code density and operational efficiency through compiler compression instructio
ns
\end_layout

\begin_layout Itemize
Support different privilege levels, can be executed by privileged instructions,
 and more secure
\end_layout

\begin_layout Subsubsection
Functional description
\end_layout

\begin_layout Standard
FPU and floating point computing power
\end_layout

\begin_layout Itemize
The FPU meets the IEEE754-2008 standard, and the calculation process is
 pipelined and has strong computing power.
 
\end_layout

\begin_layout Itemize
Core 0 and Core 1 each have a separate FPU, and both cores are capable of
 high-performance hardware floating-point computing
\end_layout

\begin_layout Itemize
Support for F extension, single-precision floating-point expansion, CPU-embedded
 FPU supports single-precision floating-point hardware acceleration 
\end_layout

\begin_layout Itemize
Support for D extension, double-precision floating-point expansion, CPU-embedded
 FPU supports double-precision floating-point hardware acceleration
\end_layout

\begin_layout Itemize
FPU with divider to support single-precision, double-precision floating-point
 hardware division 
\end_layout

\begin_layout Itemize
FPU has a square root operator that supports single-precision, double-precision
 floating-point hardware square root operations
\end_layout

\begin_layout Subsubsection
3.1.3 Advanced Interrupt Management Capabilities 
\end_layout

\begin_layout Standard
The PLIC controller of the RISC-V CPU supports flexible advanced interrupt
 management, which can be configured with 64 external interrupt sources
 in 7 priority levels.
 Each core can be configured independently:
\end_layout

\begin_layout Itemize
Interrupt management and interrupt routing control for two cores independently
\end_layout

\begin_layout Itemize
Support for software interrupts, and dual cores can trigger cross-core interrupt
s 
\end_layout

\begin_layout Itemize
Support CPU built-in timer interrupt, both cores are freely configurable
\end_layout

\begin_layout Itemize
Advanced external interrupt management, supporting 64 external interrupt
 sources, each interrupt source can be configured with 7 priority levels
\end_layout

\begin_layout Subsubsection
3.1.4 Debugging ability 
\end_layout

\begin_layout Itemize
Support performance monitoring instructions to count instruction execution
 cycles
\end_layout

\begin_layout Itemize
High-speed UART and JTAG interface for debugging 
\end_layout

\begin_layout Itemize
Support DEBUG mode and hardware breakpoints 
\end_layout

\begin_layout Subsection
Neural Network Processor (KPU)
\end_layout

\begin_layout Standard
KPU is a general-purpose neural network processor with built-in convolution,
 batch normalization, activation, and pooling operations.
 It can be used to implement faces or objects.
 Time detection, the specific characteristics are as follows:
\end_layout

\begin_layout Itemize
Support for the fixed-point model trained by the mainstream training framework
 in accordance with specific restriction rules 
\end_layout

\begin_layout Itemize
There is no direct limit on the number of network layers.
 It supports separate configuration of each layer of convolutional neural
 network parameters, including the number of input and output channels,
 input and output.
 Travel wide
\end_layout

\begin_layout Itemize
Support for two convolution kernels 1x1 and 3x3 
\end_layout

\begin_layout Itemize
Support for any form of activation function 
\end_layout

\begin_layout Itemize
Maximum support for neural network parameters in real-time operation from
 5.5MiB to 5.9MiB 
\end_layout

\begin_layout Itemize
Maximum supported network parameter size when working in non-real time (Flash
 capacity - software volume)
\end_layout

\begin_layout Standard
Functional description Working condition Real time (≥ 30fps) Non-real time
 (<10fps)*1
\end_layout

\begin_layout Standard
Maximum fixed point model size (MiB)
\end_layout

\begin_layout Standard
Pre-quantization floating-point model size (MiB)
\end_layout

\begin_layout Standard
5.9
\end_layout

\begin_layout Standard
11.8
\end_layout

\begin_layout Standard
And Flash
\end_layout

\begin_layout Standard
Capacity related *2
\end_layout

\begin_layout Standard
Related to Flash capacity
\end_layout

\begin_layout Standard
The internal structure of the KPU is shown below.
 Main control unit
\end_layout

\begin_layout Standard
Parameter parsing unit
\end_layout

\begin_layout Standard
Operation control unit
\end_layout

\begin_layout Standard
Gs interface
\end_layout

\begin_layout Standard
Main memory
\end_layout

\begin_layout Standard
AXI
\end_layout

\begin_layout Standard
KPU unit
\end_layout

\begin_layout Standard
bus
\end_layout

\begin_layout Standard
Gm interface
\end_layout

\begin_layout Standard
3.3
\end_layout

\begin_layout Standard
Write back unit
\end_layout

\begin_layout Standard
AXI bus
\end_layout

\begin_layout Standard
Parameter memory
\end_layout

\begin_layout Standard
3.3
\end_layout

\begin_layout Subsection
Audio Processor (APU) 
\end_layout

\begin_layout Standard
The APU pre-processing module is responsible for the pre-processing of voice
 direction scanning and voice data output.
 The functional characteristics of the APU pre-processing module are: 
\end_layout

\begin_layout Itemize
Can support up to 8 audio input streams, ie 4 channels of dual channel 
\end_layout

\begin_layout Itemize
Can support simultaneous sound source pre-processing and beamforming in
 up to 16 directions 
\end_layout

\begin_layout Itemize
Can support a valid voice stream output 
\end_layout

\begin_layout Itemize
Internal audio signal processing accuracy reaches 16-bit 
\end_layout

\begin_layout Itemize
Input audio signal supports 12-bit, 16-bit, 24-bit, 32-bit precision
\end_layout

\begin_layout Itemize
Support multi-channel raw signal direct output
\end_layout

\begin_layout Itemize
Can support audio input up to 192K sample rate 
\end_layout

\begin_layout Itemize
Built-in FFT transform unit to provide 512-point fast Fourier transform
 for audio data 
\end_layout

\begin_layout Itemize
Store output data into SoC's system memory using system DMAC
\end_layout

\begin_layout Standard
*1 *2
\end_layout

\begin_layout Standard
Non-real-time applications are typically used for audio applications, and
 such applications typically do not require neural network output within
 33ms.
 Flash size can be selected as: SPI NOR Flash (8MiB, 16MiB, 32MiB), SPI
 NAND Flash (64MiB, 128MiB, 256MiB), user can Choose the right Flash as
 needed.
\end_layout

\begin_layout Subsection
Static Random Access Memory (SRAM)
\end_layout

\begin_layout Standard
.
 .
 The SRAM consists of two parts, 6MiB of on-chip general-purpose SRAM memory
 and 2MiB of on-chip AI SRAM memory.
 8MiB (1MiB is 1 megabyte).
 Among them, the AI SRAM memory is the memory allocated for the KPU.
 They are distributed over consecutive address spaces In between, it can
 be accessed not only through the cache interface of the CPU, but also through
 the non-cache interface.
\end_layout

\begin_layout Standard
SRAM map distribution: Module name
\end_layout

\begin_layout Standard
Mapping type
\end_layout

\begin_layout Standard
Start address
\end_layout

\begin_layout Standard
End address
\end_layout

\begin_layout Standard
size of space
\end_layout

\begin_layout Standard
General purpose SRAM memory
\end_layout

\begin_layout Standard
CPU cache
\end_layout

\begin_layout Standard
0x80000000
\end_layout

\begin_layout Standard
0x805FFFFF
\end_layout

\begin_layout Standard
0x600000
\end_layout

\begin_layout Standard
AI SRAM memory
\end_layout

\begin_layout Standard
CPU cache
\end_layout

\begin_layout Standard
0x80600000
\end_layout

\begin_layout Standard
0x807FFFFF
\end_layout

\begin_layout Standard
0x200000
\end_layout

\begin_layout Standard
General purpose SRAM memory
\end_layout

\begin_layout Standard
Non-CPU cache
\end_layout

\begin_layout Standard
0x40000000
\end_layout

\begin_layout Standard
0x405FFFFF
\end_layout

\begin_layout Standard
0x600000
\end_layout

\begin_layout Standard
AI SRAM memory
\end_layout

\begin_layout Standard
Non-CPU cache
\end_layout

\begin_layout Standard
0x40600000
\end_layout

\begin_layout Standard
0x407FFFFF
\end_layout

\begin_layout Standard
0x200000
\end_layout

\begin_layout Subsubsection
3.4.1 General SRAM Memory 
\end_layout

\begin_layout Standard
The general purpose SRAM memory is accessible at any time during normal
 operation of the chip.
 The memory is divided into two banks, MEM0 and
\end_layout

\begin_layout Standard
MEM1, and the DMA controller can operate different banks simultaneously.
 General purpose SRAM memory address space:
\end_layout

\begin_layout Standard
3.4.2
\end_layout

\begin_layout Standard
Module name
\end_layout

\begin_layout Standard
Mapping type
\end_layout

\begin_layout Standard
Start address
\end_layout

\begin_layout Standard
End address
\end_layout

\begin_layout Standard
size of space
\end_layout

\begin_layout Standard
MEM0
\end_layout

\begin_layout Standard
CPU cache
\end_layout

\begin_layout Standard
0x80000000
\end_layout

\begin_layout Standard
0x803FFFFF
\end_layout

\begin_layout Standard
0x400000
\end_layout

\begin_layout Standard
MEM1
\end_layout

\begin_layout Standard
CPU cache
\end_layout

\begin_layout Standard
0x80400000
\end_layout

\begin_layout Standard
0x805FFFFF
\end_layout

\begin_layout Standard
0x200000
\end_layout

\begin_layout Standard
MEM0
\end_layout

\begin_layout Standard
Non-CPU cache
\end_layout

\begin_layout Standard
0x40000000
\end_layout

\begin_layout Standard
0x403FFFFF
\end_layout

\begin_layout Standard
0x400000
\end_layout

\begin_layout Standard
MEM1
\end_layout

\begin_layout Standard
Non-CPU cache
\end_layout

\begin_layout Standard
0x40400000
\end_layout

\begin_layout Standard
0x405FFFFF
\end_layout

\begin_layout Standard
0x200000
\end_layout

\begin_layout Standard
AI SRAM memory
\end_layout

\begin_layout Standard
The AI SRAM memory is only accessible if the following conditions are met:
 
\end_layout

\begin_layout Itemize
PLL1 is enabled and the clock system is configured correctly 
\end_layout

\begin_layout Itemize
KPU is not performing neural network calculations AI SRAM memory address
 space:
\end_layout

\begin_layout Standard
Chapter 3
\end_layout

\begin_layout Standard
3.5
\end_layout

\begin_layout Standard
16
\end_layout

\begin_layout Standard
Functional description Module name
\end_layout

\begin_layout Standard
Mapping type
\end_layout

\begin_layout Standard
Start address
\end_layout

\begin_layout Standard
End address
\end_layout

\begin_layout Standard
size of space
\end_layout

\begin_layout Standard
AI SRAM memory
\end_layout

\begin_layout Standard
CPU cache
\end_layout

\begin_layout Standard
0x80600000
\end_layout

\begin_layout Standard
0x807FFFFF
\end_layout

\begin_layout Standard
0x200000
\end_layout

\begin_layout Standard
AI SRAM memory
\end_layout

\begin_layout Standard
Non-CPU cache
\end_layout

\begin_layout Standard
0x40600000
\end_layout

\begin_layout Standard
0x407FFFFF
\end_layout

\begin_layout Standard
0x200000.
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
 .
\end_layout

\begin_layout Standard
15
\end_layout

\begin_layout Standard
3.5
\end_layout

\begin_layout Subsection
System Controller (SYSCTL)
\end_layout

\begin_layout Standard
Control chip clock, reset and system control registers:
\end_layout

\begin_layout Itemize
Configure the frequency of the PLL 
\end_layout

\begin_layout Itemize
Configure clock selection 
\end_layout

\begin_layout Itemize
Configure the division ratio of the peripheral clock 
\end_layout

\begin_layout Itemize
Control clock enable 
\end_layout

\begin_layout Itemize
Control module reset
\end_layout

\begin_layout Itemize
• Select DMA handshake signal
\end_layout

\begin_layout Subsection
Field Programmable IO Array (FPIOA/IOMUX)
\end_layout

\begin_layout Standard
FPIOA allows users to map 255 internal functions to 48 free IOs on the periphery
 of the chip: 
\end_layout

\begin_layout Itemize
Support for IO programmable function selection 
\end_layout

\begin_layout Itemize
8 drive capability options for IO output support 
\end_layout

\begin_layout Itemize
Support for internal pull-up resistor selection of IO 
\end_layout

\begin_layout Itemize
Support for internal pull-down resistor selection of IO 
\end_layout

\begin_layout Itemize
Internal Schmitt trigger settings that support IO input 
\end_layout

\begin_layout Itemize
Support for slope control of IO output
\end_layout

\begin_layout Itemize
Support for level setting of internal input logic
\end_layout

\begin_layout Subsection
One Time Programmable Memory (OTP) 
\end_layout

\begin_layout Standard
OTP is a one-time programmable memory unit with specific application features
 as follows: 
\end_layout

\begin_layout Itemize
128Kbit of large storage space 
\end_layout

\begin_layout Itemize
Internally divides multiple BLOCKs with different capacities, each BLOCK
 corresponds to a write protection bit, which can be separately written
 and protected.
 
\end_layout

\begin_layout Itemize
Has a bad point repair function 
\end_layout

\begin_layout Itemize
Internally stored 64 REGISTER_ENABLE flag bits that can be used as switches
 to control the behavior of certain SoC hardware circuits
\end_layout

\begin_layout Itemize
Can store 128-bit AES encryption and decryption required KEY, hardware-only
 write trusted storage area
\end_layout

\begin_layout Subsection
Advanced Encryption Accelerator (AES Accelerater) 
\end_layout

\begin_layout Standard
Advanced Encryption Accelerator (AES Accelerater)
\end_layout

\begin_layout Standard
The AES Accelerator is a module for encryption and decryption.
 The specific performance is as follows:
\end_layout

\begin_layout Itemize
Support ECB, CBC, GCM three encryption methods 
\end_layout

\begin_layout Itemize
Supports 128-bit, 192-bit, 256-bit KEY 
\end_layout

\begin_layout Itemize
KEY can be configured by software and protected by hardware circuit 
\end_layout

\begin_layout Itemize
Support DMA transfer 
\end_layout

\begin_layout Subsection
Digital Video Interface (DVP).
\end_layout

\begin_layout Standard
DVP is a camera interface module with the following features: 
\end_layout

\begin_layout Itemize
Camera with DVP interface
\end_layout

\begin_layout Itemize
Support for SCCB protocol configuration camera register 
\end_layout

\begin_layout Itemize
Maximum support 640X480 and below resolution, configurable per frame size
 
\end_layout

\begin_layout Itemize
Support image input in YUV422 and RGB565 formats 
\end_layout

\begin_layout Itemize
Support for simultaneous output of images to the KPU and display: 
\end_layout

\begin_deeper
\begin_layout Itemize
The format of the output to the KPU is optional RGB888, or the Y component
 of the YUV422 input 
\end_layout

\begin_layout Itemize
The format of the output to the display is RGB565 
\end_layout

\end_deeper
\begin_layout Itemize
Can send an interrupt to the CPU when a frame start or one frame of image
 transfer is completed 
\end_layout

\begin_layout Subsection
Fast Fourier Transform Accelerator (FFT Accelerater) 
\end_layout

\begin_layout Standard
The FFT accelerator implements the base 2 time division of the FFT in hardware.
 
\end_layout

\begin_layout Itemize
Support multiple operation lengths, ie support 64 points, 128 points, 256
 points and 512 points 
\end_layout

\begin_layout Itemize
Supports two modes of operation, FFT and IFFT operations 
\end_layout

\begin_layout Itemize
Supports input data bit width, which supports 32-bit and 64-bit input 
\end_layout

\begin_layout Itemize
Supports the arrangement of input data that can be matched, that is, supports
 the imaginary part, the real part alternates, the pure real part, and the
 real and imaginary parts are separated.
 Column mode
\end_layout

\begin_layout Itemize
Support DMA transfer 
\end_layout

\begin_layout Subsection
Secure Hash Algorithm Accelerator (SHA256 Accelerater)
\end_layout

\begin_layout Standard
The SHA256 accelerator is the unit of computation used to calculate SHA-256:
\end_layout

\begin_layout Itemize
Support for SHA-256 calculations
\end_layout

\begin_layout Itemize
Support for DMA transfer of input data
\end_layout

\begin_layout Subsection
Universal Asynchronous Receiver Transmitter (UART)
\end_layout

\begin_layout Subsubsection
High speed UART:
\end_layout

\begin_layout Standard
High speed UART is UARTHS (UART0)
\end_layout

\begin_layout Itemize
Communication rate up to 5Mbps
\end_layout

\begin_layout Itemize
8 bytes transmit and receive FIFO 
\end_layout

\begin_layout Itemize
Programmable THRE interrupt 
\end_layout

\begin_layout Itemize
Does not support hardware flow control or other modem control signals, or
 synchronous serial data 
\end_layout

\begin_layout Subsubsection
General UART:
\end_layout

\begin_layout Standard
The general-purpose UART is UART1, UART2 and UART3, and supports asynchronous
 communication (RS232 and RS485 and IRDA, communication speed can reach
 5Mbps.
 The UART supports hardware management of CTS and RTS signals as well as
 software flow control (XON and XOFF).
 3 interfaces can be accessed by DMA Or the CPU directly accesses.
\end_layout

\begin_layout Itemize
• 8 bytes transmit and receive FIFO • 
\end_layout

\begin_layout Itemize
Asynchronous clock support 
\end_layout

\begin_deeper
\begin_layout Itemize
In order to cope with the CPU's baud rate requirement for data synchronization,
 the UART can configure the data clock separately.
 Full-duplex mode Can guarantee the synchronization of data in two clock
 domains
\end_layout

\end_deeper
\begin_layout Itemize
RS485 interface support 
\end_layout

\begin_deeper
\begin_layout Itemize
The UART can be configured in software programmable RS485 mode.
 The default is RS232 mode • 
\end_layout

\end_deeper
\begin_layout Itemize
Programmable THRE interrupt 
\end_layout

\begin_deeper
\begin_layout Itemize
Use THRE interrupt mode to improve serial port performance.
 When THRE mode and FIFO mode are selected, if there is less FIFO Threshold
 triggers THRE interrupt
\end_layout

\end_deeper
\begin_layout Subsection
Watchdog Timer (WDT)
\end_layout

\begin_layout Standard
The WDT is a slave peripheral to the APB and is part of the “synchronized
 hardware component design”.
 Has two WDTs, respectively WDT0, WDT1 Watchdog Timer mainly contains modules:
 
\end_layout

\begin_layout Itemize
One APB slave interface 
\end_layout

\begin_layout Itemize
A register module that synchronizes the current counter 
\end_layout

\begin_layout Itemize
An interrupt/system reset module and logic control circuit that decrements
 with the counter
\end_layout

\begin_layout Itemize
A synchronous clock domain to support asynchronous clock synchronization
 
\end_layout

\begin_layout Standard
The watchdog timer supports the following settings:
\end_layout

\begin_layout Itemize
APB bus width can be configured to 8, 16, and 32 bits 
\end_layout

\begin_layout Itemize
The clock counter is decremented from a set value to 0 to indicate the end
 of time 
\end_layout

\begin_layout Itemize
Optional external clock enable signal to control the counter's count rate
 
\end_layout

\begin_layout Itemize
One clock timeout, The WDT can perform the following tasks: –
\end_layout

\begin_deeper
\begin_layout Itemize
generate a system reset signal –
\end_layout

\begin_layout Itemize
first generate an interrupt, even if the bit has been cleared by the interrupt
 service, and second it will generate a system reset signal 
\end_layout

\end_deeper
\begin_layout Itemize
Duty cycle programmable 
\end_layout

\begin_layout Itemize
Programmable and hardware set counter start value 
\end_layout

\begin_layout Itemize
Counter retime protection
\end_layout

\begin_layout Itemize
Pause mode, only when the external pause signal is enabled
\end_layout

\begin_layout Itemize
WDT accidentally disable protection 
\end_layout

\begin_layout Itemize
Test mode for counter function testing (decrementing operation) 
\end_layout

\begin_layout Itemize
External asynchronous clock support.
 When this feature is enabled, a clock interrupt and a system reset signal
 will be generated, even if the APB bus clock In case of closure 
\end_layout

\begin_layout Subsection
General Purpose Input/Output Interface (GPIO) 
\end_layout

\begin_layout Subsubsection
High speed GPIO:
\end_layout

\begin_layout Standard
The high-speed GPIO is GPIOHS, a total of 32.
 Has the following characteristics:
\end_layout

\begin_layout Itemize
• Configurable input and output signals
\end_layout

\begin_layout Itemize
• Each IO has an independent interrupt source
\end_layout

\begin_layout Itemize
• Interrupt support edge trigger and level trigger
\end_layout

\begin_layout Itemize
• Each IO can be assigned to one of the 48 pins on the FPIOA
\end_layout

\begin_layout Itemize
Configurable up and down, or high resistance
\end_layout

\begin_layout Subsubsection
General GPIO:
\end_layout

\begin_layout Standard
There are 8 general-purpose GPIOs with the following characteristics:
\end_layout

\begin_layout Itemize
• 8 IOs use one interrupt source
\end_layout

\begin_layout Itemize
• Configurable input and output signals
\end_layout

\begin_layout Itemize
• Configurable Trigger IO Total Interrupt, Edge Trigger and Level Trigger
\end_layout

\begin_layout Itemize
• Each IO can be assigned to one of the 48 pins on the FPIOA
\end_layout

\begin_layout Itemize
Configurable up and down, or high resistance
\end_layout

\begin_layout Subsection
Direct Memory Access Controller (DMAC)
\end_layout

\begin_layout Standard
DMAC is highly configurable, highly programmable, and highly efficient in
 transferring data in bus mode.
 The DMAC controller has multiple hosts.
 Multi-channel and other features.
 DMAC has the following characteristics:
\end_layout

\begin_layout Itemize
• Memory-memory, memory-peripherals, peripheral-memory, peripheral-peripheral
 DMA transfers
\end_layout

\begin_layout Itemize
• Independent core, independent and slave independent clocks
\end_layout

\begin_layout Itemize
• The main interface can turn off its clock to save power when all peripherals
 are inactive
\end_layout

\begin_layout Itemize
• Up to eight channels, each with source and destination pairs
\end_layout

\begin_layout Itemize
• Each channel data can only be transmitted in one direction at a time,
 and different channels are not affected.
\end_layout

\begin_layout Itemize
• Input pin can dynamically select the size of the end system
\end_layout

\begin_layout Itemize
• Channel lock support, support for internal channel arbitration, use of
 the privileges of the main interface bus based on the priority of data
 transfer
\end_layout

\begin_layout Itemize
• DMAC status output, free/busy indication
\end_layout

\begin_layout Itemize
• DMA transfer is assigned to the transmission level, interrupted, transfer
 completed, etc.
\end_layout

\begin_layout Subsection
Integrated Circuit Built-in Bus (I2C)
\end_layout

\begin_layout Standard
The integrated circuit bus has three I2C bus interfaces.
 According to the user's configuration, the bus interface can be used as
 an I2C MASTER or SLAVE mode.
 formula.
 I2C interface support:
\end_layout

\begin_layout Itemize
Standard mode (0 to 100Kb/s)
\end_layout

\begin_layout Itemize
Fast mode (<= 400Kb/s)
\end_layout

\begin_layout Itemize
7-bit/10-bit addressing mode
\end_layout

\begin_layout Itemize
Batch transfer mode
\end_layout

\begin_layout Itemize
Interrupt or poll mode operation 
\end_layout

\begin_layout Subsection
Serial Peripheral Interface (SPI) 
\end_layout

\begin_layout Standard
The serial peripheral interface has 4 sets of SPI interfaces, of which SPI0,
 SPI1, and SPI3 can only work in MASTER mode, and SPI2 can only work in
\end_layout

\begin_layout Itemize
SLAVE mode, they have the following characteristics:
\end_layout

\begin_layout Itemize
Support 1/2/4/8 line full duplex mode
\end_layout

\begin_layout Itemize
SPI0, SPI1, SPI2 can support 25MHz clock (update to be tested)
\end_layout

\begin_layout Itemize
SPI3 supports up to 100MHz clock (update to be tested)
\end_layout

\begin_layout Itemize
Support for 32-bit wide, 32BYTE deep FIFO
\end_layout

\begin_layout Itemize
Independent mask interrupt - host conflict, transmit FIFO overflow, transmit
 FIFO empty, receive FIFO full, receive FIFO underflow, receive Receive
 FIFO overflow interrupts can be masked independently
\end_layout

\begin_layout Itemize
Support for DMA functions
\end_layout

\begin_layout Itemize
Support for dual-edge DDR transfer mode
\end_layout

\begin_layout Itemize
SPI3 supports XIP
\end_layout

\begin_layout Subsection
Integrated Circuit Built-in Audio Bus (I2S)
\end_layout

\begin_layout Standard
There are three integrated audio buses in the integrated circuit (I2S0,
 I2S1, and I2S2), all of which are MASTER modes.
 Where I2S0 supports configurable links Connect to the voice processing
 module to achieve voice enhancement and sound source orientation.
 Here are some common features:
\end_layout

\begin_layout Itemize
Bus width can be configured to 8, 16, and 32 bits
\end_layout

\begin_layout Itemize
Supports up to 4 stereo channels per interface
\end_layout

\begin_layout Itemize
Supports full-duplex communication due to the independence of the transmitter
 and receiver
\end_layout

\begin_layout Itemize
Asynchronous clock for APB bus and I2S SCLK
\end_layout

\begin_layout Itemize
Audio data resolution is 12, 16, 20, 24 and 32 bit
\end_layout

\begin_layout Itemize
The I2S0 transmit FIFO has a depth of 64 bytes, the receive is 8 bytes,
 and the transmit and receive FIFO depths of both I2S1 and I2S2 are 8 byte
\end_layout

\begin_layout Itemize
Support DMA transfer
\end_layout

\begin_layout Itemize
Programmable FIFO threshold
\end_layout

\begin_layout Subsection
Timer (TIMER)
\end_layout

\begin_layout Standard
The system has three TIMER modules with the following features:
\end_layout

\begin_layout Itemize
32-bit counter width
\end_layout

\begin_layout Itemize
Configurable up/down time base counter: increase or decrease
\end_layout

\begin_layout Itemize
Clock independent
\end_layout

\begin_layout Itemize
Configurable polarity for each interrupt
\end_layout

\begin_layout Itemize
Single or combined interrupt output flags are configurable
\end_layout

\begin_layout Itemize
Each timer has a read/write consistency register
\end_layout

\begin_layout Itemize
Timer switch output, switching whenever the timer counter is reloaded
\end_layout

\begin_layout Itemize
Pulse width modulation (PWM) of the timer switching output, 0% to 100% duty
 cycle 
\end_layout

\begin_layout Subsection
Read Only Memory (ROM)
\end_layout

\begin_layout Standard
The AXI ROM is responsible for copying the program from the SPI FLASH to
 the SRAM of the chip.
\end_layout

\begin_layout Itemize
Support firmware AES-128-CBC decryption
\end_layout

\begin_layout Itemize
Programs that support UOP mode to program FLASH
\end_layout

\begin_layout Itemize
Support firmware SHA256 integrity check tamper resistance
\end_layout

\begin_layout Itemize
Support UOP mode in OTP, SHA256 check, AES decryption
\end_layout

\begin_layout Itemize
Support for entering TURBO mode, allowing the chip and its peripherals to
 run at higher frequencies during startup 
\end_layout

\begin_layout Subsection
Real time clock (RTC)
\end_layout

\begin_layout Standard
The RTC is a unit for timing and has a timing function after the set time:
\end_layout

\begin_layout Itemize
Can be timed using an external high frequency crystal
\end_layout

\begin_layout Itemize
Configurable external crystal frequency and crossover
\end_layout

\begin_layout Itemize
Support perpetual calendar configuration, configurable items including century,
 year, month, day, hour, minute, second and week
\end_layout

\begin_layout Itemize
Can count in seconds and query current time
\end_layout

\begin_layout Itemize
Supports setting a set of alarms.
 The configurable items include year, month, day, hour, minute, and second.
 When the alarm arrives, the interrupt is triggered.
\end_layout

\begin_layout Itemize
Interrupt configurable to support daily, hourly, minute, and second trigger
 interrupts
\end_layout

\begin_layout Itemize
Readout counter count value less than 1 second, the smallest scale unit
 is the single period of the external crystal
\end_layout

\begin_layout Itemize
Data clear after power-on/reset
\end_layout

\begin_layout Subsection
Pulse Width Modulator (PWM)
\end_layout

\begin_layout Standard
The PWM is used to control the duty cycle of the pulse output.
 The user can configure the following functions of the PWM timer module:
\end_layout

\begin_layout Itemize
Control the frequency of events by specifying the PWM timer frequency or
 period
\end_layout

\begin_layout Itemize
Configuring a specific PWM timer to synchronize with other PWM timers or
 modules
\end_layout

\begin_layout Itemize
Make the PWM timer in phase with other PWM timers or modules
\end_layout

\begin_layout Itemize
Set the timer count mode: increment, decrement, or increment and decrement
 loop count mode
\end_layout

\begin_layout Itemize
Use the prescaler to change the rate of the PWM timer clock (PT_clk).
 Each timer has its own prescaler, passed Register PWM_TIMER0_CFG0_REG PWM_TIMER
x_PRESCALE configuration.
 The PWM timer is based on the setting of this register.
 Increase or decrease at a slower rate 
\end_layout

\begin_layout Section
Electrical characteristics
\end_layout

\begin_layout Standard
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Storage temperature range
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TSTR
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−40
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25
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150
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◦C
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</cell>
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Range of working temperature
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TOPR
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−40
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25
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125
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◦C
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\end_layout

\begin_layout Subsection
Programmable Drive Capability
\end_layout

\begin_layout Subsubsection*
Low level output current
\end_layout

\begin_layout Standard
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<features tabularvalignment="middle">
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DS[3:0]
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Min(mA)
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Typ(mA)
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Max(mA)
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0000
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3.2
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5.4
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8.3
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0001
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4.7
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8
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12.3
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0010
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6.3
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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\noun off
\color none
10.7
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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\noun off
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16.4
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<row>
<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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0011
\end_layout

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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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7.8
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13.2
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\noun off
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20.2
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<row>
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\begin_inset Text

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\color none
0100
\end_layout

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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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\noun off
\color none
9.4
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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\noun off
\color none
15.9
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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\emph off
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\uuline off
\uwave off
\noun off
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24.2
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<row>
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0101
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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10.9
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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18.4
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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\emph off
\bar no
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\noun off
\color none
28.1
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<row>
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0110
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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12.4
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20.9
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31.8
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<row>
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\color none
0111
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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13.9
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
\begin_inset Text

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23.4
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<cell alignment="center" valignment="top" bottomline="true" usebox="none">
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35.5
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</lyxtabular>

\end_inset


\end_layout

\begin_layout Subsubsection*
High level output current 
\end_layout

\begin_layout Standard
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<features tabularvalignment="middle">
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<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
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DS[3:0] 
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Min(mA) 
\end_layout

\end_inset
</cell>
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Typ(mA)
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 Max(mA) 
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<row>
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 0000
\end_layout

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5.0 
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7.6 
\end_layout

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11.2
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<row>
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0001
\end_layout

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7.5 
\end_layout

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11.4 
\end_layout

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16.8 
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0010
\end_layout

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10.0
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 15.2
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22.3 
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0011
\end_layout

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12.4 
\end_layout

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18.9
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27.8 
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<row>
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0100
\end_layout

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14.9 
\end_layout

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22.6
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 33.3 
\end_layout

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<row>
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0101
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17.4 
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26.3 
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38.7 
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0110
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19.8
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 30.0
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44.1 
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0111
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 22.3
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 33.7 
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49.5
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\begin_layout Section
Package information
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\end_body
\end_document