Skip to content

Instantly share code, notes, and snippets.

@qsimpleq

qsimpleq/AMD Phenom(tm) 9550 Quad-Core Processor

Last active July 14, 2016 13:20
Show Gist options
  • Save qsimpleq/78ed456a289f9cc418f69527298e3e9a to your computer and use it in GitHub Desktop.
Save qsimpleq/78ed456a289f9cc418f69527298e3e9a to your computer and use it in GitHub Desktop.
Download ZIP
dlang_cpuid
Raw
AMD Phenom(tm) 9550 Quad-Core Processor
################ Unified Information ################
Cores per CPU = 4
Threads per CPU = 4
------------------ TLB Information ------------------
Instruction TLB:
- - - - - ITLB1: - - - - - - - - - - - - - - - - - -
Page size = 4 KB
Pages count = 32
Pages count = 32
Associativity: Fully associative
Data TLB:
- - - - - DTLB1: - - - - - - - - - - - - - - - - - -
Page size = 4 KB
Pages count = 48
Pages count = 48
Associativity: Fully associative
- - - - - DTLB2: - - - - - - - - - - - - - - - - - -
Page size = 4 KB
Pages count = 128
Pages count = 128
Associativity: 2-way associative
Unified TLB:
----------------- Cache Information -----------------
Instruction Cache:
- - - - - ICache1: - - - - - - - - - - - - - - - - -
Cache size = 64 KB
Line = 64 bytes
Cores per cache = 1
Inclusive: false
Associativity: 2-way associative
Data Cache:
- - - - - DCache1: - - - - - - - - - - - - - - - - -
Cache size = 64 KB
Line = 64 bytes
Cores per cache = 1
Inclusive: false
Associativity: 2-way associative
Unified Cache:
- - - - - UCache1: - - - - - - - - - - - - - - - - -
Cache size = 512 KB
Line = 64 bytes
Cores per cache = 1
Inclusive: false
Associativity: 16-way associative
- - - - - UCache2: - - - - - - - - - - - - - - - - -
Cache size = 2048 KB
Line = 64 bytes
Cores per cache = 4
Inclusive: false
Associativity: 32-way associative
################## x86 Information ##################
vendor: AuthenticAMD
brand: AMD Phenom(tm) 9550 Quad-Core Processor
vendorIndex: 0x5
brandIndex: 0x0
maxBasicLeaf: 0x5
maxExtendedLeaf: 0x8000001A
clflushLineSize: 0x8
maxLogicalProcessors: 0x4
initialAPIC: 0x2
stepping: 0x3
model: 0x2
family: 0xF
type: 0x0
extendedModel: 0x0
extendedFamily: 0x1
sse3: true
pclmulqdq: false
dtes64: false
monitor: true
ds_cpl: false
vmx: false
smx: false
eist: false
tm2: false
ssse3: false
cnxt_id: false
sdbg: false
fma: false
cmpxchg16b: true
xtpr: false
pdcm: false
pcid: false
dca: false
sse41: false
sse42: false
x2apic: false
movbe: false
popcnt: true
tsc_deadline: false
aes: false
xsave: false
osxsave: false
avx: false
f16c: false
rdrand: false
fpu: true
vme: true
de: true
pse: true
tsc: true
msr: true
pae: true
mce: true
cx8: true
apic: true
sep: true
mtrr: true
pge: true
mca: true
cmov: true
pat: true
pse36: true
psn: false
clfsh: true
ds: false
acpi: false
mmx: true
fxsr: true
sse: true
sse2: true
ss: false
htt: true
tm: false
pbe: false
Raw
Intel(R) Core(TM)2 CPU 4400 @ 2.00GHz
################ Unified Information ################
Cores per CPU = 1
Threads per CPU = 2
------------------ TLB Information ------------------
Instruction TLB:
- - - - - ITLB1: - - - - - - - - - - - - - - - - - -
Page size = 4 KB
Pages count = 128
Pages count = 128
Associativity: 4-way associative
Data TLB:
- - - - - DTLB1: - - - - - - - - - - - - - - - - - -
Page size = 4 KB
Pages count = 16
Pages count = 16
Associativity: 4-way associative
- - - - - DTLB2: - - - - - - - - - - - - - - - - - -
Page size = 4 KB
Pages count = 256
Pages count = 256
Associativity: 4-way associative
Unified TLB:
----------------- Cache Information -----------------
Instruction Cache:
- - - - - ICache1: - - - - - - - - - - - - - - - - -
Cache size = 32 KB
Line = 64 bytes
Cores per cache = 1
Inclusive: false
Associativity: 8-way associative
Data Cache:
- - - - - DCache1: - - - - - - - - - - - - - - - - -
Cache size = 32 KB
Line = 64 bytes
Cores per cache = 1
Inclusive: false
Associativity: 8-way associative
Unified Cache:
- - - - - UCache1: - - - - - - - - - - - - - - - - -
Cache size = 2048 KB
Line = 64 bytes
Cores per cache = 1
Inclusive: false
Associativity: 8-way associative
################## x86 Information ##################
vendor: GenuineIntel
brand: Intel(R) Core(TM)2 CPU 4400 @ 2.00GHz
vendorIndex: 0x8
brandIndex: 0x0
maxBasicLeaf: 0xA
maxExtendedLeaf: 0x80000008
clflushLineSize: 0x8
maxLogicalProcessors: 0x2
initialAPIC: 0x1
stepping: 0x2
model: 0xF
family: 0x6
type: 0x0
extendedModel: 0x0
extendedFamily: 0x0
sse3: true
pclmulqdq: false
dtes64: true
monitor: true
ds_cpl: true
vmx: false
smx: false
eist: true
tm2: true
ssse3: true
cnxt_id: false
sdbg: false
fma: false
cmpxchg16b: true
xtpr: true
pdcm: true
pcid: false
dca: false
sse41: false
sse42: false
x2apic: false
movbe: false
popcnt: false
tsc_deadline: false
aes: false
xsave: false
osxsave: false
avx: false
f16c: false
rdrand: false
fpu: true
vme: true
de: true
pse: true
tsc: true
msr: true
pae: true
mce: true
cx8: true
apic: true
sep: true
mtrr: true
pge: true
mca: true
cmov: true
pat: true
pse36: true
psn: false
clfsh: true
ds: true
acpi: true
mmx: true
fxsr: true
sse: true
sse2: true
ss: true
htt: true
tm: true
pbe: true
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment