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@rafaelcorsi
Created December 9, 2017 12:16
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# Rafael Corsi @ insper.edu.br
# Dez/2017
# Disciplina Elementos de Sistemas
#
# Convert program memmory to altera mif file
# that can be used to load FPGA and to Simulate (modelsim)
# http://quartushelp.altera.com/13.0/mergedProjects/reference/glossary/def_mif.htm
#
# TODO:
import os
import argparse
TAB = " "
END = "\n"
def toMIF(mem, mif):
cnt = 0
try :
fw = open(mif,"w")
fr = open(mem,"r")
fw.write("-- Elementos de Sistema - INSPER.edu.br"+END)
fw.write("-- Rafael Corsi"+END)
fw.write("-- File generated by toMIF.py"+END)
fw.write("-- originated from"+mem+""+END)
fw.write("-- to be used on ALTERA FPGAs\r\n"+END)
fw.write("WIDTH=16;"+END)
fw.write("DEPTH=30;"+END)
fw.write(""+END)
fw.write("ADDRESS_RADIX=UNS;"+END)
fw.write("DATA_RADIX=BIN;"+END)
fw.write(""+END)
fw.write("CONTENT BEGIN"+END)
for line in fr:
fw.write( TAB
+ '{:4d}'.format(cnt)
+" : "
+line.rstrip()
+";"
+""+END)
cnt = cnt + 1
# colocar for aqui
fw.write("END;"+END)
fw.close()
fr.close()
except IOError:
print("Arquivo não encontrado")
if __name__ == "__main__":
ap = argparse.ArgumentParser()
ap.add_argument("-i", "--in_mem_mif" , required=True, help="arquivo de entrada memoria")
ap.add_argument("-o", "--out_mif" , required=True, help="arquivo de saida mif para Altera")
args = vars(ap.parse_args())
root = os.getcwd()
toMIF(mem=args["in_mem_mif"], mif=args["out_mif"])
@rafaelcorsi
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Input example

0001000000010000
1110110000010000
0100000000000000
1110000010010000
0000000000000001
1110001100001000
0000000000010000
1110110000010000
0000000000010000
1110001100001000
0000000000000001
1111110000100000
1110111010001000
0000000000010100
1110110000010000
0000000000000001
1111110000100000
1110000010010000
0000000000000001
1110001100001000
0000000000010000
1111110000010000
1110001110010000
1110001100001000
0000000000001010
1110001100000101
1110101010000000
0000000000011011
1110001100000111
1110101010000000

@rafaelcorsi
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OutPut file

-- Elementos de Sistema - INSPER.edu.br
-- Rafael Corsi
-- File generated by toMIF.py
-- originated fromin/Abs0.bin
-- to be used on ALTERA FPGAs

WIDTH=16;
DEPTH=30;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
       0 : 0001000000010000;
       1 : 1110110000010000;
       2 : 0100000000000000;
       3 : 1110000010010000;
       4 : 0000000000000001;
       5 : 1110001100001000;
       6 : 0000000000010000;
       7 : 1110110000010000;
       8 : 0000000000010000;
       9 : 1110001100001000;
      10 : 0000000000000001;
      11 : 1111110000100000;
      12 : 1110111010001000;
      13 : 0000000000010100;
      14 : 1110110000010000;
      15 : 0000000000000001;
      16 : 1111110000100000;
      17 : 1110000010010000;
      18 : 0000000000000001;
      19 : 1110001100001000;
      20 : 0000000000010000;
      21 : 1111110000010000;
      22 : 1110001110010000;
      23 : 1110001100001000;
      24 : 0000000000001010;
      25 : 1110001100000101;
      26 : 1110101010000000;
      27 : 0000000000011011;
      28 : 1110001100000111;
      29 : 1110101010000000;
END;

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