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November 2, 2024 12:45
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Netcup VM cpuid
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| $ cpuid | |
| CPU 0: | |
| vendor_id = "GenuineIntel" | |
| version information (1/eax): | |
| processor type = primary processor (0) | |
| family = 0xf (15) | |
| model = 0xb (11) | |
| stepping id = 0x1 (1) | |
| extended family = 0x0 (0) | |
| extended model = 0x6 (6) | |
| (family synth) = 0xf (15) | |
| (model synth) = 0x6b (107) | |
| miscellaneous (1/ebx): | |
| process local APIC physical ID = 0x0 (0) | |
| maximum IDs for CPUs in pkg = 0x0 (0) | |
| CLFLUSH line size = 0x8 (8) | |
| brand index = 0x0 (0) | |
| brand id = 0x00 (0): unknown | |
| feature information (1/edx): | |
| x87 FPU on chip = true | |
| VME: virtual-8086 mode enhancement = false | |
| DE: debugging extensions = true | |
| PSE: page size extensions = true | |
| TSC: time stamp counter = true | |
| RDMSR and WRMSR support = true | |
| PAE: physical address extensions = true | |
| MCE: machine check exception = true | |
| CMPXCHG8B inst. = true | |
| APIC on chip = true | |
| SYSENTER and SYSEXIT = true | |
| MTRR: memory type range registers = true | |
| PTE global bit = true | |
| MCA: machine check architecture = true | |
| CMOV: conditional move/compare instr = true | |
| PAT: page attribute table = true | |
| PSE-36: page size extension = true | |
| PSN: processor serial number = false | |
| CLFLUSH instruction = true | |
| DS: debug store = false | |
| ACPI: thermal monitor and clock ctrl = false | |
| MMX Technology = true | |
| FXSAVE/FXRSTOR = true | |
| SSE extensions = true | |
| SSE2 extensions = true | |
| SS: self snoop = false | |
| hyper-threading / multi-core supported = false | |
| TM: therm. monitor = false | |
| IA64 = false | |
| PBE: pending break event = false | |
| feature information (1/ecx): | |
| PNI/SSE3: Prescott New Instructions = true | |
| PCLMULDQ instruction = true | |
| DTES64: 64-bit debug store = false | |
| MONITOR/MWAIT = false | |
| CPL-qualified debug store = false | |
| VMX: virtual machine extensions = false | |
| SMX: safer mode extensions = false | |
| Enhanced Intel SpeedStep Technology = false | |
| TM2: thermal monitor 2 = false | |
| SSSE3 extensions = true | |
| context ID: adaptive or shared L1 data = false | |
| SDBG: IA32_DEBUG_INTERFACE = false | |
| FMA instruction = false | |
| CMPXCHG16B instruction = true | |
| xTPR disable = false | |
| PDCM: perfmon and debug = false | |
| PCID: process context identifiers = true | |
| DCA: direct cache access = false | |
| SSE4.1 extensions = true | |
| SSE4.2 extensions = true | |
| x2APIC: extended xAPIC support = true | |
| MOVBE instruction = false | |
| POPCNT instruction = true | |
| time stamp counter deadline = false | |
| AES instruction = true | |
| XSAVE/XSTOR states = true | |
| OS-enabled XSAVE/XSTOR = true | |
| AVX: advanced vector extensions = false | |
| F16C half-precision convert instruction = false | |
| RDRAND instruction = true | |
| hypervisor guest status = true | |
| cache and TLB information (2): | |
| 0x4d: L3 cache: 16M, 16-way, 64 byte lines | |
| 0x7d: L2 cache: 2M, 8-way, 64 byte lines | |
| 0x30: L1 cache: 32K, 8-way, 64 byte lines | |
| 0x2c: L1 data cache: 32K, 8-way, 64 byte lines | |
| processor serial number = 0006-0FB1-0000-0000-0000-0000 | |
| deterministic cache parameters (4): | |
| --- cache 0 --- | |
| cache type = data cache (1) | |
| cache level = 0x1 (1) | |
| self-initializing cache level = true | |
| fully associative cache = false | |
| maximum IDs for CPUs sharing cache = 0x0 (0) | |
| maximum IDs for cores in pkg = 0x0 (0) | |
| system coherency line size = 0x40 (64) | |
| physical line partitions = 0x1 (1) | |
| ways of associativity = 0x8 (8) | |
| number of sets = 0x40 (64) | |
| WBINVD/INVD acts on lower caches = true | |
| inclusive to lower caches = false | |
| complex cache indexing = false | |
| number of sets (s) = 64 | |
| (size synth) = 32768 (32 KB) | |
| --- cache 1 --- | |
| cache type = instruction cache (2) | |
| cache level = 0x1 (1) | |
| self-initializing cache level = true | |
| fully associative cache = false | |
| maximum IDs for CPUs sharing cache = 0x0 (0) | |
| maximum IDs for cores in pkg = 0x0 (0) | |
| system coherency line size = 0x40 (64) | |
| physical line partitions = 0x1 (1) | |
| ways of associativity = 0x8 (8) | |
| number of sets = 0x40 (64) | |
| WBINVD/INVD acts on lower caches = true | |
| inclusive to lower caches = false | |
| complex cache indexing = false | |
| number of sets (s) = 64 | |
| (size synth) = 32768 (32 KB) | |
| --- cache 2 --- | |
| cache type = unified cache (3) | |
| cache level = 0x2 (2) | |
| self-initializing cache level = true | |
| fully associative cache = false | |
| maximum IDs for CPUs sharing cache = 0x0 (0) | |
| maximum IDs for cores in pkg = 0x0 (0) | |
| system coherency line size = 0x40 (64) | |
| physical line partitions = 0x1 (1) | |
| ways of associativity = 0x10 (16) | |
| number of sets = 0x1000 (4096) | |
| WBINVD/INVD acts on lower caches = true | |
| inclusive to lower caches = false | |
| complex cache indexing = false | |
| number of sets (s) = 4096 | |
| (size synth) = 4194304 (4 MB) | |
| --- cache 3 --- | |
| cache type = unified cache (3) | |
| cache level = 0x3 (3) | |
| self-initializing cache level = true | |
| fully associative cache = false | |
| maximum IDs for CPUs sharing cache = 0x0 (0) | |
| maximum IDs for cores in pkg = 0x0 (0) | |
| system coherency line size = 0x40 (64) | |
| physical line partitions = 0x1 (1) | |
| ways of associativity = 0x10 (16) | |
| number of sets = 0x4000 (16384) | |
| WBINVD/INVD acts on lower caches = false | |
| inclusive to lower caches = true | |
| complex cache indexing = true | |
| number of sets (s) = 16384 | |
| (size synth) = 16777216 (16 MB) | |
| --- cache 4 --- | |
| cache type = no more caches (0) | |
| MONITOR/MWAIT (5): | |
| smallest monitor-line size (bytes) = 0x0 (0) | |
| largest monitor-line size (bytes) = 0x0 (0) | |
| enum of Monitor-MWAIT exts supported = true | |
| supports intrs as break-event for MWAIT = true | |
| monitorless MWAIT supported = false | |
| number of C0 sub C-states using MWAIT = 0x0 (0) | |
| number of C1 sub C-states using MWAIT = 0x0 (0) | |
| number of C2 sub C-states using MWAIT = 0x0 (0) | |
| number of C3 sub C-states using MWAIT = 0x0 (0) | |
| number of C4 sub C-states using MWAIT = 0x0 (0) | |
| number of C5 sub C-states using MWAIT = 0x0 (0) | |
| number of C6 sub C-states using MWAIT = 0x0 (0) | |
| number of C7 sub C-states using MWAIT = 0x0 (0) | |
| Thermal and Power Management Features (6): | |
| digital thermometer = false | |
| Intel Turbo Boost Technology = false | |
| ARAT always running APIC timer = false | |
| PLN power limit notification = false | |
| ECMD extended clock modulation duty = false | |
| PTM package thermal management = false | |
| HWP base registers = false | |
| HWP notification = false | |
| HWP activity window = false | |
| HWP energy performance preference = false | |
| HWP package level request = false | |
| HDC base registers = false | |
| Intel Turbo Boost Max Technology 3.0 = false | |
| HWP capabilities = false | |
| HWP PECI override = false | |
| flexible HWP = false | |
| IA32_HWP_REQUEST MSR fast access mode = false | |
| HW_FEEDBACK MSRs supported = false | |
| ignoring idle logical processor HWP req = false | |
| Thread Director = false | |
| IA32_HW_FEEDBACK_THREAD_CONFIG bit 25 = false | |
| digital thermometer thresholds = 0x0 (0) | |
| hardware coordination feedback = false | |
| ACNT2 available = false | |
| performance-energy bias capability = false | |
| number of enh hardware feedback classes = 0x0 (0) | |
| performance capability reporting = false | |
| energy efficiency capability reporting = false | |
| size of feedback struct (4KB pages) = 0x1 (1) | |
| index of CPU's row in feedback struct = 0x0 (0) | |
| extended feature flags (7): | |
| FSGSBASE instructions = false | |
| IA32_TSC_ADJUST MSR supported = false | |
| SGX: Software Guard Extensions supported = false | |
| BMI1 instructions = false | |
| HLE hardware lock elision = false | |
| AVX2: advanced vector extensions 2 = false | |
| FDP_EXCPTN_ONLY = false | |
| SMEP supervisor mode exec protection = false | |
| BMI2 instructions = false | |
| enhanced REP MOVSB/STOSB = false | |
| INVPCID instruction = true | |
| RTM: restricted transactional memory = false | |
| RDT-CMT/PQoS cache monitoring = false | |
| deprecated FPU CS/DS = false | |
| MPX: intel memory protection extensions = false | |
| RDT-CAT/PQE cache allocation = false | |
| AVX512F: AVX-512 foundation instructions = false | |
| AVX512DQ: double & quadword instructions = false | |
| RDSEED instruction = false | |
| ADX instructions = false | |
| SMAP: supervisor mode access prevention = false | |
| AVX512IFMA: integer fused multiply add = false | |
| PCOMMIT instruction = false | |
| CLFLUSHOPT instruction = false | |
| CLWB instruction = false | |
| Intel processor trace = false | |
| AVX512PF: prefetch instructions = false | |
| AVX512ER: exponent & reciprocal instrs = false | |
| AVX512CD: conflict detection instrs = false | |
| SHA instructions = false | |
| AVX512BW: byte & word instructions = false | |
| AVX512VL: vector length = false | |
| PREFETCHWT1 = false | |
| AVX512VBMI: vector byte manipulation = false | |
| UMIP: user-mode instruction prevention = false | |
| PKU protection keys for user-mode = false | |
| OSPKE CR4.PKE and RDPKRU/WRPKRU = false | |
| WAITPKG instructions = false | |
| AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false | |
| CET_SS: CET shadow stack = false | |
| GFNI: Galois Field New Instructions = false | |
| VAES instructions = false | |
| VPCLMULQDQ instruction = false | |
| AVX512_VNNI: neural network instructions = false | |
| AVX512_BITALG: bit count/shiffle = false | |
| TME: Total Memory Encryption = false | |
| AVX512: VPOPCNTDQ instruction = false | |
| LA57: 57-bit addrs & 5-level paging = false | |
| BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) | |
| RDPID: read processor ID supported = false | |
| KL: key locker = false | |
| bus lock detection = false | |
| CLDEMOTE supports cache line demote = false | |
| MOVDIRI instruction = false | |
| MOVDIR64B instruction = false | |
| ENQCMD instruction = false | |
| SGX_LC: SGX launch config supported = false | |
| PKS: supervisor protection keys = false | |
| SGX-KEYS: SGX attestation services = false | |
| AVX512_4VNNIW: neural network instrs = false | |
| AVX512_4FMAPS: multiply acc single prec = false | |
| fast short REP MOV = false | |
| UINTR: user interrupts = false | |
| AVX512_VP2INTERSECT: intersect mask regs = false | |
| IA32_MCU_OPT_CTRL SRBDS mitigation MSR = false | |
| VERW MD_CLEAR microcode support = true | |
| RTM transaction always aborts = false | |
| IA32_TSX_FORCE_ABORT MSR = false | |
| SERIALIZE instruction = false | |
| hybrid part = false | |
| TSXLDTRK: TSX suspend load addr tracking = false | |
| PCONFIG instruction = false | |
| LBR: architectural last branch records = false | |
| CET_IBT: CET indirect branch tracking = false | |
| AMX-BF16: tile bfloat16 support = false | |
| AVX512_FP16: fp16 support = false | |
| AMX-TILE: tile architecture support = false | |
| AMX-INT8: tile 8-bit integer support = false | |
| IBRS/IBPB: indirect branch restrictions = true | |
| STIBP: 1 thr indirect branch predictor = false | |
| L1D_FLUSH: IA32_FLUSH_CMD MSR = false | |
| IA32_ARCH_CAPABILITIES MSR = true | |
| IA32_CORE_CAPABILITIES MSR = false | |
| SSBD: speculative store bypass disable = true | |
| Direct Cache Access Parameters (9): | |
| PLATFORM_DCA_CAP MSR bits = 0 | |
| Architecture Performance Monitoring Features (0xa): | |
| version ID = 0x0 (0) | |
| number of counters per logical processor = 0x0 (0) | |
| bit width of counter = 0x0 (0) | |
| length of EBX bit vector = 0x0 (0) | |
| core cycle event = not available | |
| instruction retired event = not available | |
| reference cycles event = not available | |
| last-level cache ref event = not available | |
| last-level cache miss event = not available | |
| branch inst retired event = not available | |
| branch mispred retired event = not available | |
| topdown slots event = not available | |
| topdown backend bound = not available | |
| topdown bad speculation = not available | |
| topdown frontend bound = not available | |
| topdown retiring = not available | |
| LBR inserts = not available | |
| fixed counter 0 supported = false | |
| fixed counter 1 supported = false | |
| fixed counter 2 supported = false | |
| fixed counter 3 supported = false | |
| fixed counter 4 supported = false | |
| fixed counter 5 supported = false | |
| fixed counter 6 supported = false | |
| fixed counter 7 supported = false | |
| fixed counter 8 supported = false | |
| fixed counter 9 supported = false | |
| fixed counter 10 supported = false | |
| fixed counter 11 supported = false | |
| fixed counter 12 supported = false | |
| fixed counter 13 supported = false | |
| fixed counter 14 supported = false | |
| fixed counter 15 supported = false | |
| fixed counter 16 supported = false | |
| fixed counter 17 supported = false | |
| fixed counter 18 supported = false | |
| fixed counter 19 supported = false | |
| fixed counter 20 supported = false | |
| fixed counter 21 supported = false | |
| fixed counter 22 supported = false | |
| fixed counter 23 supported = false | |
| fixed counter 24 supported = false | |
| fixed counter 25 supported = false | |
| fixed counter 26 supported = false | |
| fixed counter 27 supported = false | |
| fixed counter 28 supported = false | |
| fixed counter 29 supported = false | |
| fixed counter 30 supported = false | |
| fixed counter 31 supported = false | |
| number of contiguous fixed counters = 0x0 (0) | |
| bit width of fixed counters = 0x0 (0) | |
| anythread deprecation = false | |
| x2APIC features / processor topology (0xb): | |
| extended APIC ID = 0 | |
| --- level 0 --- | |
| level number = 0x0 (0) | |
| level type = thread (1) | |
| bit width of level & previous levels = 0x0 (0) | |
| number of logical processors at level = 0x1 (1) | |
| --- level 1 --- | |
| level number = 0x1 (1) | |
| level type = core (2) | |
| bit width of level & previous levels = 0x0 (0) | |
| number of logical processors at level = 0x1 (1) | |
| --- level 2 --- | |
| level number = 0x2 (2) | |
| level type = invalid (0) | |
| bit width of level & previous levels = 0x0 (0) | |
| number of logical processors at level = 0x0 (0) | |
| XSAVE features (0xd/0): | |
| XCR0 valid bit field mask = 0x0000000000000003 | |
| x87 state = true | |
| SSE state = true | |
| AVX state = false | |
| MPX BNDREGS = false | |
| MPX BNDCSR = false | |
| AVX-512 opmask = false | |
| AVX-512 ZMM_Hi256 = false | |
| AVX-512 Hi16_ZMM = false | |
| PKRU state = false | |
| XTILECFG state = false | |
| XTILEDATA state = false | |
| bytes required by fields in XCR0 = 0x00000240 (576) | |
| bytes required by XSAVE/XRSTOR area = 0x00000240 (576) | |
| XSAVEOPT instruction = false | |
| XSAVEC instruction = false | |
| XGETBV instruction = false | |
| XSAVES/XRSTORS instructions = false | |
| XFD: extended feature disable supported = false | |
| SAVE area size in bytes = 0x00000000 (0) | |
| IA32_XSS valid bit field mask = 0x0000000000000000 | |
| PT state = false | |
| PASID state = false | |
| CET_U user state = false | |
| CET_S supervisor state = false | |
| HDC state = false | |
| UINTR state = false | |
| LBR state = false | |
| HWP state = false | |
| hypervisor_id (0x40000000) = "KVMKVMKVM\0\0\0" | |
| hypervisor features (0x40000001/eax): | |
| kvmclock available at MSR 0x11 = true | |
| delays unnecessary for PIO ops = true | |
| mmu_op = false | |
| kvmclock available at MSR 0x4b564d00 = true | |
| async pf enable available by MSR = true | |
| steal clock supported = true | |
| guest EOI optimization enabled = true | |
| guest spinlock optimization enabled = false | |
| guest TLB flush optimization enabled = false | |
| async PF VM exit enable available by MSR = false | |
| guest send IPI optimization enabled = false | |
| host HLT poll disable at MSR 0x4b564d05 = false | |
| guest sched yield optimization enabled = false | |
| guest uses intrs for page ready APF evs = false | |
| extended destination ID = false | |
| map gpa range hypercall supported = false | |
| MSR_KVM_MIGRATION_CONTROL supported = false | |
| stable: no guest per-cpu warps expected = true | |
| hypervisor features (0x40000001/edx): | |
| realtime hint: no unbound preemption = false | |
| hypervisor_id (0x40000100) = "@\2\0\0@\2\0\0\0\0\0\0" | |
| extended feature flags (0x80000001/edx): | |
| SYSCALL and SYSRET instructions = true | |
| execution disable = true | |
| 1-GB large page support = false | |
| RDTSCP = false | |
| 64-bit extensions technology available = true | |
| Intel feature flags (0x80000001/ecx): | |
| LAHF/SAHF supported in 64-bit mode = true | |
| LZCNT advanced bit manipulation = true | |
| 3DNow! PREFETCH/PREFETCHW instructions = false | |
| brand = "QEMU Virtual CPU version 2.5+" | |
| L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): | |
| instruction # entries = 0xff (255) | |
| instruction associativity = 0x1 (1) | |
| data # entries = 0xff (255) | |
| data associativity = 0x1 (1) | |
| L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): | |
| instruction # entries = 0xff (255) | |
| instruction associativity = 0x1 (1) | |
| data # entries = 0xff (255) | |
| data associativity = 0x1 (1) | |
| L1 data cache information (0x80000005/ecx): | |
| line size (bytes) = 0x40 (64) | |
| lines per tag = 0x1 (1) | |
| associativity = 0x2 (2) | |
| size (KB) = 0x40 (64) | |
| L1 instruction cache information (0x80000005/edx): | |
| line size (bytes) = 0x40 (64) | |
| lines per tag = 0x1 (1) | |
| associativity = 0x2 (2) | |
| size (KB) = 0x40 (64) | |
| L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): | |
| instruction # entries = 0x0 (0) | |
| instruction associativity = L2 off (0) | |
| data # entries = 0x0 (0) | |
| data associativity = L2 off (0) | |
| L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): | |
| instruction # entries = 0x200 (512) | |
| instruction associativity = 4 to 5-way (4) | |
| data # entries = 0x200 (512) | |
| data associativity = 4 to 5-way (4) | |
| L2 unified cache information (0x80000006/ecx): | |
| line size (bytes) = 0x40 (64) | |
| lines per tag = 0x1 (1) | |
| associativity = 16 to 31-way (8) | |
| size (KB) = 0x200 (512) | |
| L3 cache information (0x80000006/edx): | |
| line size (bytes) = 0x40 (64) | |
| lines per tag = 0x1 (1) | |
| associativity = 16 to 31-way (8) | |
| size (in 512KB units) = 0x20 (32) | |
| RAS Capability (0x80000007/ebx): | |
| MCA overflow recovery support = false | |
| SUCCOR support = false | |
| HWA: hardware assert support = false | |
| scalable MCA support = false | |
| Advanced Power Management Features (0x80000007/ecx): | |
| CmpUnitPwrSampleTimeRatio = 0x0 (0) | |
| Advanced Power Management Features (0x80000007/edx): | |
| TS: temperature sensing diode = false | |
| FID: frequency ID control = false | |
| VID: voltage ID control = false | |
| TTP: thermal trip = false | |
| TM: thermal monitor = false | |
| STC: software thermal control = false | |
| 100 MHz multiplier control = false | |
| hardware P-State control = false | |
| TscInvariant = false | |
| CPB: core performance boost = false | |
| read-only effective frequency interface = false | |
| processor feedback interface = false | |
| APM power reporting = false | |
| connected standby = false | |
| RAPL: running average power limit = false | |
| Physical Address and Linear Address Size (0x80000008/eax): | |
| maximum physical address bits = 0x28 (40) | |
| maximum linear (virtual) address bits = 0x30 (48) | |
| maximum guest physical address bits = 0x0 (0) | |
| Extended Feature Extensions ID (0x80000008/ebx): | |
| CLZERO instruction = false | |
| instructions retired count support = false | |
| always save/restore error pointers = false | |
| INVLPGB instruction = false | |
| RDPRU instruction = false | |
| memory bandwidth enforcement = false | |
| MCOMMIT instruction = false | |
| WBNOINVD instruction = false | |
| IBPB: indirect branch prediction barrier = false | |
| interruptible WBINVD, WBNOINVD = false | |
| IBRS: indirect branch restr speculation = false | |
| STIBP: 1 thr indirect branch predictor = false | |
| CPU prefers: IBRS always on = false | |
| CPU prefers: STIBP always on = false | |
| IBRS preferred over software solution = false | |
| IBRS provides same mode protection = false | |
| EFER[LMSLE] not supported = false | |
| INVLPGB supports TLB flush guest nested = false | |
| ppin processor id number supported = false | |
| SSBD: speculative store bypass disable = true | |
| virtualized SSBD = false | |
| SSBD fixed in hardware = false | |
| CPPC: collaborative processor perf ctrl = false | |
| PSFD: predictive store forward disable = false | |
| not vulnerable to branch type confusion = false | |
| IBPB_RET: ret addr predictor cleared = false | |
| branch sampling feature support = false | |
| (vuln to branch type confusion synth) = true | |
| Size Identifiers (0x80000008/ecx): | |
| number of CPU cores = 0x1 (1) | |
| ApicIdCoreIdSize = 0x0 (0) | |
| performance time-stamp counter size = 40 bits (0) | |
| Feature Extended Size (0x80000008/edx): | |
| max page count for INVLPGB instruction = 0x0 (0) | |
| RDPRU instruction max input support = 0x0 (0) | |
| SVM Secure Virtual Machine (0x8000000a/eax): | |
| SvmRev: SVM revision = 0x0 (0) | |
| SVM Secure Virtual Machine (0x8000000a/edx): | |
| nested paging = false | |
| LBR virtualization = false | |
| SVM lock = false | |
| NRIP save = false | |
| MSR based TSC rate control = false | |
| VMCB clean bits support = false | |
| flush by ASID = false | |
| decode assists = false | |
| SSSE3/SSE5 opcode set disable = false | |
| pause intercept filter = false | |
| pause filter threshold = false | |
| AVIC: AMD virtual interrupt controller = false | |
| virtualized VMLOAD/VMSAVE = false | |
| virtualized global interrupt flag (GIF) = false | |
| GMET: guest mode execute trap = false | |
| X2AVIC: virtualized X2APIC = false | |
| supervisor shadow stack = false | |
| guest Spec_ctl support = false | |
| ROGPT: read-only guest page table = false | |
| host MCE override = false | |
| INVLPGB/TLBSYNC hyperv interc enable = false | |
| VNMI: NMI virtualization = false | |
| IBS virtualization = false | |
| extended LVT AVIC access changes = false | |
| guest VMCB addr check = false | |
| bus lock threshold = false | |
| NASID: number of address space identifiers = 0x0 (0): | |
| (instruction supported synth): | |
| MWAIT = false | |
| (multi-processing synth) = none | |
| (multi-processing method) = Intel leaf 0xb | |
| (APIC widths synth): CORE_width=0 SMT_width=0 | |
| (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0 | |
| (uarch synth) = Intel {Netburst} | |
| (synth) = Intel Pentium 4 / Pentium D / Xeon / Xeon MP / Celeron / Celeron D (unknown model) {Netburst} |
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