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@ravijain056
Created June 9, 2016 18:04
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from myhdl import Signal, block, always_seq, instance, delay
@block
def deadlock(): # not convertible
sig1 = Signal(bool(0))
@instance
def initialpush():
yield delay(10)
sig1.next = True
@always_seq(sig1.posedge, reset=None)
def posdriver():
sig1.next = not sig1
@always_seq(sig1.negedge, reset=None)
def negdriver():
sig1.next = not sig1
return initialpush, posdriver, negdriver
dlinst = deadlock()
dlinst.config_sim(trace=True)
dlinst.run_sim(duration=100)
@block
def deadlock2(): # can be convertible
sig1 = Signal(bool(0))
sig2 = Signal(bool(0))
sig3 = Signal(bool(0))
@instance
def initialpush():
while True:
yield delay(10)
sig1.next = True
@always_seq(sig1.posedge, reset=None)
def posdriver():
sig1.next = not sig1
sig2.next = sig1
@always_seq(sig1.negedge, reset=None)
def negdriver():
sig3.next = sig1
return initialpush, posdriver, negdriver
dlinst2 = deadlock2()
dlinst2.config_sim(trace=True)
dlinst2.run_sim(duration=100)
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