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from myhdl import block, always_seq, always_comb, Signal, intbv, enum,\ | |
ResetSignal | |
from gemac.crc32 import crc32 | |
txstate = enum('IDLE', 'PREAMBLE', 'SFD', 'FIRSTBYTE', 'INFRAME', 'PADDING', | |
'ERROR', 'CRC1', 'CRC2', 'CRC3', 'CRC4', 'SENDPAUSE') | |
@block | |
def txengine(txclientintf, txgmii_intf, txflowintf, txconfig, sysreset): | |
state = Signal(txstate.IDLE) | |
curbyte = Signal(intbv(1, min=0, max=10000)) | |
pausereq = Signal(bool(0)) | |
reset = ResetSignal(0, active=0, async=True) | |
ifgwait = Signal(intbv(0)[16:]) | |
data = Signal(intbv(0)[8:]) | |
dv = Signal(bool(0)) | |
clearcrc = Signal(bool(0)) | |
calccrc = Signal(bool(0)) | |
crcout = Signal(intbv(0xFFFFFFFF)[32:]) | |
crc32inst = crc32(txclientintf.clk, clearcrc, calccrc, data, crcout, reset) | |
@always_comb | |
def assign(): | |
txgmii_intf.clk.next = txclientintf.clk | |
txclientintf.ack.next = state == txstate.FIRSTBYTE | |
txgmii_intf.err.next = state == txstate.ERROR | |
txflowintf.ispaused = state == txstate.IDLE | |
clearcrc.next = state == txstate.IDLE | |
fcsen = txconfig[29] | |
calccrc.next = ((state == txstate.INFRAME) or | |
(state == txstate.PADDING)) and not fcsen | |
reseten = txconfig[31] | |
reset.next = sysreset or not reseten | |
@always_seq(txclientintf.clk.posedge, reset) | |
def curbyteinc(): | |
if state == txstate.IDLE: | |
curbyte.next = 1 | |
else: | |
curbyte.next = curbyte + 1 | |
@always_seq(txclientintf.clk.posedge, reset) | |
def pausecntrl(): | |
if txflowintf.pausereq: | |
pausereq.next = 1 | |
elif state == txstate.SENDPAUSE: | |
pausereq.next = 0 | |
@always_seq(txclientintf.clk.posedge, reset) | |
def transmitter(): | |
txen = txconfig[28] | |
if (state == txstate.IDLE) and txen: | |
data.next = 0x00 | |
dv.next = False | |
txgmii_intf.data.next = 0x00 | |
txgmii_intf.dv.next = False | |
if ifgwait > 0: | |
ifgwait.next = ifgwait - 1 | |
elif pausereq: | |
state.next = txstate.SENDPAUSE | |
elif not txflowintf.pauseapply and txclientintf.dv: | |
state.next = txstate.PREAMBLE | |
elif state == txstate.PREAMBLE: | |
data.next = 0x55 | |
dv.next = True | |
txgmii_intf.data.next = data | |
txgmii_intf.dv.next = dv | |
if curbyte == 7: | |
state.next = txstate.SFD | |
elif state == txstate.SFD: | |
data.next = 0xD5 | |
txgmii_intf.data.next = data | |
state.next = txstate.FIRSTBYTE | |
elif state == txstate.FIRSTBYTE: | |
ifgen = txconfig[25] | |
ifgwait.next = txclientintf.ifgdelay if ifgen else 12 | |
data.next = txclientintf.data | |
txgmii_intf.data.next = data | |
state.next = txstate.INFRAME | |
elif state == txstate.INFRAME: | |
data.next = txclientintf.data | |
txgmii_intf.data.next = data | |
if not txclientintf.dv: | |
jumboen = txconfig[30] | |
fcsen = txconfig[29] | |
vlanen = txconfig[27] | |
if curbyte > (1526 + vlanen*4) and not jumboen: | |
state.next = txstate.ERROR | |
elif fcsen: | |
state.next = txstate.IDLE | |
elif curbyte < 68: | |
state.next = txstate.PADDING | |
else: | |
state.next = txstate.CRC1 | |
elif state == txstate.PADDING: | |
if curbyte == 68: | |
state.next = txstate.CRC1 | |
elif state == txstate.CRC1: | |
txgmii_intf.data.next = crcout[32:24] | |
state.next = txstate.CRC2 | |
elif state == txstate.CRC2: | |
txgmii_intf.data.next = crcout[24:16] | |
state.next = txstate.CRC3 | |
elif state == txstate.CRC3: | |
txgmii_intf.data.next = crcout[16:8] | |
state.next = txstate.CRC4 | |
elif state == txstate.CRC4: | |
txgmii_intf.data.next = crcout[8:] | |
state.next = txstate.IDLE | |
elif state == txstate.ERROR: | |
state.next = txstate.IDLE | |
return assign, pausecntrl, curbyteinc, transmitter, crc32inst |
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