simple_2dlos.py

from random import randint
from myhdl import *

def m_2dlos(clock, reset, x, y, Nrows=4, Mcols=8):

    mem2d = [[Signal(intbv(randint(1, 7689), min=0, max=7690)) 
              for col in range(Mcols)] 
             for row in range(Nrows)]
    rcnt = Signal(modbv(0, min=0, max=4))
    ccnt = Signal(modbv(0, min=0, max=8))

    @always_seq(clock.posedge, reset=reset)
    def rtl():

        ccnt.next = ccnt + 1
        if ccnt == Mcols-1:
            rcnt.next = rcnt + 1

        mem2d[rcnt][ccnt].next = x
        y.next = mem2d[rcnt][ccnt]

    return rtl
    
def test_2dlos():
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)
    x = Signal(intbv(0, min=0, max=7690))
    y = Signal(intbv(1, min=0, max=7690))

    try:
        inst = conversion.verify(m_2dlos, clock, reset, x, y)
    except ConversionError as e:
#       assert e.kind == _error.ListAsPort
        print("Failed to convert to VHDL")
    except ToVerilogError as e:
        print("Failed to convert to Verilog")
    else:
        assert False
   

test_2dlos.py

import sys

from myhdl import *
from myhdl.conversion._toVerilog import ToVerilogError
from myhdl.conversion._toVHDL import ToVHDLError
from myhdl.conversion._toVHDL import ConversionError

from simple_2dlos import m_2dlos

def test_2dlos(tov='verilog'):
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)
    x = Signal(intbv(0, min=0, max=7690))
    y = Signal(intbv(1, min=0, max=7690))

    # simple test to verify the above functionally works, this
    # testbench is a non-convertible testbench!
    def _test():
        N,M = 4,8
        tbdut = m_2dlos(clock, reset, x, y, Nrows=N, Mcols=M)

        @always(delay(3))
        def tbclk():
            clock.next = not clock

        @instance
        def tbstim():
            x.next = 0
            reset.next = reset.active
            yield delay(33)
            reset.next = not reset.active
            yield clock.posedge
            yield clock.posedge

            # the default values are not 0
            for ii in range(N*M):
                assert y != 0
                yield clock.posedge

            for ii in range(N*M):
                assert y == 0
                yield clock.posedge

            raise StopSimulation

        return tbdut, tbclk, tbstim

    Simulation(_test()).run()

    # do the conversions, should fail    
    if 'ver' in tov.lower():
        try:
            toVerilog(m_2dlos, clock, reset, x, y)
        except ToVerilogError:
            print("Failed to convert to Verilog")

    elif 'vhd' in tov.lower():
        try:
            toVHDL(m_2dlos, clock, reset, x, y)
        except ConversionError:
            print("Failed to convert to VHDL")


if __name__ == '__main__':
    test_2dlos(sys.argv[1])