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from myhdl import block, instance, always_comb, Signal | |
@block | |
def orgate(input1, input2, output): | |
@always_comb | |
def orlogic(): | |
output.next = input1 | input2 | |
return orlogic | |
@block | |
def multior(inputs, output, n=2): | |
""" | |
inputs - boolean signal list of all inputs | |
output - ORed output | |
n - minimum 2 | |
""" | |
orinst = [None for _ in range(n-1)] | |
outinst = [Signal(bool(0)) for _ in range(n-1)] | |
orinst[0] = orgate(inputs[0], inputs[1], outinst[0]) | |
for i in range(1, n-1): | |
out = Signal(bool(0)) | |
orinst[i] = orgate(outinst[i-1], inputs[i+1], outinst[i]) | |
@always_comb | |
def orlogic(): | |
output.next = outinst[n-1] | |
return orlogic, orinst | |
@block | |
def test(): | |
inputs = [Signal(bool(0)) for _ in range(10)] | |
output = Signal(bool(0)) | |
inst = multior(inputs, output, n=10) | |
return inst | |
testinst = test() | |
testinst.convert(hdl='verilog') |
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