ncr5390 WIP changes

ncr5390.cpp.diff

diff --git a/src/devices/machine/ncr5390.cpp b/src/devices/machine/ncr5390.cpp
index 7a52d237982..76a135e20b5 100644
--- a/src/devices/machine/ncr5390.cpp
+++ b/src/devices/machine/ncr5390.cpp
@@ -421,7 +421,10 @@ void ncr5390_device::step(bool timeout)
 			break;
 
 		if((state & STATE_MASK) != INIT_XFR_RECV_PAD)
+		{
 			fifo_push(scsi_bus->data_r());
+			decrement_tcounter(1);
+		}
 		scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
 		state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
 		step(false);
@@ -620,7 +623,9 @@ void ncr5390_device::step(bool timeout)
 
 	case INIT_XFR_BUS_COMPLETE:
 		// wait for dma transfer to complete or fifo to drain
-		if (dma_command && !(status & S_TC0) && fifo_pos)
+		if ((dma_dir == DMA_OUT) && dma_command && !(status & S_TC0) && fifo_pos)
+			break;
+		if ((dma_dir == DMA_IN) && dma_command && (status & S_TC0) && fifo_pos)
 			break;
 
 		bus_complete();
@@ -794,6 +799,8 @@ uint8_t ncr5390_device::fifo_r()
 		memmove(fifo, fifo+1, fifo_pos);
 	} else
 		r = 0;
+
+	check_drq();
 	LOGMASKED(LOG_FIFO, "fifo_r 0x%02x fifo_pos %d (%s)\n", r, fifo_pos, machine().describe_context());
 	return r;
 }
@@ -803,6 +810,7 @@ void ncr5390_device::fifo_w(uint8_t data)
 	LOGMASKED(LOG_FIFO, "fifo_w 0x%02x fifo_pos %d (%s)\n", data, fifo_pos, machine().describe_context());
 	if(fifo_pos != 16)
 		fifo[fifo_pos++] = data;
+	check_drq();
 }
 
 uint8_t ncr5390_device::command_r()
@@ -813,7 +821,7 @@ uint8_t ncr5390_device::command_r()
 
 void ncr5390_device::command_w(uint8_t data)
 {
-	LOG("command_w %02x command_pos %d (%s)\n", data, command_pos, machine().describe_context());
+	LOGMASKED(LOG_COMMAND, "5390 command_w %02x command_pos %d (%s)\n", data, command_pos, machine().describe_context().c_str());
 	if(command_pos == 2) {
 		status |= S_GROSS_ERROR;
 		check_irq();
@@ -918,7 +926,7 @@ void ncr5390_device::start_command()
 		break;
 
 	case CI_XFER:
-		LOGMASKED(LOG_COMMAND, "Transfer information\n");
+		LOGMASKED(LOG_COMMAND, "Transfer information (%d bytes)\n", tcounter);
 		state = INIT_XFR;
 		xfr_phase = scsi_bus->ctrl_r() & S_PHASE_MASK;
 		dma_set(dma_command ? ((xfr_phase & S_INP) ? DMA_IN : DMA_OUT) : DMA_NONE);
@@ -1045,7 +1053,7 @@ void ncr5390_device::timeout_w(uint8_t data)
 uint8_t ncr5390_device::seq_step_r()
 {
 	LOG("seq_step_r %d (%s)\n", seq, machine().describe_context());
-	return seq;
+	return seq + 1;	// hack for Mac Quadra 700; our sequence steps don't correspond exactly to what the real chip returns
 }
 
 void ncr5390_device::sync_period_w(uint8_t data)
@@ -1125,7 +1133,7 @@ void ncr5390_device::check_drq()
 		break;
 
 	case DMA_IN: // device to memory
-		drq_state = !(status & S_TC0) && fifo_pos;
+		drq_state = (status & S_TC0) && (fifo_pos > 0);
 		break;
 
 	case DMA_OUT: // memory to device
@@ -1147,6 +1155,8 @@ void ncr5390_device::decrement_tcounter(int count)
 	tcounter -= count;
 	if (tcounter == 0)
 		status |= S_TC0;
+
+	check_drq();
 }
 
 /*
@@ -1271,7 +1281,7 @@ void ncr53c94_device::check_drq()
 			break;
 
 		case DMA_IN: // device to memory
-			drq_state = !(status & S_TC0) && fifo_pos > 1;
+			drq_state = (status & S_TC0) && fifo_pos;
 			break;
 
 		case DMA_OUT: // memory to device
@@ -1279,6 +1289,8 @@ void ncr53c94_device::check_drq()
 			break;
 		}
 
+		LOGMASKED(LOG_FIFO, "check_drq: %d (dir %d fifo_pos %d)\n", drq_state, dma_dir, fifo_pos);
+
 		if (drq_state != drq) {
 			drq = drq_state;
 			m_drq_handler(drq);