A simple example in VHDL

counter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity special_counter is
        port(
                clk : in std_logic;
                rst : in std_logic;
                output : out std_logic_vector(0 to 5)
        );  
end entity;

architecture behavioral of special_counter is
        signal count1 : std_logic_vector(0 to 2); 
        signal count2 : std_logic_vector(0 to 5); 

begin 
        count_process : process(clk, rst) 
        begin
                if rst = '1' then
                        count1 <= "000";
                        count2 <= "000000";
                elsif(rising_edge(clk)) then
                        count1 <= count1 + 1;
                        if count1 = "101" then
                                count2 <= count2 + 1;
                        end if; 
                end if; 
        end process;

        output <= count2;
end architecture;