A simple testbench for the counter in VHDL

counter_tb.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity special_counter_tb is
end entity;

architecture tb of special_counter_tb is
        component special_counter is
                port(
                        clk : in std_logic;
                        rst : in std_logic;
                        output : out std_logic_vector(0 to 5)
                );
        end component;

        -- inputs
        signal clk : std_logic;
        signal rst : std_logic;
        -- outputs
        signal output : std_logic_vector(0 to 5);

        constant clk_period : time := 10 ns;

        begin
                uut : special_counter port map(
                        clk => clk,
                        rst => rst,
                        output => output
                );

                clk_process : process
                begin
                        clk <= '0';
                        wait for clk_period/2;
clk <= '1';
                        wait for clk_period/2;
                end process;

                stimulus_process : process
                begin
                        rst <= '0';
                        wait for clk_period * 10;
                        rst <= not rst;
                        wait;
                end process;
end architecture;