rlane

#include "oort.h"  // https://github.com/rlane/oort3/blob/c/shared/c-api/oort.h

void tick() {
    write_f64(AccelerateX, 100.0);
    write_u64(Fire0, 1);
}

rlane

FROM rust:1.71.0-slim
WORKDIR /home
RUN apt-get update && \
    apt-get upgrade -y && \
    apt-get install -y git g++
RUN cargo install trunk wasm-opt
RUN apt install -y pkg-config
RUN apt install -y openssl
RUN apt install -y libssl-dev
RUN git clone https://github.com/rlane/oort3.git

rlane

/*
 * int lookup8_16(uint64_t *haystack, uint64_t needle)
 *
 * Returns the index of 'needle' in 'haystack', or -1
 * if not found. 'haystack' must be 16 elements in size.
 */
.global lookup8_16
lookup8_16:
xor    %eax,%eax

rlane

#!/usr/bin/env python
from flask import Flask
from flask import request
import json
import logging
import os
import errno
import argparse
import docker
from docker.utils import check_resource

rlane

#!/bin/bash
for S in submodules/*; do
    echo "Updating $S"
    git -C $S checkout --quiet master
    git -C $S pull --quiet origin master
    if ! git diff --quiet $S; then
        (echo "update $(basename $S)"; echo; git submodule summary $S) | git commit -F- $S
    fi
done

rlane

macro_rules! offset_of(
    ($typename:ident, $fieldname:ident) => (
        unsafe {
            let ptr = std::ptr::null::<$typename>();
            std::ptr::to_unsafe_ptr(&(*ptr).$fieldname).to_uint() -
                ptr.to_uint()
        }
    );
)

rlane

Dear Notch,

I'm writing to you on behalf of #0x10c-std community at Freenode IRC. We have been discussing various ideas for DCPU-16
for a couple of days now and in the process devised much improved DCPU-16 specification. Our rationale for changes is to
keep emulation complexity minimal, yet enable DCPU to be as flexible as possible for people to be able to do really cool
stuff with it.

As you see we also propose very simple interrupts mechanisim. We believe that it is vital for DCPU to become really
general-purpose processor since interrupts allow among many things: flexible timers or preemptive task-switching to
happen. However we kept the complexity minimal so DCPU is capable of only one interrupt handler. We believe the gains to DCPU capabilites are worth increased emulation cost.

rlane

mat4 translate(vec3 d)
{
	return mat4(1, 0, 0, d.x,
	            0, 1, 0, d.y,
	            0, 0, 1, d.z,
	            0, 0, 0, 1);
}

mat4 scale(float c)
{