|
/dts-v1/; |
|
|
|
/ { |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
compatible = "cvitek,cv181x"; |
|
model = "LicheeRv Nano"; |
|
|
|
adc@0300A100 { |
|
clk_source = <0x4130000>; |
|
clock-names = "i2sclk"; |
|
clocks = <0x0f 0x00>; |
|
compatible = "cvitek,cv182xaadc"; |
|
reg = <0x00 0x300a100 0x00 0x100>; |
|
}; |
|
|
|
aliases { |
|
ethernet0 = "/ethernet@4070000"; |
|
i2c0 = "/i2c@04000000"; |
|
i2c1 = "/i2c@04010000"; |
|
i2c2 = "/i2c@04020000"; |
|
i2c3 = "/i2c@04030000"; |
|
i2c4 = "/i2c@04040000"; |
|
serial0 = "/serial@04140000"; |
|
serial1 = "/serial@04150000"; |
|
serial2 = "/serial@04160000"; |
|
serial3 = "/serial@04170000"; |
|
serial4 = "/serial@041C0000"; |
|
}; |
|
|
|
audio_clock { |
|
#clock-cells = <0x00>; |
|
clock-frequency = <0x1770000>; |
|
compatible = "fixed-clock"; |
|
}; |
|
|
|
base { |
|
compatible = "cvitek,base"; |
|
reg = <0x00 0xa0c8000 0x00 0x20>; |
|
reg-names = "vip_sys"; |
|
}; |
|
|
|
bt_pin { |
|
compatible = "cvitek,bt-pin"; |
|
poweron-gpio = <0x08 0x09 0x00>; |
|
}; |
|
|
|
chosen { |
|
stdout-path = "serial0"; |
|
}; |
|
|
|
cif { |
|
clock-names = "clk_cam0\0clk_cam1\0clk_sys_2\0clk_mipimpll\0clk_disppll\0clk_fpll"; |
|
clocks = <0x02 0x58 0x02 0x59 0x02 0x85 0x02 0x03 0x02 0x05 0x02 0x02>; |
|
compatible = "cvitek,cif"; |
|
interrupt-names = "csi0\0csi1"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x1a 0x04 0x1b 0x04>; |
|
reg = <0x00 0xa0c2000 0x00 0x2000 0x00 0xa0d0000 0x00 0x1000 0x00 0xa0c4000 0x00 0x2000 0x00 0xa0c6000 0x00 0x2000 0x00 0x3001c30 0x00 0x30>; |
|
reg-names = "csi_mac0\0csi_wrap0\0csi_mac1\0csi_mac2\0pad_ctrl"; |
|
reset-names = "phy0\0phy1\0phy-apb0\0phy-apb1"; |
|
resets = <0x03 0x46 0x03 0x48 0x03 0x47 0x03 0x49>; |
|
snsr-reset = <0x08 0x01 0x01>; |
|
}; |
|
|
|
clk-reset-controller { |
|
#reset-cells = <0x01>; |
|
compatible = "cvitek,clk-reset"; |
|
reg = <0x00 0x3002000 0x00 0x08>; |
|
}; |
|
|
|
clock-controller { |
|
#clock-cells = <0x01>; |
|
clocks = <0x01>; |
|
compatible = "cvitek,cv181x-clk"; |
|
phandle = <0x02>; |
|
reg = <0x00 0x3002000 0x00 0x1000>; |
|
}; |
|
|
|
cooling { |
|
#cooling-cells = <0x02>; |
|
clock-names = "clk_cpu\0clk_tpu_axi"; |
|
clocks = <0x02 0x95 0x02 0x0c>; |
|
compatible = "sophgo,cooling"; |
|
dev-freqs = <0x32a9f880 0x1dcd6500 0x1954fc40 0x165a0bc0 0x1954fc40 0x11e1a300>; |
|
}; |
|
|
|
cpus { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
timebase-frequency = <0x17d7840>; |
|
|
|
cpu-map { |
|
|
|
cluster0 { |
|
|
|
core0 { |
|
cpu = <0x01>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu@0 { |
|
clock-frequency = <0x17d7840>; |
|
compatible = "riscv"; |
|
device_type = "cpu"; |
|
mmu-type = "riscv,sv39"; |
|
reg = <0x00>; |
|
riscv,isa = "rv64imafdvcsu"; |
|
status = "okay"; |
|
|
|
interrupt-controller { |
|
#interrupt-cells = <0x01>; |
|
compatible = "riscv,cpu-intc"; |
|
interrupt-controller; |
|
phandle = <0x13>; |
|
}; |
|
}; |
|
}; |
|
|
|
cv-sd@4310000 { |
|
64_addressing; |
|
bus-width = <0x04>; |
|
cap-mmc-highspeed; |
|
cap-sd-highspeed; |
|
compatible = "cvitek,cv181x-sd"; |
|
cvi-cd-gpios = <0x0e 0x0d 0x01>; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x24 0x04>; |
|
max-frequency = <0x17d7840>; |
|
min-frequency = <0x61a80>; |
|
no-1-8-v; |
|
no-mmc; |
|
no-sdio; |
|
pll_index = <0x06>; |
|
pll_reg = <0x3002070>; |
|
reg = <0x00 0x4310000 0x00 0x1000>; |
|
reg-names = "core_mem"; |
|
reset-names = "sdhci"; |
|
reset_tx_rx_phy; |
|
sd-uhs-sdr104; |
|
sd-uhs-sdr12; |
|
sd-uhs-sdr25; |
|
sd-uhs-sdr50; |
|
src-frequency = <0x165a0bc0>; |
|
}; |
|
|
|
cv-wd@0x3010000 { |
|
clocks = <0x06>; |
|
compatible = "snps,dw-wdt"; |
|
interrupts = <0x3a 0x04>; |
|
reg = <0x00 0x3010000 0x00 0x1000>; |
|
resets = <0x03 0x30>; |
|
}; |
|
|
|
cvi-spif@10000000 { |
|
bus-num = <0x00>; |
|
compatible = "cvitek,cvi-spif"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x5f 0x04>; |
|
reg = <0x00 0x10000000 0x00 0x10000000>; |
|
reg-names = "spif"; |
|
sck-div = <0x03>; |
|
sck_mhz = <0x12c>; |
|
spi-max-frequency = <0x47868c0>; |
|
|
|
spiflash { |
|
compatible = "jedec,spi-nor"; |
|
spi-rx-bus-width = <0x04>; |
|
spi-tx-bus-width = <0x04>; |
|
}; |
|
}; |
|
|
|
cvi_vc_drv { |
|
compatible = "cvitek,cvi_vc_drv"; |
|
reg = <0x00 0xb030000 0x00 0x100 0x00 0xb058000 0x00 0x100 0x00 0xb050000 0x00 0x400>; |
|
reg-names = "vc_ctrl\0vc_sbm\0vc_addr_remap"; |
|
}; |
|
|
|
cviaudio_core { |
|
compatible = "cvitek,audio"; |
|
}; |
|
|
|
cvifb { |
|
compatible = "cvitek,fb"; |
|
memory-region = <0x11>; |
|
reg = <0x00 0xa088000 0x00 0x1000>; |
|
reg-names = "disp"; |
|
status = "okay"; |
|
}; |
|
|
|
cvitek-ion { |
|
compatible = "cvitek,cvitek-ion"; |
|
|
|
heap_carveout@0 { |
|
compatible = "cvitek,carveout"; |
|
memory-region = <0x05>; |
|
}; |
|
}; |
|
|
|
dac@0300A000 { |
|
clock-names = "i2sclk"; |
|
clocks = <0x0f 0x00>; |
|
compatible = "cvitek,cv182xadac"; |
|
reg = <0x00 0x300a000 0x00 0x100>; |
|
status = "okay"; |
|
}; |
|
|
|
dma@0x4330000 { |
|
#dma-cells = <0x03>; |
|
axi_tr_width = <0x04>; |
|
block-ts = <0x0f>; |
|
block_size = <0x400>; |
|
chan_allocation_order = [00]; |
|
chan_priority = [01]; |
|
clock-names = "clk_sdma_axi"; |
|
clocks = <0x02 0x29>; |
|
compatible = "snps,dmac-bm"; |
|
data-width = <0x04 0x04>; |
|
dma-channels = [08]; |
|
dma-masters = [02]; |
|
dma-requests = [10]; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x1d 0x04>; |
|
phandle = <0x10>; |
|
reg = <0x00 0x4330000 0x00 0x1000>; |
|
}; |
|
|
|
dwa { |
|
clock-freq-vip-sys1 = <0x11e1a300>; |
|
clock-names = "clk_sys_0\0clk_sys_1\0clk_sys_2\0clk_sys_3\0clk_sys_4\0clk_dwa"; |
|
clocks = <0x02 0x4d 0x02 0x4e 0x02 0x85 0x02 0x97 0x02 0x98 0x02 0x64>; |
|
compatible = "cvitek,dwa"; |
|
interrupt-names = "dwa"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x1c 0x04>; |
|
reg = <0x00 0xa0c0000 0x00 0x1000>; |
|
reg-names = "dwa"; |
|
}; |
|
|
|
eth_csrclk { |
|
#clock-cells = <0x00>; |
|
clock-frequency = <0xee6b280>; |
|
clock-output-names = "eth_csrclk"; |
|
compatible = "fixed-clock"; |
|
phandle = <0x09>; |
|
}; |
|
|
|
eth_ptpclk { |
|
#clock-cells = <0x00>; |
|
clock-frequency = <0x2faf080>; |
|
clock-output-names = "eth_ptpclk"; |
|
compatible = "fixed-clock"; |
|
phandle = <0x0a>; |
|
}; |
|
|
|
ethernet@4070000 { |
|
clock-names = "stmmaceth\0ptp_ref"; |
|
clocks = <0x09 0x0a>; |
|
compatible = "cvitek,ethernet"; |
|
interrupt-names = "macirq"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x1f 0x04>; |
|
phy-mode = "rmii"; |
|
reg = <0x00 0x4070000 0x00 0x10000>; |
|
rx-fifo-depth = <0x2000>; |
|
snps,aal; |
|
snps,axi-config = <0x0b>; |
|
snps,mtl-rx-config = <0x0c>; |
|
snps,mtl-tx-config = <0x0d>; |
|
snps,multicast-filter-bins = <0x00>; |
|
snps,perfect-filter-entries = <0x01>; |
|
snps,rxpbl = <0x08>; |
|
snps,txpbl = <0x08>; |
|
tx-fifo-depth = <0x2000>; |
|
}; |
|
|
|
fast_image { |
|
compatible = "cvitek,rtos_image"; |
|
ion-size = <0x1600000>; |
|
reg = <0x00 0x8fe00000 0x00 0x200000>; |
|
reg-names = "rtos_region"; |
|
}; |
|
|
|
gpio-keys { |
|
compatible = "gpio-keys"; |
|
|
|
key-user { |
|
debounce-interval = <0x01>; |
|
gpios = <0x0e 0x1e 0x01>; |
|
label = "User Key"; |
|
linux,code = <0x1af>; |
|
}; |
|
}; |
|
|
|
gpio@03020000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
compatible = "snps,dw-apb-gpio"; |
|
reg = <0x00 0x3020000 0x00 0x1000>; |
|
|
|
gpio-controller@0 { |
|
#gpio-cells = <0x02>; |
|
bank-name = "porta"; |
|
compatible = "snps,dw-apb-gpio-port"; |
|
gpio-controller; |
|
interrupt-controller; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x3c 0x04>; |
|
phandle = <0x0e>; |
|
reg = <0x00>; |
|
snps,nr-gpios = <0x20>; |
|
}; |
|
}; |
|
|
|
gpio@03021000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
compatible = "snps,dw-apb-gpio"; |
|
reg = <0x00 0x3021000 0x00 0x1000>; |
|
|
|
gpio-controller@1 { |
|
#gpio-cells = <0x02>; |
|
bank-name = "portb"; |
|
compatible = "snps,dw-apb-gpio-port"; |
|
gpio-controller; |
|
interrupt-controller; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x3d 0x04>; |
|
phandle = <0x07>; |
|
reg = <0x00>; |
|
snps,nr-gpios = <0x20>; |
|
}; |
|
}; |
|
|
|
gpio@03022000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
compatible = "snps,dw-apb-gpio"; |
|
reg = <0x00 0x3022000 0x00 0x1000>; |
|
|
|
gpio-controller@2 { |
|
#gpio-cells = <0x02>; |
|
bank-name = "portc"; |
|
compatible = "snps,dw-apb-gpio-port"; |
|
gpio-controller; |
|
interrupt-controller; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x3e 0x04>; |
|
reg = <0x00>; |
|
snps,nr-gpios = <0x20>; |
|
}; |
|
}; |
|
|
|
gpio@03023000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
compatible = "snps,dw-apb-gpio"; |
|
reg = <0x00 0x3023000 0x00 0x1000>; |
|
|
|
gpio-controller@3 { |
|
#gpio-cells = <0x02>; |
|
bank-name = "portd"; |
|
compatible = "snps,dw-apb-gpio-port"; |
|
gpio-controller; |
|
interrupt-controller; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x3f 0x04>; |
|
reg = <0x00>; |
|
snps,nr-gpios = <0x20>; |
|
}; |
|
}; |
|
|
|
gpio@05021000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
compatible = "snps,dw-apb-gpio"; |
|
reg = <0x00 0x5021000 0x00 0x1000>; |
|
|
|
gpio-controller@4 { |
|
#gpio-cells = <0x02>; |
|
bank-name = "porte"; |
|
compatible = "snps,dw-apb-gpio-port"; |
|
gpio-controller; |
|
interrupt-controller; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x46 0x04>; |
|
phandle = <0x08>; |
|
reg = <0x00>; |
|
snps,nr-gpios = <0x20>; |
|
}; |
|
}; |
|
|
|
i2c5@gpio { |
|
compatible = "i2c-gpio"; |
|
i2c-gpio,delay-us = <0x05>; |
|
scl-gpios = <0x0e 0x0f 0x06>; |
|
sda-gpios = <0x0e 0x1b 0x06>; |
|
status = "okay"; |
|
}; |
|
|
|
i2c@04000000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
clock-frequency = <0x61a80>; |
|
clocks = <0x02 0x6f>; |
|
compatible = "snps,designware-i2c"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x31 0x04>; |
|
reg = <0x00 0x4000000 0x00 0x1000>; |
|
reset-names = "i2c0"; |
|
resets = <0x03 0x1b>; |
|
status = "okay"; |
|
}; |
|
|
|
i2c@04010000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
clock-frequency = <0x61a80>; |
|
clocks = <0x02 0x6f>; |
|
compatible = "snps,designware-i2c"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x32 0x04>; |
|
reg = <0x00 0x4010000 0x00 0x1000>; |
|
reset-names = "i2c1"; |
|
resets = <0x03 0x1c>; |
|
status = "okay"; |
|
}; |
|
|
|
i2c@04020000 { |
|
clock-frequency = <0x186a0>; |
|
clocks = <0x02 0x6f>; |
|
compatible = "snps,designware-i2c"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x33 0x04>; |
|
reg = <0x00 0x4020000 0x00 0x1000>; |
|
reset-names = "i2c2"; |
|
resets = <0x03 0x1d>; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c@04030000 { |
|
clock-frequency = <0x61a80>; |
|
clocks = <0x02 0x6f>; |
|
compatible = "snps,designware-i2c"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x34 0x04>; |
|
reg = <0x00 0x4030000 0x00 0x1000>; |
|
reset-names = "i2c3"; |
|
resets = <0x03 0x1e>; |
|
status = "okay"; |
|
}; |
|
|
|
i2c@04040000 { |
|
clock-frequency = <0x61a80>; |
|
clocks = <0x02 0x6f>; |
|
compatible = "snps,designware-i2c"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x35 0x04>; |
|
reg = <0x00 0x4040000 0x00 0x1000>; |
|
reset-names = "i2c4"; |
|
resets = <0x03 0x1f>; |
|
scl-gpios = <0x07 0x01 0x00>; |
|
scl-pinmux = <0x30010f0 0x02 0x03>; |
|
sda-gpios = <0x07 0x02 0x00>; |
|
sda-pinmux = <0x30010f4 0x02 0x03>; |
|
status = "okay"; |
|
|
|
gt9xx@14 { |
|
compatible = "goodix,gt9xx"; |
|
goodix,irq-gpio = <0x08 0x03 0x00>; |
|
goodix,rst-gpio = <0x08 0x04 0x00>; |
|
reg = <0x14>; |
|
status = "okay"; |
|
}; |
|
|
|
hynitron@5a { |
|
compatible = "hynitron,hyn_ts\0hyn,7xx"; |
|
display-coords = <0x00 0x00 0x1e0 0x280>; |
|
hynitron,display-coords = <0x170 0x228>; |
|
hynitron,irq-gpio = <0x08 0x03 0x00>; |
|
hynitron,max-touch-number = <0x05>; |
|
hynitron,reset-gpio = <0x08 0x04 0x00>; |
|
irq-gpio = <0x08 0x03 0x00>; |
|
max-touch-number = <0x05>; |
|
pos-swap = <0x00>; |
|
posx-reverse = <0x01>; |
|
posy-reverse = <0x01>; |
|
reg = <0x5a>; |
|
reset-gpio = <0x08 0x04 0x00>; |
|
status = "okay"; |
|
}; |
|
}; |
|
|
|
i2s@04100000 { |
|
#sound-dai-cells = <0x00>; |
|
capability = "rx"; |
|
clock-names = "i2sclk"; |
|
clocks = <0x0f 0x00>; |
|
compatible = "cvitek,cv1835-i2s"; |
|
dev-id = <0x00>; |
|
dma-names = "rx"; |
|
dmas = <0x10 0x00 0x01 0x01>; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x28 0x04>; |
|
mclk_out = "false"; |
|
reg = <0x00 0x4100000 0x00 0x2000>; |
|
}; |
|
|
|
i2s@04130000 { |
|
#sound-dai-cells = <0x00>; |
|
capability = "tx"; |
|
clock-names = "i2sclk"; |
|
clocks = <0x0f 0x00>; |
|
compatible = "cvitek,cv1835-i2s"; |
|
dev-id = <0x03>; |
|
dma-names = "tx"; |
|
dmas = <0x10 0x07 0x01 0x01>; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x2b 0x04>; |
|
mclk_out = "true"; |
|
reg = <0x00 0x4130000 0x00 0x2000>; |
|
}; |
|
|
|
i2s_mclk { |
|
#clock-cells = <0x00>; |
|
clock-frequency = <0x1770000>; |
|
clock-output-names = "i2s_mclk"; |
|
compatible = "fixed-clock"; |
|
phandle = <0x0f>; |
|
}; |
|
|
|
i2s_subsys { |
|
clock-names = "i2sclk\0clk_a0pll\0clk_sdma_aud0\0clk_sdma_aud1\0clk_sdma_aud2\0clk_sdma_aud3"; |
|
clocks = <0x0f 0x02 0x04 0x02 0x2a 0x02 0x2b 0x02 0x2c 0x02 0x2d>; |
|
compatible = "cvitek,i2s_tdm_subsys"; |
|
master_base = <0x4110000>; |
|
reg = <0x00 0x4108000 0x00 0x100>; |
|
}; |
|
|
|
ive { |
|
compatible = "cvitek,ive"; |
|
interrupt-names = "ive_irq"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x61 0x04>; |
|
reg = <0x00 0xa0a0000 0x00 0x3100>; |
|
reg-names = "ive_base"; |
|
}; |
|
|
|
jpu { |
|
clock-names = "clk_axi_video_codec\0clk_jpeg\0clk_apb_jpeg\0clk_vc_src0\0clk_vc_src1\0clk_vc_src2\0clk_cfg_reg_vc"; |
|
clocks = <0x02 0x50 0x02 0x54 0x02 0x55 0x02 0x51 0x02 0x84 0x02 0x8b 0x02 0x88>; |
|
compatible = "cvitek,asic-jpeg"; |
|
interrupt-names = "jpeg"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x14 0x04>; |
|
reg = <0x00 0xb000000 0x00 0x300 0x00 0xb030000 0x00 0x100 0x00 0xb058000 0x00 0x100>; |
|
reg-names = "jpeg\0vc_ctrl\0vc_sbm"; |
|
reset-names = "jpeg"; |
|
resets = <0x03 0x04>; |
|
}; |
|
|
|
leds { |
|
compatible = "gpio-leds"; |
|
|
|
led-user { |
|
gpios = <0x0e 0x0e 0x00>; |
|
linux,default-trigger = "activity"; |
|
}; |
|
}; |
|
|
|
memory@80000000 { |
|
device_type = "memory"; |
|
reg = <0x00 0x80000000 0x00 0xfe00000>; |
|
}; |
|
|
|
mipi_tx { |
|
clock-names = "clk_disp\0clk_dsi"; |
|
clocks = <0x02 0x66 0x02 0x67>; |
|
compatible = "cvitek,mipi_tx"; |
|
status = "okay"; |
|
}; |
|
|
|
mon { |
|
compatible = "cvitek,mon"; |
|
interrupt-names = "mon_irq"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x5d 0x04>; |
|
reg = <0x00 0x1040000 0x00 0x1000 0x00 0x8004000 0x00 0x1000 0x00 0x8006000 0x00 0x1000 0x00 0x8008000 0x00 0x1000 0x00 0x800a000 0x00 0x1000>; |
|
reg-names = "pcmon\0ddr_ctrl\0ddr_phyd\0ddr_aximon\0ddr_top"; |
|
}; |
|
|
|
oscillator { |
|
#clock-cells = <0x00>; |
|
clock-frequency = <0x17d7840>; |
|
clock-output-names = "osc"; |
|
compatible = "fixed-clock"; |
|
phandle = <0x01>; |
|
}; |
|
|
|
pclk { |
|
#clock-cells = <0x00>; |
|
clock-frequency = <0x17d7840>; |
|
compatible = "fixed-clock"; |
|
phandle = <0x06>; |
|
}; |
|
|
|
pdm@0x041D0C00 { |
|
clock-names = "i2sclk"; |
|
clocks = <0x0f 0x00>; |
|
compatible = "cvitek,cv1835pdm"; |
|
reg = <0x00 0x41d0c00 0x00 0x100>; |
|
}; |
|
|
|
pwm@3060000 { |
|
#pwm-cells = <0x04>; |
|
clocks = <0x02 0x30>; |
|
compatible = "cvitek,cvi-pwm"; |
|
reg = <0x00 0x3060000 0x00 0x1000>; |
|
status = "okay"; |
|
}; |
|
|
|
pwm@3061000 { |
|
#pwm-cells = <0x04>; |
|
clocks = <0x02 0x30>; |
|
compatible = "cvitek,cvi-pwm"; |
|
reg = <0x00 0x3061000 0x00 0x1000>; |
|
status = "okay"; |
|
}; |
|
|
|
pwm@3062000 { |
|
#pwm-cells = <0x04>; |
|
clocks = <0x02 0x30>; |
|
compatible = "cvitek,cvi-pwm"; |
|
reg = <0x00 0x3062000 0x00 0x1000>; |
|
status = "okay"; |
|
}; |
|
|
|
pwm@3063000 { |
|
#pwm-cells = <0x04>; |
|
clocks = <0x02 0x30>; |
|
compatible = "cvitek,cvi-pwm"; |
|
reg = <0x00 0x3063000 0x00 0x1000>; |
|
}; |
|
|
|
reserved-memory { |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
ranges; |
|
|
|
cvifb { |
|
alloc-ranges = <0x00 0x8ab30000 0x00 0x7d0000>; |
|
phandle = <0x11>; |
|
size = <0x00 0x7d0000>; |
|
status = "okay"; |
|
}; |
|
|
|
ion { |
|
compatible = "ion-region"; |
|
phandle = <0x05>; |
|
size = <0x00 0x4b00000>; |
|
}; |
|
}; |
|
|
|
reset-controller { |
|
#reset-cells = <0x01>; |
|
compatible = "cvitek,reset"; |
|
phandle = <0x03>; |
|
reg = <0x00 0x3003000 0x00 0x10>; |
|
}; |
|
|
|
restart-controller { |
|
compatible = "cvitek,restart"; |
|
reg = <0x00 0x5025000 0x00 0x2000>; |
|
}; |
|
|
|
rgn { |
|
compatible = "cvitek,rgn"; |
|
}; |
|
|
|
rtc { |
|
clock-names = "clk_rtc"; |
|
clocks = <0x02 0x10>; |
|
compatible = "cvitek,rtc"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x11 0x04>; |
|
reg = <0x00 0x5026000 0x00 0x1000 0x00 0x5025000 0x00 0x1000>; |
|
}; |
|
|
|
rtos_cmdqu { |
|
compatible = "cvitek,rtos_cmdqu"; |
|
interrupt-names = "mailbox"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x65 0x04>; |
|
reg = <0x00 0x1900000 0x00 0x1000>; |
|
reg-names = "mailbox"; |
|
}; |
|
|
|
rx-queues-config { |
|
phandle = <0x0c>; |
|
snps,rx-queues-to-use = <0x01>; |
|
|
|
queue0 { |
|
}; |
|
}; |
|
|
|
saradc { |
|
clock-names = "clk_saradc"; |
|
clocks = <0x02 0x12>; |
|
compatible = "cvitek,saradc"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x64 0x01>; |
|
reg = <0x00 0x30f0000 0x00 0x1000 0x00 0x502c000 0x00 0x1000>; |
|
reg-names = "top_domain_saradc\0rtc_domain_saradc"; |
|
reset-names = "res_saradc"; |
|
resets = <0x03 0x34>; |
|
}; |
|
|
|
serial@04140000 { |
|
clocks = <0x02 0x36>; |
|
compatible = "snps,dw-apb-uart"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x2c 0x04>; |
|
reg = <0x00 0x4140000 0x00 0x1000>; |
|
reg-io-width = <0x04>; |
|
reg-shift = <0x02>; |
|
status = "okay"; |
|
}; |
|
|
|
serial@04150000 { |
|
clocks = <0x02 0x38>; |
|
compatible = "snps,dw-apb-uart"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x2d 0x04>; |
|
reg = <0x00 0x4150000 0x00 0x1000>; |
|
reg-io-width = <0x04>; |
|
reg-shift = <0x02>; |
|
status = "okay"; |
|
}; |
|
|
|
serial@04160000 { |
|
clocks = <0x02 0x3a>; |
|
compatible = "snps,dw-apb-uart"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x2e 0x04>; |
|
reg = <0x00 0x4160000 0x00 0x1000>; |
|
reg-io-width = <0x04>; |
|
reg-shift = <0x02>; |
|
status = "okay"; |
|
}; |
|
|
|
serial@04170000 { |
|
clocks = <0x02 0x3c>; |
|
compatible = "snps,dw-apb-uart"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x2f 0x04>; |
|
reg = <0x00 0x4170000 0x00 0x1000>; |
|
reg-io-width = <0x04>; |
|
reg-shift = <0x02>; |
|
status = "okay"; |
|
}; |
|
|
|
serial@041C0000 { |
|
clock-frequency = <0x17d7840>; |
|
compatible = "snps,dw-apb-uart"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x30 0x04>; |
|
reg = <0x00 0x41c0000 0x00 0x1000>; |
|
reg-io-width = <0x04>; |
|
reg-shift = <0x02>; |
|
status = "disabled"; |
|
}; |
|
|
|
soc { |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
compatible = "simple-bus"; |
|
ranges; |
|
|
|
clint@74000000 { |
|
clint,has-no-64bit-mmio; |
|
compatible = "riscv,clint0"; |
|
interrupts-extended = <0x13 0x03 0x13 0x07>; |
|
reg = <0x00 0x74000000 0x00 0x10000>; |
|
}; |
|
|
|
interrupt-controller@70000000 { |
|
#address-cells = <0x00>; |
|
#interrupt-cells = <0x02>; |
|
compatible = "riscv,plic0"; |
|
interrupt-controller; |
|
interrupts-extended = <0x13 0xffffffff 0x13 0x09>; |
|
phandle = <0x04>; |
|
reg = <0x00 0x70000000 0x00 0x4000000>; |
|
reg-names = "control"; |
|
riscv,max-priority = <0x07>; |
|
riscv,ndev = <0x65>; |
|
}; |
|
}; |
|
|
|
sound_adc { |
|
compatible = "cvitek,cv182xa-adc"; |
|
cvi,card_name = "cv182xa_adc"; |
|
cvi,model = "CV182XA"; |
|
}; |
|
|
|
sound_dac { |
|
compatible = "cvitek,cv182xa-dac"; |
|
cvi,card_name = "cv182xa_dac"; |
|
cvi,model = "CV182XA"; |
|
}; |
|
|
|
spi0@04180000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
clocks = <0x02 0x6e>; |
|
compatible = "snps,dw-apb-ssi"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x36 0x04>; |
|
num-cs = <0x01>; |
|
reg = <0x00 0x4180000 0x00 0x10000>; |
|
status = "okay"; |
|
|
|
spidev@0 { |
|
compatible = "rohm,dh2228fv"; |
|
reg = <0x00>; |
|
spi-max-frequency = <0xf4240>; |
|
}; |
|
}; |
|
|
|
spi1@04190000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
clocks = <0x02 0x6e>; |
|
compatible = "snps,dw-apb-ssi"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x37 0x04>; |
|
num-cs = <0x01>; |
|
reg = <0x00 0x4190000 0x00 0x10000>; |
|
status = "okay"; |
|
|
|
spidev@0 { |
|
compatible = "rohm,dh2228fv"; |
|
reg = <0x00>; |
|
spi-max-frequency = <0xf4240>; |
|
}; |
|
}; |
|
|
|
spi2@041A0000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
clocks = <0x02 0x6e>; |
|
compatible = "snps,dw-apb-ssi"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x38 0x04>; |
|
num-cs = <0x01>; |
|
reg = <0x00 0x41a0000 0x00 0x10000>; |
|
status = "okay"; |
|
|
|
spidev@0 { |
|
compatible = "rohm,dh2228fv"; |
|
reg = <0x00>; |
|
spi-max-frequency = <0xf4240>; |
|
}; |
|
}; |
|
|
|
spi3@041B0000 { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
clocks = <0x02 0x6e>; |
|
compatible = "snps,dw-apb-ssi"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x39 0x04>; |
|
num-cs = <0x01>; |
|
reg = <0x00 0x41b0000 0x00 0x10000>; |
|
status = "okay"; |
|
|
|
spidev@0 { |
|
compatible = "rohm,dh2228fv"; |
|
reg = <0x00>; |
|
spi-max-frequency = <0xf4240>; |
|
}; |
|
}; |
|
|
|
spi4@gpio { |
|
compatible = "spi-gpio"; |
|
cs-gpio = <0x0e 0x18 0x01>; |
|
miso-gpio = <0x0e 0x17 0x00>; |
|
mosi-gpio = <0x0e 0x19 0x00>; |
|
num-chipselects = <0x01>; |
|
sck-gpio = <0x0e 0x16 0x00>; |
|
status = "okay"; |
|
|
|
spidev@0 { |
|
compatible = "spidev"; |
|
reg = <0x00>; |
|
}; |
|
}; |
|
|
|
stmmac-axi-config { |
|
phandle = <0x0b>; |
|
snps,blen = <0x04 0x08 0x10 0x00 0x00 0x00 0x00>; |
|
snps,rd_osr_lmt = <0x02>; |
|
snps,wr_osr_lmt = <0x01>; |
|
}; |
|
|
|
sys { |
|
compatible = "cvitek,sys"; |
|
}; |
|
|
|
sysdma_remap { |
|
ch-remap = <0x00 0x05 0x02 0x03 0x26 0x26 0x04 0x07>; |
|
compatible = "cvitek,sysdma_remap"; |
|
int_mux = <0x7fc00>; |
|
int_mux_base = <0x3000298>; |
|
reg = <0x00 0x3000154 0x00 0x10>; |
|
}; |
|
|
|
thermal-zones { |
|
|
|
soc_thermal_0 { |
|
polling-delay = <0x3e8>; |
|
polling-delay-passive = <0x3e8>; |
|
thermal-sensors = <0x12 0x00>; |
|
|
|
trips { |
|
|
|
soc_thermal_crtical_0 { |
|
hysteresis = <0x00>; |
|
temperature = <0x1fbd0>; |
|
type = "critical"; |
|
}; |
|
|
|
soc_thermal_trip_0 { |
|
hysteresis = <0x1388>; |
|
temperature = <0x1adb0>; |
|
type = "passive"; |
|
}; |
|
|
|
soc_thermal_trip_1 { |
|
hysteresis = <0x1388>; |
|
temperature = <0x1d4c0>; |
|
type = "passive"; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
thermal@030E0000 { |
|
#thermal-sensor-cells = <0x01>; |
|
clock-names = "clk_tempsen"; |
|
clocks = <0x02 0x11>; |
|
compatible = "cvitek,cv181x-thermal"; |
|
interrupt-names = "tempsen"; |
|
interrupts = <0x10 0x04>; |
|
phandle = <0x12>; |
|
reg = <0x00 0x30e0000 0x00 0x10000>; |
|
reset-names = "tempsen"; |
|
}; |
|
|
|
top_misc_ctrl@3000000 { |
|
compatible = "syscon"; |
|
reg = <0x00 0x3000000 0x00 0x8000>; |
|
}; |
|
|
|
tpu { |
|
clock-names = "clk_tpu_axi\0clk_tpu_fab"; |
|
clocks = <0x02 0x0c 0x02 0x0d>; |
|
compatible = "cvitek,tpu"; |
|
interrupt-names = "tiu_irq\0tdma_irq"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x4b 0x04 0x4c 0x04>; |
|
reg = <0x00 0xc100000 0x00 0x1000 0x00 0xc101000 0x00 0x1000>; |
|
reg-names = "tdma\0tiu"; |
|
reset-names = "res_tdma\0res_tpu\0res_tpusys"; |
|
resets = <0x03 0x07 0x03 0x08 0x03 0x09>; |
|
}; |
|
|
|
tx-queues-config { |
|
phandle = <0x0d>; |
|
snps,tx-queues-to-use = <0x01>; |
|
|
|
queue0 { |
|
}; |
|
}; |
|
|
|
usb@04340000 { |
|
clock-names = "clk_axi\0clk_apb\0clk_125m\0clk_33k\0clk_12m"; |
|
clocks = <0x02 0x44 0x02 0x45 0x02 0x46 0x02 0x47 0x02 0x48>; |
|
compatible = "cvitek,cv182x-usb"; |
|
dr_mode = "otg"; |
|
g-np-tx-fifo-size = <0x20>; |
|
g-rx-fifo-size = <0x218>; |
|
g-tx-fifo-size = <0x300 0x200 0x200 0x180 0x80 0x80>; |
|
g-use-dma; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x1e 0x04>; |
|
reg = <0x00 0x4340000 0x00 0x10000 0x00 0x3006000 0x00 0x58>; |
|
status = "okay"; |
|
vbus-gpio = <0x07 0x06 0x00>; |
|
}; |
|
|
|
vcodec { |
|
clock-names = "clk_axi_video_codec\0clk_h264c\0clk_apb_h264c\0clk_h265c\0clk_apb_h265c\0clk_vc_src0\0clk_vc_src1\0clk_vc_src2\0clk_cfg_reg_vc"; |
|
clocks = <0x02 0x50 0x02 0x52 0x02 0x56 0x02 0x53 0x02 0x57 0x02 0x51 0x02 0x84 0x02 0x8b 0x02 0x88>; |
|
compatible = "cvitek,asic-vcodec"; |
|
interrupt-names = "h265\0h264\0sbm"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x16 0x04 0x15 0x04 0x17 0x04>; |
|
reg = <0x00 0xb020000 0x00 0x10000 0x00 0xb010000 0x00 0x10000 0x00 0xb030000 0x00 0x100 0x00 0xb058000 0x00 0x100 0x00 0xb050000 0x00 0x400>; |
|
reg-names = "h265\0h264\0vc_ctrl\0vc_sbm\0vc_addr_remap"; |
|
}; |
|
|
|
vi { |
|
clock-freq-vip-sys1 = <0x11e1a300>; |
|
clock-names = "clk_sys_0\0clk_sys_1\0clk_sys_2\0clk_sys_3\0clk_axi\0clk_csi_be\0clk_raw\0clk_isp_top\0clk_csi_mac0\0clk_csi_mac1\0clk_csi_mac2"; |
|
clocks = <0x02 0x4d 0x02 0x4e 0x02 0x85 0x02 0x97 0x02 0x4c 0x02 0x90 0x02 0x9a 0x02 0x5c 0x02 0x5a 0x02 0x5b 0x02 0x9c>; |
|
compatible = "cvitek,vi"; |
|
interrupt-names = "isp"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x18 0x04>; |
|
reg = <0x00 0xa000000 0x00 0x80000>; |
|
}; |
|
|
|
vo { |
|
clock-names = "clk_disp\0clk_dsi\0clk_bt"; |
|
clocks = <0x02 0x66 0x02 0x67 0x02 0x65>; |
|
compatible = "cvitek,vo"; |
|
pwm-gpio = <0x08 0x02 0x01>; |
|
reg = <0x00 0xa080000 0x00 0x10000 0x00 0xa0c8000 0x00 0xa0 0x00 0xa0d1000 0x00 0x100>; |
|
reg-names = "sc\0vip_sys\0dphy"; |
|
reset-gpio = <0x08 0x00 0x01>; |
|
}; |
|
|
|
vpss { |
|
clock-freq-vip-sys1 = <0x11e1a300>; |
|
clock-names = "clk_sys_0\0clk_sys_1\0clk_sys_2\0clk_img_d\0clk_img_v\0clk_sc_top\0clk_sc_d\0clk_sc_v1\0clk_sc_v2\0clk_sc_v3"; |
|
clocks = <0x02 0x4d 0x02 0x4e 0x02 0x85 0x02 0x5d 0x02 0x5e 0x02 0x5f 0x02 0x60 0x02 0x61 0x02 0x62 0x02 0x63>; |
|
compatible = "cvitek,vpss"; |
|
interrupt-names = "sc"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x19 0x04>; |
|
reg = <0x00 0xa080000 0x00 0x10000 0x00 0xa0d1000 0x00 0x100>; |
|
reg-names = "sc"; |
|
}; |
|
|
|
wiegand0 { |
|
clock-names = "clk_wgn\0clk_wgn1"; |
|
clocks = <0x02 0x7e 0x02 0x7f>; |
|
compatible = "cvitek,wiegand"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x40 0x04>; |
|
reg = <0x00 0x3030000 0x00 0x1000>; |
|
reg-names = "wiegand"; |
|
reset-names = "res_wgn"; |
|
resets = <0x03 0x56>; |
|
}; |
|
|
|
wiegand1 { |
|
clock-names = "clk_wgn\0clk_wgn1"; |
|
clocks = <0x02 0x7e 0x02 0x80>; |
|
compatible = "cvitek,wiegand"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x41 0x04>; |
|
reg = <0x00 0x3031000 0x00 0x1000>; |
|
reg-names = "wiegand"; |
|
reset-names = "res_wgn"; |
|
resets = <0x03 0x57>; |
|
}; |
|
|
|
wiegand2 { |
|
clock-names = "clk_wgn\0clk_wgn1"; |
|
clocks = <0x02 0x7e 0x02 0x81>; |
|
compatible = "cvitek,wiegand"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x42 0x04>; |
|
reg = <0x00 0x3032000 0x00 0x1000>; |
|
reg-names = "wiegand"; |
|
reset-names = "res_wgn"; |
|
resets = <0x03 0x58>; |
|
}; |
|
|
|
wifi-sd@4320000 { |
|
64_addressing; |
|
bus-width = <0x04>; |
|
compatible = "cvitek,cv181x-sdio"; |
|
interrupt-parent = <0x04>; |
|
interrupts = <0x26 0x04>; |
|
max-frequency = <0x2faf080>; |
|
min-frequency = <0x61a80>; |
|
no-mmc; |
|
no-sd; |
|
non-removable; |
|
pll_index = <0x07>; |
|
pll_reg = <0x300207c>; |
|
reg = <0x00 0x4320000 0x00 0x1000>; |
|
reg_names = "core_mem"; |
|
reset_tx_rx_phy; |
|
src-frequency = <0x165a0bc0>; |
|
status = "okay"; |
|
}; |
|
|
|
wifi_pin { |
|
compatible = "cvitek,wifi-pin"; |
|
poweron-gpio = <0x08 0x02 0x00>; |
|
wakeup-gpio = <0x08 0x06 0x00>; |
|
}; |
|
}; |
