Created
April 19, 2017 01:09
-
-
Save rndmcnlly/7b9ed09b8bc5a1a8936d108e77047c9c to your computer and use it in GitHub Desktop.
Check if two combinatorial circuits defined in Verilog are behaviorally equivalent (synthesis to a sea of gates using Yosys and search using Potassco)
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment