example vhdl state machine

gistfile1.vhdl

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY Custom_FSM IS
	PORT
    (
clk  :  IN  STD_LOGIC;
init : IN  STD_LOGIC;
x1 :  IN  STD_LOGIC;
y1 :  OUT  STD_LOGIC;
y2 :  OUT  STD_LOGIC
    );
END Custom_FSM;

ARCHITECTURE Custom_FSM_Architecture OF Custom_FSM IS 

SIGNAL q_synt0 :  STD_LOGIC;
SIGNAL q_synt1 :  STD_LOGIC;

BEGIN

y1 <= NOT((NOT(q_synt0) OR q_synt1 OR '0'));
y2 <= NOT((q_synt0 OR NOT(q_synt1) OR '0'));

PROCESS(clk)
VARIABLE synt_var_q_synt0 : STD_LOGIC;
BEGIN
synt_var_q_synt0 := q_synt0;
IF (RISING_EDGE(clk)) THEN
	synt_var_q_synt0 := (NOT(synt_var_q_synt0) AND (  
        NOT((q_synt0 OR q_synt1 OR NOT(x1)))  
        )) OR ((synt_var_q_synt0) AND 
        NOT( NOT((NOT(q_synt0) OR NOT(q_synt1) OR '0'))  ));
END IF;
q_synt0 <= init AND synt_var_q_synt0;
END PROCESS;


PROCESS(clk)
VARIABLE synt_var_q_synt1 : STD_LOGIC;
BEGIN
synt_var_q_synt1 := q_synt1;
IF (RISING_EDGE(clk)) THEN
	synt_var_q_synt1 := (NOT(synt_var_q_synt1) AND (  
        NOT((NOT(q_synt0) OR q_synt1 OR '0'))  
        )) OR ((synt_var_q_synt1) AND 
        NOT( NOT((q_synt0 OR NOT(q_synt1) OR '0'))  ));
END IF;
q_synt1 <= init AND synt_var_q_synt1;
END PROCESS;


END Custom_FSM_Architecture;